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-rw-r--r--board/nvidia/common/board.c58
-rw-r--r--board/nvidia/common/board.h4
-rw-r--r--board/nvidia/harmony/harmony.c57
-rw-r--r--board/nvidia/seaboard/seaboard.c81
-rw-r--r--board/nvidia/ventana/Makefile49
5 files changed, 148 insertions, 101 deletions
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 370a25906d..c806a6b3cb 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -33,10 +33,6 @@
#include <asm/arch/uart.h>
#include "board.h"
-#ifdef CONFIG_TEGRA2_MMC
-#include <mmc.h>
-#endif
-
DECLARE_GLOBAL_DATA_PTR;
const struct tegra2_sysinfo sysinfo = {
@@ -100,33 +96,6 @@ static void pin_mux_uart(void)
#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
}
-#ifdef CONFIG_TEGRA2_MMC
-/*
- * Routine: pin_mux_mmc
- * Description: setup the pin muxes/tristate values for the SDMMC(s)
- */
-static void pin_mux_mmc(void)
-{
- /* SDMMC4: config 3, x8 on 2nd set of pins */
- pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4);
- pinmux_set_func(PINGRP_GMA, PMUX_FUNC_SDIO4);
- pinmux_set_func(PINGRP_GME, PMUX_FUNC_SDIO4);
-
- pinmux_tristate_disable(PINGRP_ATB);
- pinmux_tristate_disable(PINGRP_GMA);
- pinmux_tristate_disable(PINGRP_GME);
-
- /* SDMMC3: SDIO3_CLK, SDIO3_CMD, SDIO3_DAT[3:0] */
- pinmux_set_func(PINGRP_SDB, PMUX_FUNC_SDIO3);
- pinmux_set_func(PINGRP_SDC, PMUX_FUNC_SDIO3);
- pinmux_set_func(PINGRP_SDD, PMUX_FUNC_SDIO3);
-
- pinmux_tristate_disable(PINGRP_SDC);
- pinmux_tristate_disable(PINGRP_SDD);
- pinmux_tristate_disable(PINGRP_SDB);
-}
-#endif
-
/*
* Routine: board_init
* Description: Early hardware init.
@@ -142,30 +111,12 @@ int board_init(void)
return 0;
}
-#ifdef CONFIG_TEGRA2_MMC
-/* this is a weak define that we are overriding */
-int board_mmc_init(bd_t *bd)
-{
- debug("board_mmc_init called\n");
- /* Enable muxes, etc. for SDMMC controllers */
- pin_mux_mmc();
- gpio_config_mmc();
-
- debug("board_mmc_init: init eMMC\n");
- /* init dev 0, eMMC chip, with 4-bit bus */
- tegra2_mmc_init(0, 4);
-
- debug("board_mmc_init: init SD slot\n");
- /* init dev 1, SD slot, with 4-bit bus */
- tegra2_mmc_init(1, 4);
-
- return 0;
-}
-#endif
-
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
+ /* We didn't do this init in start.S, so do it now */
+ cpu_init_cp15();
+
/* Initialize essential common plls */
clock_early_init();
@@ -177,9 +128,6 @@ int board_early_init_f(void)
/* Initialize periph GPIOs */
gpio_config_uart();
-
- /* Init UART, scratch regs, and start CPU */
- tegra2_start();
return 0;
}
#endif /* EARLY_INIT */
diff --git a/board/nvidia/common/board.h b/board/nvidia/common/board.h
index 344e70283e..1f57086602 100644
--- a/board/nvidia/common/board.h
+++ b/board/nvidia/common/board.h
@@ -24,9 +24,7 @@
#ifndef _BOARD_H_
#define _BOARD_H_
-void tegra2_start(void);
void gpio_config_uart(void);
-void gpio_config_mmc(void);
-int tegra2_mmc_init(int dev_index, int bus_width);
+int tegra2_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio);
#endif /* BOARD_H */
diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c
index cbb30d6301..3cbe820c95 100644
--- a/board/nvidia/harmony/harmony.c
+++ b/board/nvidia/harmony/harmony.c
@@ -24,9 +24,12 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/tegra2.h>
+#include <asm/arch/pinmux.h>
+#include <asm/gpio.h>
#ifdef CONFIG_TEGRA2_MMC
#include <mmc.h>
#endif
+#include "../common/board.h"
/*
* Routine: gpio_config_uart
@@ -38,23 +41,55 @@ void gpio_config_uart(void)
#ifdef CONFIG_TEGRA2_MMC
/*
- * Routine: gpio_config_mmc
- * Description: Set GPIOs for SD card
+ * Routine: pin_mux_mmc
+ * Description: setup the pin muxes/tristate values for the SDMMC(s)
*/
-void gpio_config_mmc(void)
+static void pin_mux_mmc(void)
{
- /* Not implemented for now */
+ /* SDMMC4: config 3, x8 on 2nd set of pins */
+ pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4);
+ pinmux_set_func(PINGRP_GMA, PMUX_FUNC_SDIO4);
+ pinmux_set_func(PINGRP_GME, PMUX_FUNC_SDIO4);
+
+ pinmux_tristate_disable(PINGRP_ATB);
+ pinmux_tristate_disable(PINGRP_GMA);
+ pinmux_tristate_disable(PINGRP_GME);
+
+ /* For power GPIO PI6 */
+ pinmux_tristate_disable(PINGRP_ATA);
+ /* For CD GPIO PH2 */
+ pinmux_tristate_disable(PINGRP_ATD);
+
+ /* SDMMC2: SDIO2_CLK, SDIO2_CMD, SDIO2_DAT[7:0] */
+ pinmux_set_func(PINGRP_DTA, PMUX_FUNC_SDIO2);
+ pinmux_set_func(PINGRP_DTD, PMUX_FUNC_SDIO2);
+
+ pinmux_tristate_disable(PINGRP_DTA);
+ pinmux_tristate_disable(PINGRP_DTD);
+
+ /* For power GPIO PT3 */
+ pinmux_tristate_disable(PINGRP_DTB);
+ /* For CD GPIO PI5 */
+ pinmux_tristate_disable(PINGRP_ATC);
}
/* this is a weak define that we are overriding */
-int board_mmc_getcd(u8 *cd, struct mmc *mmc)
+int board_mmc_init(bd_t *bd)
{
- debug("board_mmc_getcd called\n");
- /*
- * Hard-code CD presence for now. Need to add GPIO inputs
- * for Harmony
- */
- *cd = 1;
+ debug("board_mmc_init called\n");
+
+ /* Enable muxes, etc. for SDMMC controllers */
+ pin_mux_mmc();
+
+ debug("board_mmc_init: init SD slot J26\n");
+ /* init dev 0, SD slot J26, with 4-bit bus */
+ /* The board has an 8-bit bus, but 8-bit doesn't work yet */
+ tegra2_mmc_init(0, 4, GPIO_PI6, GPIO_PH2);
+
+ debug("board_mmc_init: init SD slot J5\n");
+ /* init dev 2, SD slot J5, with 4-bit bus */
+ tegra2_mmc_init(2, 4, GPIO_PT3, GPIO_PI5);
+
return 0;
}
#endif
diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c
index bc67d0f94c..7f2827b8be 100644
--- a/board/nvidia/seaboard/seaboard.c
+++ b/board/nvidia/seaboard/seaboard.c
@@ -24,61 +24,78 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/tegra2.h>
+#include <asm/arch/pinmux.h>
#include <asm/gpio.h>
#ifdef CONFIG_TEGRA2_MMC
#include <mmc.h>
#endif
+#include "../common/board.h"
/*
- * Routine: gpio_config_uart
+ * Routine: gpio_config_uart_seaboard
* Description: Force GPIO_PI3 low on Seaboard so UART4 works.
*/
-void gpio_config_uart(void)
+static void gpio_config_uart_seaboard(void)
{
- int gp = GPIO_PI3;
- struct gpio_ctlr *gpio = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
- struct gpio_ctlr_bank *bank = &gpio->gpio_bank[GPIO_BANK(gp)];
- u32 val;
-
/* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */
- val = readl(&bank->gpio_config[GPIO_PORT(gp)]);
- val |= 1 << GPIO_BIT(gp);
- writel(val, &bank->gpio_config[GPIO_PORT(gp)]);
-
- val = readl(&bank->gpio_out[GPIO_PORT(gp)]);
- val &= ~(1 << GPIO_BIT(gp));
- writel(val, &bank->gpio_out[GPIO_PORT(gp)]);
+ gpio_request(GPIO_PI3, NULL);
+ gpio_direction_output(GPIO_PI3, 0);
+}
- val = readl(&bank->gpio_dir_out[GPIO_PORT(gp)]);
- val |= 1 << GPIO_BIT(gp);
- writel(val, &bank->gpio_dir_out[GPIO_PORT(gp)]);
+void gpio_config_uart(void)
+{
+ if (machine_is_ventana())
+ return;
+ gpio_config_uart_seaboard();
}
#ifdef CONFIG_TEGRA2_MMC
/*
- * Routine: gpio_config_mmc
- * Description: Set GPIOs for SDMMC3 SDIO slot.
+ * Routine: pin_mux_mmc
+ * Description: setup the pin muxes/tristate values for the SDMMC(s)
*/
-void gpio_config_mmc(void)
+static void pin_mux_mmc(void)
{
- /* Set EN_VDDIO_SD (GPIO I6) */
- gpio_direction_output(GPIO_PI6, 1);
+ /* SDMMC4: config 3, x8 on 2nd set of pins */
+ pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4);
+ pinmux_set_func(PINGRP_GMA, PMUX_FUNC_SDIO4);
+ pinmux_set_func(PINGRP_GME, PMUX_FUNC_SDIO4);
- /* Config pin as GPI for Card Detect (GPIO I5) */
- gpio_direction_input(GPIO_PI5);
+ pinmux_tristate_disable(PINGRP_ATB);
+ pinmux_tristate_disable(PINGRP_GMA);
+ pinmux_tristate_disable(PINGRP_GME);
+
+ /* SDMMC3: SDIO3_CLK, SDIO3_CMD, SDIO3_DAT[3:0] */
+ pinmux_set_func(PINGRP_SDB, PMUX_FUNC_SDIO3);
+ pinmux_set_func(PINGRP_SDC, PMUX_FUNC_SDIO3);
+ pinmux_set_func(PINGRP_SDD, PMUX_FUNC_SDIO3);
+
+ pinmux_tristate_disable(PINGRP_SDC);
+ pinmux_tristate_disable(PINGRP_SDD);
+ pinmux_tristate_disable(PINGRP_SDB);
+
+ /* For power GPIO PI6 */
+ pinmux_tristate_disable(PINGRP_ATA);
+ /* For CD GPIO PI5 */
+ pinmux_tristate_disable(PINGRP_ATC);
}
/* this is a weak define that we are overriding */
-int board_mmc_getcd(u8 *cd, struct mmc *mmc)
+int board_mmc_init(bd_t *bd)
{
- debug("board_mmc_getcd called\n");
- *cd = 1; /* Assume card is inserted, or eMMC */
+ debug("board_mmc_init called\n");
+
+ /* Enable muxes, etc. for SDMMC controllers */
+ pin_mux_mmc();
+
+ debug("board_mmc_init: init eMMC\n");
+ /* init dev 0, eMMC chip, with 4-bit bus */
+ /* The board has an 8-bit bus, but 8-bit doesn't work yet */
+ tegra2_mmc_init(0, 4, -1, -1);
- if (IS_SD(mmc)) {
- /* Seaboard SDMMC3 = SDIO3_CD = GPIO_PI5 */
- if (gpio_get_value(GPIO_PI5))
- *cd = 0;
- }
+ debug("board_mmc_init: init SD slot\n");
+ /* init dev 1, SD slot, with 4-bit bus */
+ tegra2_mmc_init(1, 4, GPIO_PI6, GPIO_PI5);
return 0;
}
diff --git a/board/nvidia/ventana/Makefile b/board/nvidia/ventana/Makefile
new file mode 100644
index 0000000000..9e5a87ffe8
--- /dev/null
+++ b/board/nvidia/ventana/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2010,2011
+# NVIDIA Corporation <www.nvidia.com>
+#
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS += ../seaboard/seaboard.o
+COBJS += ../common/board.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
generated by cgit (git 2.34.1) at 2025-01-12 13:09:21 +0000