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-rw-r--r--board/phytec/pcm051/Kconfig15
-rw-r--r--board/phytec/pcm051/MAINTAINERS7
-rw-r--r--board/phytec/pcm051/Makefile11
-rw-r--r--board/phytec/pcm051/board.c258
-rw-r--r--board/phytec/pcm051/board.h24
-rw-r--r--board/phytec/pcm051/mux.c127
6 files changed, 0 insertions, 442 deletions
diff --git a/board/phytec/pcm051/Kconfig b/board/phytec/pcm051/Kconfig
deleted file mode 100644
index 2cc0d8872d..0000000000
--- a/board/phytec/pcm051/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_PCM051
-
-config SYS_BOARD
- default "pcm051"
-
-config SYS_VENDOR
- default "phytec"
-
-config SYS_SOC
- default "am33xx"
-
-config SYS_CONFIG_NAME
- default "pcm051"
-
-endif
diff --git a/board/phytec/pcm051/MAINTAINERS b/board/phytec/pcm051/MAINTAINERS
deleted file mode 100644
index 18ea636a83..0000000000
--- a/board/phytec/pcm051/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-PCM051 BOARD
-M: Lars Poeschel <poeschel@lemonage.de>
-S: Maintained
-F: board/phytec/pcm051/
-F: include/configs/pcm051.h
-F: configs/pcm051_rev1_defconfig
-F: configs/pcm051_rev3_defconfig
diff --git a/board/phytec/pcm051/Makefile b/board/phytec/pcm051/Makefile
deleted file mode 100644
index ff6f8b4221..0000000000
--- a/board/phytec/pcm051/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Makefile
-#
-# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
-
-ifdef CONFIG_SPL_BUILD
-obj-y += mux.o
-endif
-
-obj-y += board.o
diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
deleted file mode 100644
index 6f1ada82c4..0000000000
--- a/board/phytec/pcm051/board.c
+++ /dev/null
@@ -1,258 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * board.c
- *
- * Board functions for Phytec phyCORE-AM335x (pcm051) based boards
- *
- * Copyright (C) 2013 Lemonage Software GmbH
- * Author Lars Poeschel <poeschel@lemonage.de>
- */
-
-#include <common.h>
-#include <env.h>
-#include <errno.h>
-#include <init.h>
-#include <net.h>
-#include <spl.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/omap.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/io.h>
-#include <asm/emif.h>
-#include <asm/gpio.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <cpsw.h>
-#include "board.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* MII mode defines */
-#define RMII_RGMII2_MODE_ENABLE 0x49
-
-static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
-#ifdef CONFIG_SPL_BUILD
-
-/* DDR RAM defines */
-#define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */
-
-#define OSC (V_OSCK/1000000)
-const struct dpll_params dpll_ddr = {
- DDR_CLK_MHZ, OSC-1, 1, -1, -1, -1, -1};
-
-const struct dpll_params *get_dpll_ddr_params(void)
-{
- return &dpll_ddr;
-}
-
-#ifdef CONFIG_REV1
-const struct ctrl_ioregs ioregs = {
- .cm0ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
- .cm1ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
- .cm2ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
- .dt0ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
- .dt1ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
-};
-
-static const struct ddr_data ddr3_data = {
- .datardsratio0 = MT41J256M8HX15E_RD_DQS,
- .datawdsratio0 = MT41J256M8HX15E_WR_DQS,
- .datafwsratio0 = MT41J256M8HX15E_PHY_FIFO_WE,
- .datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA,
-};
-
-static const struct cmd_control ddr3_cmd_ctrl_data = {
- .cmd0csratio = MT41J256M8HX15E_RATIO,
- .cmd0iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
-
- .cmd1csratio = MT41J256M8HX15E_RATIO,
- .cmd1iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
-
- .cmd2csratio = MT41J256M8HX15E_RATIO,
- .cmd2iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
-};
-
-static struct emif_regs ddr3_emif_reg_data = {
- .sdram_config = MT41J256M8HX15E_EMIF_SDCFG,
- .ref_ctrl = MT41J256M8HX15E_EMIF_SDREF,
- .sdram_tim1 = MT41J256M8HX15E_EMIF_TIM1,
- .sdram_tim2 = MT41J256M8HX15E_EMIF_TIM2,
- .sdram_tim3 = MT41J256M8HX15E_EMIF_TIM3,
- .zq_config = MT41J256M8HX15E_ZQ_CFG,
- .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY |
- PHY_EN_DYN_PWRDN,
-};
-
-void sdram_init(void)
-{
- config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data,
- &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
-}
-#else
-const struct ctrl_ioregs ioregs = {
- .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
-};
-
-static const struct ddr_data ddr3_data = {
- .datardsratio0 = MT41K256M16HA125E_RD_DQS,
- .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
- .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
- .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
-};
-
-static const struct cmd_control ddr3_cmd_ctrl_data = {
- .cmd0csratio = MT41K256M16HA125E_RATIO,
- .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
-
- .cmd1csratio = MT41K256M16HA125E_RATIO,
- .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
-
- .cmd2csratio = MT41K256M16HA125E_RATIO,
- .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
-};
-
-static struct emif_regs ddr3_emif_reg_data = {
- .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
- .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
- .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
- .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
- .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
- .zq_config = MT41K256M16HA125E_ZQ_CFG,
- .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY |
- PHY_EN_DYN_PWRDN,
-};
-
-void sdram_init(void)
-{
- config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data,
- &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
-}
-#endif
-
-void set_uart_mux_conf(void)
-{
- enable_uart0_pin_mux();
-}
-
-void set_mux_conf_regs(void)
-{
- /* Initalize the board header */
- enable_i2c0_pin_mux();
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
-
- enable_board_pin_mux();
-}
-#endif
-
-/*
- * Basic board specific setup. Pinmux has been handled already.
- */
-int board_init(void)
-{
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
-
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
- return 0;
-}
-
-#ifdef CONFIG_DRIVER_TI_CPSW
-static void cpsw_control(int enabled)
-{
- /* VTP can be added here */
-
- return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
- {
- .slave_reg_ofs = 0x208,
- .sliver_reg_ofs = 0xd80,
- .phy_addr = 0,
- .phy_if = PHY_INTERFACE_MODE_RGMII,
- },
- {
- .slave_reg_ofs = 0x308,
- .sliver_reg_ofs = 0xdc0,
- .phy_addr = 1,
- .phy_if = PHY_INTERFACE_MODE_RGMII,
- },
-};
-
-static struct cpsw_platform_data cpsw_data = {
- .mdio_base = CPSW_MDIO_BASE,
- .cpsw_base = CPSW_BASE,
- .mdio_div = 0xff,
- .channels = 8,
- .cpdma_reg_ofs = 0x800,
- .slaves = 1,
- .slave_data = cpsw_slaves,
- .ale_reg_ofs = 0xd00,
- .ale_entries = 1024,
- .host_port_reg_ofs = 0x108,
- .hw_stats_reg_ofs = 0x900,
- .bd_ram_ofs = 0x2000,
- .mac_control = (1 << 5),
- .control = cpsw_control,
- .host_port_num = 0,
- .version = CPSW_CTRL_VERSION_2,
-};
-#endif
-
-#if defined(CONFIG_DRIVER_TI_CPSW) || \
- (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
-int board_eth_init(bd_t *bis)
-{
- int rv, n = 0;
-#ifdef CONFIG_DRIVER_TI_CPSW
- uint8_t mac_addr[6];
- uint32_t mac_hi, mac_lo;
-
- if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
- printf("<ethaddr> not set. Reading from E-fuse\n");
- /* try reading mac address from efuse */
- mac_lo = readl(&cdev->macid0l);
- mac_hi = readl(&cdev->macid0h);
- mac_addr[0] = mac_hi & 0xFF;
- mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
- mac_addr[4] = mac_lo & 0xFF;
- mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
- if (is_valid_ethaddr(mac_addr))
- eth_env_set_enetaddr("ethaddr", mac_addr);
- else
- goto try_usbether;
- }
-
- writel(RMII_RGMII2_MODE_ENABLE, &cdev->miisel);
-
- rv = cpsw_register(&cpsw_data);
- if (rv < 0)
- printf("Error %d registering CPSW switch\n", rv);
- else
- n += rv;
-try_usbether:
-#endif
-
-#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD)
- rv = usb_eth_initialize(bis);
- if (rv < 0)
- printf("Error %d registering USB_ETHER\n", rv);
- else
- n += rv;
-#endif
- return n;
-}
-#endif
diff --git a/board/phytec/pcm051/board.h b/board/phytec/pcm051/board.h
deleted file mode 100644
index 3366e51c85..0000000000
--- a/board/phytec/pcm051/board.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * board.h
- *
- * Phytec phyCORE-AM335x (pcm051) boards information header
- *
- * Copyright (C) 2013, Lemonage Software GmbH
- * Author Lars Poeschel <poeschel@lemonage.de>
- */
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-/*
- * We have three pin mux functions that must exist. We must be able to enable
- * uart0, for initial output and i2c0 to read the main EEPROM. We then have a
- * main pinmux function that can be overridden to enable all other pinmux that
- * is required on the board.
- */
-void enable_uart0_pin_mux(void);
-void enable_i2c0_pin_mux(void);
-void enable_board_pin_mux(void);
-void enable_cbmux_pin_mux(void);
-#endif
diff --git a/board/phytec/pcm051/mux.c b/board/phytec/pcm051/mux.c
deleted file mode 100644
index 9bca8eae9f..0000000000
--- a/board/phytec/pcm051/mux.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * mux.c
- *
- * Copyright (C) 2013 Lemonage Software GmbH
- * Author Lars Poeschel <poeschel@lemonage.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/mux.h>
-#include <asm/io.h>
-#include "board.h"
-
-static struct module_pin_mux uart0_pin_mux[] = {
- {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
- {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
- {-1},
-};
-
-#ifdef CONFIG_MMC
-static struct module_pin_mux mmc0_pin_mux[] = {
- {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
- {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
- {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
- {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
- {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
- {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
- {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
- {-1},
-};
-#endif
-
-#ifdef CONFIG_I2C
-static struct module_pin_mux i2c0_pin_mux[] = {
- {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
- PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
- {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
- PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
- {-1},
-};
-#endif
-
-#ifdef CONFIG_SPI
-static struct module_pin_mux spi0_pin_mux[] = {
- {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */
- {OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
- PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */
- {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */
- {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
- PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */
- {-1},
-};
-#endif
-
-static struct module_pin_mux rmii1_pin_mux[] = {
- {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */
- {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
- {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
- {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
- {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
- {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
- {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
- {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
- {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
- {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
- {-1},
-};
-
-static struct module_pin_mux cbmux_pin_mux[] = {
- {OFFSET(uart0_ctsn), MODE(7) | RXACTIVE | PULLDOWN_EN}, /* JP3 */
- {OFFSET(uart0_rtsn), MODE(7) | RXACTIVE | PULLUP_EN}, /* JP4 */
- {-1},
-};
-
-#ifdef CONFIG_MTD_RAW_NAND
-static struct module_pin_mux nand_pin_mux[] = {
- {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
- {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
- {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
- {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
- {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
- {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
- {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
- {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
- {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
- {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
- {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
- {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
- {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
- {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
- {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
- {-1},
-};
-#endif
-
-void enable_uart0_pin_mux(void)
-{
- configure_module_pin_mux(uart0_pin_mux);
-}
-
-void enable_i2c0_pin_mux(void)
-{
- configure_module_pin_mux(i2c0_pin_mux);
-}
-
-void enable_board_pin_mux()
-{
- configure_module_pin_mux(rmii1_pin_mux);
- configure_module_pin_mux(mmc0_pin_mux);
- configure_module_pin_mux(cbmux_pin_mux);
-#ifdef CONFIG_MTD_RAW_NAND
- configure_module_pin_mux(nand_pin_mux);
-#endif
-#ifdef CONFIG_SPI
- configure_module_pin_mux(spi0_pin_mux);
-#endif
-}
generated by cgit (git 2.34.1) at 2024-12-28 03:16:57 +0000