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-rw-r--r--board/menlo/m53menlo/Kconfig15
-rw-r--r--board/menlo/m53menlo/MAINTAINERS7
-rw-r--r--board/menlo/m53menlo/Makefile9
-rw-r--r--board/menlo/m53menlo/imximage.cfg91
-rw-r--r--board/menlo/m53menlo/m53menlo.c513
5 files changed, 635 insertions, 0 deletions
diff --git a/board/menlo/m53menlo/Kconfig b/board/menlo/m53menlo/Kconfig
new file mode 100644
index 0000000000..1953f5041b
--- /dev/null
+++ b/board/menlo/m53menlo/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M53MENLO
+
+config SYS_BOARD
+ default "m53menlo"
+
+config SYS_VENDOR
+ default "menlo"
+
+config SYS_SOC
+ default "mx5"
+
+config SYS_CONFIG_NAME
+ default "m53menlo"
+
+endif
diff --git a/board/menlo/m53menlo/MAINTAINERS b/board/menlo/m53menlo/MAINTAINERS
new file mode 100644
index 0000000000..7b78340060
--- /dev/null
+++ b/board/menlo/m53menlo/MAINTAINERS
@@ -0,0 +1,7 @@
+M53MENLO BOARD
+M: Marek Vasut <marex@denx.de>
+M: Olaf Mandel <o.mandel@menlosystems.com>
+S: Maintained
+F: board/menlo/m53menlo/
+F: include/configs/m53menlo.h
+F: configs/m53menlo_defconfig
diff --git a/board/menlo/m53menlo/Makefile b/board/menlo/m53menlo/Makefile
new file mode 100644
index 0000000000..b4ab95a568
--- /dev/null
+++ b/board/menlo/m53menlo/Makefile
@@ -0,0 +1,9 @@
+#
+# Menlosystems M53Menlo
+# Copyright (C) 2012-2017 Marek Vasut <marex@denx.de>
+# Copyright (C) 2014-2017 Olaf Mandel <o.mandel@menlosystems.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := m53menlo.o
diff --git a/board/menlo/m53menlo/imximage.cfg b/board/menlo/m53menlo/imximage.cfg
new file mode 100644
index 0000000000..68b3eb5c1c
--- /dev/null
+++ b/board/menlo/m53menlo/imximage.cfg
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * M53 DRAM init values
+ * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+#include <asm/mach-imx/imximage.cfg>
+
+/* image version */
+IMAGE_VERSION 2
+
+
+/* Boot Offset 0x400, valid for both SD and NAND boot. */
+BOOT_OFFSET FLASH_OFFSET_STANDARD
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+DATA 4 0x53fa86f4 0x00000000 /* GRP_DDRMODE_CTL */
+DATA 4 0x53fa8714 0x00000000 /* GRP_DDRMODE */
+DATA 4 0x53fa86fc 0x00000000 /* GRP_DDRPKE */
+DATA 4 0x53fa8724 0x04000000 /* GRP_DDR_TYPE */
+
+DATA 4 0x53fa872c 0x00300000 /* GRP_B3DS */
+DATA 4 0x53fa8554 0x00300000 /* DRAM_DQM3 */
+DATA 4 0x53fa8558 0x00300040 /* DRAM_SDQS3 */
+
+DATA 4 0x53fa8728 0x00300000 /* GRP_B2DS */
+DATA 4 0x53fa8560 0x00300000 /* DRAM_DQM2 */
+DATA 4 0x53fa8568 0x00300040 /* DRAM_SDQS2 */
+
+DATA 4 0x53fa871c 0x00300000 /* GRP_B1DS */
+DATA 4 0x53fa8594 0x00300000 /* DRAM_DQM1 */
+DATA 4 0x53fa8590 0x00300040 /* DRAM_SDQS1 */
+
+DATA 4 0x53fa8718 0x00300000 /* GRP_B0DS */
+DATA 4 0x53fa8584 0x00300000 /* DRAM_DQM0 */
+DATA 4 0x53fa857c 0x00300040 /* DRAM_SDQS0 */
+
+DATA 4 0x53fa8578 0x00300000 /* DRAM_SDCLK_0 */
+DATA 4 0x53fa8570 0x00300000 /* DRAM_SDCLK_1 */
+
+DATA 4 0x53fa8574 0x00300000 /* DRAM_CAS */
+DATA 4 0x53fa8588 0x00300000 /* DRAM_RAS */
+DATA 4 0x53fa86f0 0x00300000 /* GRP_ADDDS */
+DATA 4 0x53fa8720 0x00300000 /* GRP_CTLDS */
+
+DATA 4 0x53fa8564 0x00300040 /* DRAM_SDODT1 */
+DATA 4 0x53fa8580 0x00300040 /* DRAM_SDODT0 */
+
+/* ESDCTL */
+DATA 4 0x63fd9088 0x32383535
+DATA 4 0x63fd9090 0x40383538
+DATA 4 0x63fd907c 0x0136014d
+DATA 4 0x63fd9080 0x01510141
+
+DATA 4 0x63fd9018 0x00011740
+DATA 4 0x63fd9000 0xc3190000
+DATA 4 0x63fd900c 0x555952e3
+DATA 4 0x63fd9010 0xb68e8b63
+DATA 4 0x63fd9014 0x01ff00db
+DATA 4 0x63fd902c 0x000026d2
+DATA 4 0x63fd9030 0x009f0e21
+DATA 4 0x63fd9008 0x12273030
+DATA 4 0x63fd9004 0x0002002d
+DATA 4 0x63fd901c 0x00008032
+DATA 4 0x63fd901c 0x00008033
+DATA 4 0x63fd901c 0x00028031
+DATA 4 0x63fd901c 0x092080b0
+DATA 4 0x63fd901c 0x04008040
+DATA 4 0x63fd901c 0x0000803a
+DATA 4 0x63fd901c 0x0000803b
+DATA 4 0x63fd901c 0x00028039
+DATA 4 0x63fd901c 0x09208138
+DATA 4 0x63fd901c 0x04008048
+DATA 4 0x63fd9020 0x00001800
+DATA 4 0x63fd9040 0x04b80003
+DATA 4 0x63fd9058 0x00022227
+DATA 4 0x63fd901c 0x00000000
diff --git a/board/menlo/m53menlo/m53menlo.c b/board/menlo/m53menlo/m53menlo.c
new file mode 100644
index 0000000000..6bdd6d5b23
--- /dev/null
+++ b/board/menlo/m53menlo/m53menlo.c
@@ -0,0 +1,513 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Menlosystems M53Menlo board
+ *
+ * Copyright (C) 2012-2017 Marek Vasut <marex@denx.de>
+ * Copyright (C) 2014-2017 Olaf Mandel <o.mandel@menlosystems.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux-mx53.h>
+#include <asm/mach-imx/mx5_video.h>
+#include <asm/mach-imx/video.h>
+#include <asm/gpio.h>
+#include <asm/spl.h>
+#include <fdt_support.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+#include <ipu_pixfmt.h>
+#include <linux/errno.h>
+#include <linux/fb.h>
+#include <mmc.h>
+#include <netdev.h>
+#include <spl.h>
+#include <splash.h>
+#include <usb/ehci-ci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 mx53_dram_size[2];
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+ /*
+ * WARNING: We must override get_effective_memsize() function here
+ * to report only the size of the first DRAM bank. This is to make
+ * U-Boot relocator place U-Boot into valid memory, that is, at the
+ * end of the first DRAM bank. If we did not override this function
+ * like so, U-Boot would be placed at the address of the first DRAM
+ * bank + total DRAM size - sizeof(uboot), which in the setup where
+ * each DRAM bank contains 512MiB of DRAM would result in placing
+ * U-Boot into invalid memory area close to the end of the first
+ * DRAM bank.
+ */
+ return PHYS_SDRAM_2 + mx53_dram_size[1];
+}
+
+int dram_init(void)
+{
+ mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
+ mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
+
+ gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = mx53_dram_size[0];
+
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = mx53_dram_size[1];
+
+ return 0;
+}
+
+static void setup_iomux_uart(void)
+{
+ static const iomux_v3_cfg_t uart_pads[] = {
+ MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
+ MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+}
+
+#ifdef CONFIG_USB_EHCI_MX5
+int board_ehci_hcd_init(int port)
+{
+ if (port == 0) {
+ /* USB OTG PWRON */
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4,
+ PAD_CTL_PKE |
+ PAD_CTL_DSE_HIGH));
+ gpio_direction_output(IMX_GPIO_NR(1, 4), 0);
+
+ /* USB OTG Over Current */
+ imx_iomux_v3_setup_pad(MX53_PAD_GPIO_18__GPIO7_13);
+ } else if (port == 1) {
+ /* USB Host PWRON */
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2,
+ PAD_CTL_PKE |
+ PAD_CTL_DSE_HIGH));
+ gpio_direction_output(IMX_GPIO_NR(1, 2), 0);
+
+ /* USB Host Over Current */
+ imx_iomux_v3_setup_pad(MX53_PAD_GPIO_3__USBOH3_USBH1_OC);
+ }
+
+ return 0;
+}
+#endif
+
+static void setup_iomux_fec(void)
+{
+ static const iomux_v3_cfg_t fec_pads[] = {
+ /* MDIO pads */
+ NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
+ PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
+
+ /* FEC 0 pads */
+ NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
+
+ /* FEC 1 pads */
+ NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg = {
+ MMC_SDHC1_BASE_ADDR,
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
+ gpio_direction_input(IMX_GPIO_NR(1, 1));
+
+ return !gpio_get_value(IMX_GPIO_NR(1, 1));
+}
+
+#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP)
+#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_DSE_HIGH)
+
+int board_mmc_init(bd_t *bis)
+{
+ static const iomux_v3_cfg_t sd1_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
+ };
+
+ esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+ imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
+
+ return fsl_esdhc_initialize(bis, &esdhc_cfg);
+}
+#endif
+
+#ifdef CONFIG_VIDEO
+static void enable_lvds_clock(struct display_info_t const *dev, const u8 hclk)
+{
+ static struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
+ int ret;
+
+ /* For ETM0430G0DH6 model, this must be enabled before the clock. */
+ gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
+
+ /*
+ * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
+ * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
+ */
+ ret = mxc_set_clock(MXC_HCLK, hclk, MXC_LDB_CLK);
+ if (ret)
+ puts("IPU: Failed to configure LDB clock\n");
+
+ /* Configure CCM_CSCMR2 */
+ clrsetbits_le32(&mxc_ccm->cscmr2,
+ (0x7 << 26) | BIT(10) | BIT(8),
+ (0x5 << 26) | BIT(10) | BIT(8));
+
+ /* Configure LDB_CTRL */
+ writel(0x201, 0x53fa8008);
+}
+
+static void enable_lvds_etm0430g0dh6(struct display_info_t const *dev)
+{
+ /* For ETM0430G0DH6 model, this must be enabled before the clock. */
+ gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
+
+ /*
+ * Set LVDS clock to 9 MHz for the display. The PLL4 is set to
+ * 63 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
+ */
+ enable_lvds_clock(dev, 63);
+}
+
+static void enable_lvds_etm0700g0dh6(struct display_info_t const *dev)
+{
+ /*
+ * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
+ * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
+ */
+ enable_lvds_clock(dev, 233);
+
+ /* For ETM0700G0DH6 model, this may be enabled after the clock. */
+ gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
+}
+
+static const char *lvds_compat_string;
+
+static int detect_lvds(struct display_info_t const *dev)
+{
+ u8 touchid[23];
+ u8 *touchptr = &touchid[0];
+ int ret;
+
+ ret = i2c_set_bus_num(0);
+ if (ret)
+ return 0;
+
+ /* Touchscreen is at address 0x38, ID register is 0xbb. */
+ ret = i2c_read(0x38, 0xbb, 1, touchid, sizeof(touchid));
+ if (ret)
+ return 0;
+
+ /* EP0430 prefixes the response with 0xbb, skip it. */
+ if (*touchptr == 0xbb)
+ touchptr++;
+
+ /* Skip the 'EP' prefix. */
+ touchptr += 2;
+
+ ret = !memcmp(touchptr, &dev->mode.name[7], 4);
+ if (ret)
+ lvds_compat_string = dev->mode.name;
+
+ return ret;
+}
+
+void board_preboot_os(void)
+{
+ /* Power off the LCD to prevent awful color flicker */
+ gpio_direction_output(IMX_GPIO_NR(6, 0), 0);
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ if (lvds_compat_string)
+ do_fixup_by_path_string(blob, "/panel", "compatible",
+ lvds_compat_string);
+
+ return 0;
+}
+
+struct display_info_t const displays[] = {
+ {
+ .bus = 0,
+ .addr = 0,
+ .detect = detect_lvds,
+ .enable = enable_lvds_etm0430g0dh6,
+ .pixfmt = IPU_PIX_FMT_RGB666,
+ .mode = {
+ .name = "edt,etm0430g0dh6",
+ .refresh = 60,
+ .xres = 480,
+ .yres = 272,
+ .pixclock = 111111, /* picosecond (9 MHz) */
+ .left_margin = 2,
+ .right_margin = 2,
+ .upper_margin = 2,
+ .lower_margin = 2,
+ .hsync_len = 41,
+ .vsync_len = 10,
+ .sync = 0x40000000,
+ .vmode = FB_VMODE_NONINTERLACED
+ }
+ }, {
+ .bus = 0,
+ .addr = 0,
+ .detect = detect_lvds,
+ .enable = enable_lvds_etm0700g0dh6,
+ .pixfmt = IPU_PIX_FMT_RGB666,
+ .mode = {
+ .name = "edt,etm0700g0dh6",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 30048, /* picosecond (33.28 MHz) */
+ .left_margin = 40,
+ .right_margin = 88,
+ .upper_margin = 10,
+ .lower_margin = 33,
+ .hsync_len = 128,
+ .vsync_len = 2,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+ }
+ }
+};
+
+size_t display_count = ARRAY_SIZE(displays);
+#endif
+
+#ifdef CONFIG_SPLASH_SCREEN
+static struct splash_location default_splash_locations[] = {
+ {
+ .name = "mmc_fs",
+ .storage = SPLASH_STORAGE_MMC,
+ .flags = SPLASH_STORAGE_FS,
+ .devpart = "0:1",
+ },
+};
+
+int splash_screen_prepare(void)
+{
+ return splash_source_load(default_splash_locations,
+ ARRAY_SIZE(default_splash_locations));
+}
+#endif
+
+#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
+static void setup_iomux_i2c(void)
+{
+ static const iomux_v3_cfg_t i2c_pads[] = {
+ /* I2C1 */
+ NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, I2C_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, I2C_PAD_CTRL),
+ /* I2C2 */
+ NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
+}
+
+static void setup_iomux_video(void)
+{
+ static const iomux_v3_cfg_t lcd_pads[] = {
+ MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
+ MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
+ MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
+ MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
+ MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
+}
+
+static void setup_iomux_nand(void)
+{
+ static const iomux_v3_cfg_t nand_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
+ PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
+ PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
+ PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
+ PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
+ PAD_CTL_PUS_100K_UP),
+ NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
+ PAD_CTL_PUS_100K_UP),
+ NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
+ PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0,
+ PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1,
+ PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2,
+ PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3,
+ PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4,
+ PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5,
+ PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6,
+ PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7,
+ PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
+}
+
+static void m53_set_clock(void)
+{
+ int ret;
+ const u32 ref_clk = MXC_HCLK;
+ const u32 dramclk = 400;
+ u32 cpuclk;
+
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
+ PAD_CTL_DSE_HIGH | PAD_CTL_PKE));
+ gpio_direction_input(IMX_GPIO_NR(4, 0));
+
+ /* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
+ cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800;
+
+ ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
+ if (ret)
+ printf("CPU: Switch CPU clock to %dMHz failed\n", cpuclk);
+
+ ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
+ if (ret) {
+ printf("CPU: Switch peripheral clock to %dMHz failed\n",
+ dramclk);
+ }
+
+ ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
+ if (ret)
+ printf("CPU: Switch DDR clock to %dMHz failed\n", dramclk);
+}
+
+static void m53_set_nand(void)
+{
+ u32 i;
+
+ /* NAND flash is muxed on ATA pins */
+ setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK);
+
+ /* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
+ for (i = 0x4; i < 0x94; i += 0x18) {
+ clrbits_le32(WEIM_BASE_ADDR + i,
+ WEIM_GCR2_MUX16_BYP_GRANT_MASK);
+ }
+
+ mxc_set_clock(0, 33, MXC_NFC_CLK);
+ enable_nfc_clk(1);
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+ setup_iomux_fec();
+ setup_iomux_i2c();
+ setup_iomux_nand();
+ setup_iomux_video();
+
+ m53_set_clock();
+
+ mxc_set_sata_internal_clock();
+
+ /* NAND clock @ 33MHz */
+ m53_set_nand();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: Menlosystems M53Menlo\n");
+
+ return 0;
+}
+
+/*
+ * NAND SPL
+ */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+ setup_iomux_nand();
+ m53_set_clock();
+ m53_set_nand();
+}
+
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_NAND;
+}
+#endif
generated by cgit (git 2.34.1) at 2024-12-23 09:15:21 +0000