diff options
Diffstat (limited to 'board')
27 files changed, 511 insertions, 136 deletions
diff --git a/board/8dtech/eco5pk/eco5pk.h b/board/8dtech/eco5pk/eco5pk.h index a794764852..acf2b80307 100644 --- a/board/8dtech/eco5pk/eco5pk.h +++ b/board/8dtech/eco5pk/eco5pk.h @@ -332,7 +332,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \ /* JTAG */\ - MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \ diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c index 0944903ec8..d0b0930f42 100644 --- a/board/compulab/cm_t35/cm_t35.c +++ b/board/compulab/cm_t35/cm_t35.c @@ -53,16 +53,6 @@ static u32 gpmc_net_config[GPMC_MAX_REG] = { 0 }; -static u32 gpmc_nand_config[GPMC_MAX_REG] = { - M_NAND_GPMC_CONFIG1, - M_NAND_GPMC_CONFIG2, - M_NAND_GPMC_CONFIG3, - M_NAND_GPMC_CONFIG4, - M_NAND_GPMC_CONFIG5, - M_NAND_GPMC_CONFIG6, - 0, -}; - #ifdef CONFIG_LCD #ifdef CONFIG_CMD_NAND static int splash_load_from_nand(u32 bmp_load_addr) @@ -148,9 +138,6 @@ int board_init(void) { gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ - enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[0], - CONFIG_SYS_NAND_BASE, GPMC_SIZE_16M); - /* board id for Linux */ if (get_cpu_family() == CPU_OMAP34XX) gd->bd->bi_arch_number = MACH_TYPE_CM_T35; @@ -381,7 +368,7 @@ static void cm_t3x_set_common_muxconf(void) MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*OFF_MODE*/ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*CLKOUT1*/ MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*green LED*/ - MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)); /*JTAG_nTRST*/ + MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)); /*JTAG_NTRST*/ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/ @@ -457,6 +444,8 @@ void set_muxconf_regs(void) } #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) +#define SB_T35_WP_GPIO 59 + int board_mmc_getcd(struct mmc *mmc) { u8 val; @@ -469,7 +458,7 @@ int board_mmc_getcd(struct mmc *mmc) int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0, 0, 0, -1, 59); + return omap_mmc_init(0, 0, 0, -1, SB_T35_WP_GPIO); } #endif diff --git a/board/htkw/mcx/mcx.h b/board/htkw/mcx/mcx.h index 17c122cf50..d6c5df203e 100644 --- a/board/htkw/mcx/mcx.h +++ b/board/htkw/mcx/mcx.h @@ -339,7 +339,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4))\ MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4))\ /* JTAG */\ - MUX_VAL(CP(JTAG_nTRST), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(JTAG_NTRST), (IEN | PTU | EN | M4)) \ MUX_VAL(CP(JTAG_TCK), (IEN | PTU | EN | M4)) \ MUX_VAL(CP(JTAG_TMS), (IEN | PTU | EN | M4)) \ MUX_VAL(CP(JTAG_TDI), (IEN | PTU | EN | M4)) \ diff --git a/board/logicpd/am3517evm/am3517evm.h b/board/logicpd/am3517evm/am3517evm.h index d407d66ae6..a6a55eef49 100644 --- a/board/logicpd/am3517evm/am3517evm.h +++ b/board/logicpd/am3517evm/am3517evm.h @@ -333,7 +333,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \ /* JTAG */\ - MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \ diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c index 075fe949ae..1fd9f2cf01 100644 --- a/board/logicpd/omap3som/omap3logic.c +++ b/board/logicpd/omap3som/omap3logic.c @@ -230,6 +230,6 @@ void set_muxconf_regs(void) MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)); - MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)); MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); } diff --git a/board/overo/overo.c b/board/overo/overo.c index 7506820e34..dfb8602baf 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -27,12 +27,19 @@ #include <asm/mach-types.h> #include "overo.h" +#ifdef CONFIG_USB_EHCI +#include <usb.h> +#include <asm/ehci-omap.h> +#endif + DECLARE_GLOBAL_DATA_PTR; #define TWL4030_I2C_BUS 0 #define EXPANSION_EEPROM_I2C_BUS 2 #define EXPANSION_EEPROM_I2C_ADDRESS 0x51 +#define GUMSTIX_EMPTY_EEPROM 0x0 + #define GUMSTIX_SUMMIT 0x01000200 #define GUMSTIX_TOBI 0x02000200 #define GUMSTIX_TOBI_DUO 0x03000200 @@ -58,22 +65,7 @@ static struct { char fab_revision[8]; char env_var[16]; char env_setting[64]; -} expansion_config; - -#if defined(CONFIG_CMD_NET) -static void setup_net_chip(void); -#endif - -/* GPMC definitions for LAN9221 chips on Tobi expansion boards */ -static const u32 gpmc_lan_config[] = { - NET_LAN9221_GPMC_CONFIG1, - NET_LAN9221_GPMC_CONFIG2, - NET_LAN9221_GPMC_CONFIG3, - NET_LAN9221_GPMC_CONFIG4, - NET_LAN9221_GPMC_CONFIG5, - NET_LAN9221_GPMC_CONFIG6, - /*CONFIG7- computed as params */ -}; +} expansion_config = {0x0}; static const struct ns16550_platdata overo_serial = { OMAP34XX_UART3, @@ -226,6 +218,9 @@ int get_sdio2_config(void) */ unsigned int get_expansion_id(void) { + if (expansion_config.device_vendor != 0x0) + return expansion_config.device_vendor; + i2c_set_bus_num(EXPANSION_EEPROM_I2C_BUS); /* return GUMSTIX_NO_EEPROM if eeprom doesn't respond */ @@ -254,10 +249,6 @@ int misc_init_r(void) twl4030_power_init(); twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); -#if defined(CONFIG_CMD_NET) - setup_net_chip(); -#endif - printf("Board revision: %d\n", get_board_revision()); switch (get_sdio2_config()) { @@ -279,6 +270,7 @@ int misc_init_r(void) printf("Recognized Summit expansion board (rev %d %s)\n", expansion_config.revision, expansion_config.fab_revision); + MUX_GUMSTIX(); setenv("defaultdisplay", "dvi"); setenv("expansionname", "summit"); break; @@ -286,6 +278,7 @@ int misc_init_r(void) printf("Recognized Tobi expansion board (rev %d %s)\n", expansion_config.revision, expansion_config.fab_revision); + MUX_GUMSTIX(); setenv("defaultdisplay", "dvi"); setenv("expansionname", "tobi"); break; @@ -293,20 +286,20 @@ int misc_init_r(void) printf("Recognized Tobi Duo expansion board (rev %d %s)\n", expansion_config.revision, expansion_config.fab_revision); - /* second lan chip */ - enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[4], - 0x2B000000, GPMC_SIZE_16M); + MUX_GUMSTIX(); break; case GUMSTIX_PALO35: printf("Recognized Palo35 expansion board (rev %d %s)\n", expansion_config.revision, expansion_config.fab_revision); + MUX_GUMSTIX(); setenv("defaultdisplay", "lcd35"); break; case GUMSTIX_PALO43: printf("Recognized Palo43 expansion board (rev %d %s)\n", expansion_config.revision, expansion_config.fab_revision); + MUX_GUMSTIX(); setenv("defaultdisplay", "lcd43"); setenv("expansionname", "palo43"); break; @@ -314,6 +307,7 @@ int misc_init_r(void) printf("Recognized Chestnut43 expansion board (rev %d %s)\n", expansion_config.revision, expansion_config.fab_revision); + MUX_GUMSTIX(); setenv("defaultdisplay", "lcd43"); setenv("expansionname", "chestnut43"); break; @@ -321,11 +315,13 @@ int misc_init_r(void) printf("Recognized Pinto expansion board (rev %d %s)\n", expansion_config.revision, expansion_config.fab_revision); + MUX_GUMSTIX(); break; case GUMSTIX_GALLOP43: printf("Recognized Gallop43 expansion board (rev %d %s)\n", expansion_config.revision, expansion_config.fab_revision); + MUX_GUMSTIX(); setenv("defaultdisplay", "lcd43"); setenv("expansionname", "gallop43"); break; @@ -333,6 +329,7 @@ int misc_init_r(void) printf("Recognized Alto35 expansion board (rev %d %s)\n", expansion_config.revision, expansion_config.fab_revision); + MUX_GUMSTIX(); MUX_ALTO35(); setenv("defaultdisplay", "lcd35"); setenv("expansionname", "alto35"); @@ -341,21 +338,25 @@ int misc_init_r(void) printf("Recognized Stagecoach expansion board (rev %d %s)\n", expansion_config.revision, expansion_config.fab_revision); + MUX_GUMSTIX(); break; case GUMSTIX_THUMBO: printf("Recognized Thumbo expansion board (rev %d %s)\n", expansion_config.revision, expansion_config.fab_revision); + MUX_GUMSTIX(); break; case GUMSTIX_TURTLECORE: printf("Recognized Turtlecore expansion board (rev %d %s)\n", expansion_config.revision, expansion_config.fab_revision); + MUX_GUMSTIX(); break; case GUMSTIX_ARBOR43C: printf("Recognized Arbor43C expansion board (rev %d %s)\n", expansion_config.revision, expansion_config.fab_revision); + MUX_GUMSTIX(); MUX_ARBOR43C(); setenv("defaultdisplay", "lcd43"); break; @@ -363,16 +364,17 @@ int misc_init_r(void) printf("Recognized Ettus Research USRP-E (rev %d %s)\n", expansion_config.revision, expansion_config.fab_revision); + MUX_GUMSTIX(); MUX_USRP_E(); setenv("defaultdisplay", "dvi"); break; case GUMSTIX_NO_EEPROM: - puts("No EEPROM on expansion board\n"); + case GUMSTIX_EMPTY_EEPROM: + puts("No or empty EEPROM on expansion board\n"); + MUX_GUMSTIX(); setenv("expansionname", "tobi"); break; default: - if (expansion_id == 0x0) - setenv("expansionname", "tobi"); printf("Unrecognized expansion board 0x%08x\n", expansion_id); break; } @@ -401,7 +403,18 @@ void set_muxconf_regs(void) MUX_OVERO(); } -#if defined(CONFIG_CMD_NET) +#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SPL_BUILD) +/* GPMC definitions for LAN9221 chips on Tobi expansion boards */ +static const u32 gpmc_lan_config[] = { + NET_LAN9221_GPMC_CONFIG1, + NET_LAN9221_GPMC_CONFIG2, + NET_LAN9221_GPMC_CONFIG3, + NET_LAN9221_GPMC_CONFIG4, + NET_LAN9221_GPMC_CONFIG5, + NET_LAN9221_GPMC_CONFIG6, + /*CONFIG7- computed as params */ +}; + /* * Routine: setup_net_chip * Description: Setting up the configuration GPMC registers specific to the @@ -411,10 +424,6 @@ static void setup_net_chip(void) { struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; - /* first lan chip */ - enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000, - GPMC_SIZE_16M); - /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ @@ -422,7 +431,14 @@ static void setup_net_chip(void) /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, &ctrl_base->gpmc_nadv_ale); +} +/* + * Routine: reset_net_chip + * Description: Reset the Ethernet hardware. + */ +static void reset_net_chip(void) +{ /* Make GPIO 64 as output pin and send a magic pulse through it */ if (!gpio_request(64, "")) { gpio_direction_output(64, 0); @@ -433,16 +449,42 @@ static void setup_net_chip(void) gpio_set_value(64, 1); } } -#endif int board_eth_init(bd_t *bis) { + unsigned int expansion_id; int rc = 0; + #ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); + expansion_id = get_expansion_id(); + switch (expansion_id) { + case GUMSTIX_TOBI_DUO: + /* second lan chip */ + enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[4], + 0x2B000000, GPMC_SIZE_16M); + /* no break */ + case GUMSTIX_TOBI: + case GUMSTIX_CHESTNUT43: + case GUMSTIX_STAGECOACH: + case GUMSTIX_NO_EEPROM: + case GUMSTIX_EMPTY_EEPROM: + /* first lan chip */ + enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], + 0x2C000000, GPMC_SIZE_16M); + + setup_net_chip(); + reset_net_chip(); + + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); + break; + default: + break; + } #endif + return rc; } +#endif #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) @@ -450,3 +492,32 @@ int board_mmc_init(bd_t *bis) return omap_mmc_init(0, 0, 0, -1, -1); } #endif + +#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD) +static struct omap_usbhs_board_data usbhs_bdata = { + .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED +}; + +#define GUMSTIX_GPIO_USBH_CPEN 168 +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) +{ + /* Enable USB power */ + if (!gpio_request(GUMSTIX_GPIO_USBH_CPEN, "usbh_cpen")) + gpio_direction_output(GUMSTIX_GPIO_USBH_CPEN, 1); + + return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); +} + +int ehci_hcd_stop(void) +{ + /* Disable USB power */ + gpio_set_value(GUMSTIX_GPIO_USBH_CPEN, 0); + gpio_free(GUMSTIX_GPIO_USBH_CPEN); + + return omap_ehci_hcd_stop(); +} + +#endif /* CONFIG_USB_EHCI */ diff --git a/board/overo/overo.h b/board/overo/overo.h index 57725d867f..d0edf86365 100644 --- a/board/overo/overo.h +++ b/board/overo/overo.h @@ -101,13 +101,9 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ - MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /*GPIO_54*/\ /* - MMC1_WP*/\ - MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\ - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\ - MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) /*GPMC_nCS6*/\ MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) /*GPMC_nCS7*/\ MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nCS3*/\ MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M0)) /*GPMC_CLK*/\ @@ -117,45 +113,11 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\ - /* - SMSC911X_NRES*/\ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | DIS | M4)) /*GPIO_65*/\ - /*DSS*/\ - MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\ - MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\ - MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\ - MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\ - MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\ - MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\ - MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\ - MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\ - MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\ - MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\ - MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\ - MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\ - MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\ - MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\ - MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\ - MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\ - MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\ - MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\ - MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\ - MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\ - MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\ - MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\ - MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\ - MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\ - MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\ - MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\ - MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\ - MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\ /*CAMERA*/\ MUX_VAL(CP(CAM_HS), (IEN | PTU | DIS | M0)) /*CAM_HS */\ MUX_VAL(CP(CAM_VS), (IEN | PTU | DIS | M0)) /*CAM_VS */\ MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\ MUX_VAL(CP(CAM_PCLK), (IEN | PTU | DIS | M0)) /*CAM_PCLK*/\ - MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*CAM_FLD*/\ MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\ MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\ MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\ @@ -168,13 +130,8 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\ MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\ MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\ - MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\ - MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M0)) /*CAM_WEN*/\ - MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) /*GPIO_112*/\ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) /*GPIO_113*/\ - MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) /*GPIO_114*/\ - /* - PEN_DOWN*/\ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) /*GPIO_115*/\ /*Audio Interface */\ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\ @@ -208,14 +165,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\ MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\ MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\ - MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144 - LCD_EN*/\ - MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\ - MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\ - MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ MUX_VAL(CP(UART1_RTS), (IEN | PTU | DIS | M4)) /*GPIO_149*/ \ - MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M4)) /*GPIO_150-MMC3_WP*/\ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M0)) /*McBSP4_CLKX*/\ MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M0)) /*McBSP4_DR*/\ MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M0)) /*McBSP4_DX*/\ @@ -228,7 +178,6 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) /*McBSP1_FSX*/\ MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) /*McBSP1_CLKX*/\ /*Serial Interface*/\ - MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\ MUX_VAL(CP(UART3_RTS_SD), (IEN | PTU | EN | M4)) /*GPIO_164 W2W_*/\ /* BT_NRESET*/\ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTU | EN | M0)) /*UART3_RX_IRRX*/\ @@ -255,14 +204,6 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ - MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*HDQ_SIO*/\ - MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\ - MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\ - MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\ - MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\ - MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\ - MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176 */\ - /* - LAN_INTR */\ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA2*/\ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA7*/\ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA4*/\ @@ -281,21 +222,9 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\ - MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | EN | M4)) /*GPIO_10*/\ - MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\ - MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M2)) /*MMC3_CLK*/\ - MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /*MMC3_CMD*/\ - MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M4)) /*GPIO_14*/\ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M4)) /*GPIO_15 - X_GATE*/\ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M4)) /*GPIO_16*/\ /* - W2W_NRESET*/\ - MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT3*/\ - MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT0*/\ - MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT1*/\ - MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT2*/\ - MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M4)) /*GPIO_21*/\ - MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | EN | M4)) /*GPIO_22*/\ - MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | EN | M4)) /*GPIO_23*/\ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_STP*/\ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DIR*/\ @@ -369,6 +298,85 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/ +#define MUX_GUMSTIX() \ + /*GPMC*/\ + MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ + MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\ + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\ + MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) /*GPMC_nCS6*/\ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) /*GPIO_63*/\ + /* - CAM_IRQ*/\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\ + /* - SMSC911X_NRES*/\ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | DIS | M4)) /*GPIO_65*/\ + /*DSS*/\ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\ + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\ + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\ + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\ + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\ + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\ + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\ + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\ + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\ + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\ + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\ + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\ + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\ + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\ + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\ + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\ + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\ + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\ + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\ + /*CAMERA*/\ + MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*CAM_FLD*/\ + MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M0)) /*CAM_WEN*/\ + MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) /*GPIO_114*/\ + /* - PEN_DOWN*/\ + /*Bluetooth*/\ + MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144 - LCD_EN*/\ + MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\ + MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\ + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M4)) /*GPIO_150-MMC3_WP*/\ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ + /*Serial Interface*/\ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\ + MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*HDQ_SIO*/\ + MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\ + MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\ + MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\ + MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\ + MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\ + MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176 */\ + /* - LAN_INTR */\ + /*Control and debug */\ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | EN | M4)) /*GPIO_10*/\ + MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\ + MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M2)) /*MMC3_CLK*/\ + MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /*MMC3_CMD*/\ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M4)) /*GPIO_14*/\ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT3*/\ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT0*/\ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT1*/\ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT2*/\ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M4)) /*GPIO_21*/\ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | EN | M4)) /*GPIO_22*/\ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | EN | M4)) /*GPIO_23*/\ + #define MUX_OVERO_SDIO2_DIRECT() \ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\ diff --git a/board/pandora/pandora.h b/board/pandora/pandora.h index cbf4186f71..268b92998f 100644 --- a/board/pandora/pandora.h +++ b/board/pandora/pandora.h @@ -310,7 +310,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8*/\ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\ /*JTAG*/\ - MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\ + MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) /*JTAG_NTRST*/\ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\ diff --git a/board/technexion/tao3530/tao3530.h b/board/technexion/tao3530/tao3530.h index daff109480..4a94399fc9 100644 --- a/board/technexion/tao3530/tao3530.h +++ b/board/technexion/tao3530/tao3530.h @@ -275,7 +275,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \ diff --git a/board/technexion/twister/twister.h b/board/technexion/twister/twister.h index 62fbfdfed6..e286bd4522 100644 --- a/board/technexion/twister/twister.h +++ b/board/technexion/twister/twister.h @@ -337,7 +337,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \ /* JTAG */\ - MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \ diff --git a/board/teejet/mt_ventoux/mt_ventoux.h b/board/teejet/mt_ventoux/mt_ventoux.h index aba71a84bf..bc85ad4350 100644 --- a/board/teejet/mt_ventoux/mt_ventoux.h +++ b/board/teejet/mt_ventoux/mt_ventoux.h @@ -339,7 +339,7 @@ const omap3_sysinfo sysinfo = { /* gpio_10 */\ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \ /* JTAG */\ - MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \ diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index f4bb9f890b..680f6560f2 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -359,9 +359,9 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header) configure_module_pin_mux(i2c1_pin_mux); configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); -#if defined(CONFIG_NAND) +#if defined(CONFIG_NAND) && defined(CONFIG_EMMC_BOOT) configure_module_pin_mux(nand_pin_mux); -#elif defined(CONFIG_NOR) +#elif defined(CONFIG_NOR) && defined(CONFIG_EMMC_BOOT) configure_module_pin_mux(bone_norcape_pin_mux); #else configure_module_pin_mux(mmc1_pin_mux); diff --git a/board/ti/am3517crane/am3517crane.h b/board/ti/am3517crane/am3517crane.h index e131c8fb99..6289ca787c 100644 --- a/board/ti/am3517crane/am3517crane.h +++ b/board/ti/am3517crane/am3517crane.h @@ -284,7 +284,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4))/*GPIO_10 TP*/\ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0))\ /*JTAG*/\ - MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0))\ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0))\ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0))\ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0))\ diff --git a/board/ti/evm/evm.h b/board/ti/evm/evm.h index f50193d99a..91e9b88c54 100644 --- a/board/ti/evm/evm.h +++ b/board/ti/evm/evm.h @@ -300,7 +300,7 @@ static void reset_net_chip(void); MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) /*SYS_CLKOUT2*/\ - MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\ + MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) /*JTAG_NTRST*/\ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\ diff --git a/board/ti/ks2_evm/Kconfig b/board/ti/ks2_evm/Kconfig index 9c1e103a20..96c5f22ead 100644 --- a/board/ti/ks2_evm/Kconfig +++ b/board/ti/ks2_evm/Kconfig @@ -23,3 +23,19 @@ config SYS_CONFIG_NAME default "k2hk_evm" endif + +if TARGET_K2L_EVM + +config SYS_BOARD + string + default "ks2_evm" + +config SYS_VENDOR + string + default "ti" + +config SYS_CONFIG_NAME + string + default "k2l_evm" + +endif diff --git a/board/ti/ks2_evm/MAINTAINERS b/board/ti/ks2_evm/MAINTAINERS index 595a80a8bc..87c36c9d14 100644 --- a/board/ti/ks2_evm/MAINTAINERS +++ b/board/ti/ks2_evm/MAINTAINERS @@ -6,3 +6,5 @@ F: include/configs/k2hk_evm.h F: configs/k2hk_evm_defconfig F: include/configs/k2e_evm.h F: configs/k2e_evm_defconfig +F: include/configs/k2l_evm.h +F: configs/k2l_evm_defconfig diff --git a/board/ti/ks2_evm/Makefile b/board/ti/ks2_evm/Makefile index 00f1164833..071dbee180 100644 --- a/board/ti/ks2_evm/Makefile +++ b/board/ti/ks2_evm/Makefile @@ -11,3 +11,5 @@ obj-$(CONFIG_K2HK_EVM) += board_k2hk.o obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o obj-$(CONFIG_K2E_EVM) += board_k2e.o obj-$(CONFIG_K2E_EVM) += ddr3_k2e.o +obj-$(CONFIG_K2L_EVM) += board_k2l.o +obj-$(CONFIG_K2L_EVM) += ddr3_k2l.o diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index dfe7be60e7..4029493452 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -9,11 +9,13 @@ #include "board.h" #include <common.h> +#include <spl.h> #include <exports.h> #include <fdt_support.h> #include <asm/arch/ddr3.h> -#include <asm/arch/emac_defs.h> +#include <asm/arch/psc_defs.h> #include <asm/ti-common/ti-aemif.h> +#include <asm/ti-common/keystone_net.h> DECLARE_GLOBAL_DATA_PTR; @@ -38,6 +40,7 @@ int dram_init(void) gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE); aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs); + ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE); return 0; } @@ -68,6 +71,15 @@ int board_eth_init(bd_t *bis) int port_num; char link_type_name[32]; + /* By default, select PA PLL clock as PA clock source */ + if (psc_enable_module(KS2_LPSC_PA)) + return -1; + if (psc_enable_module(KS2_LPSC_CPGMAC)) + return -1; + if (psc_enable_module(KS2_LPSC_CRYPTO)) + return -1; + pass_pll_pa_clk_enable(); + port_num = get_num_eth_ports(); for (j = 0; j < port_num; j++) { @@ -83,6 +95,24 @@ int board_eth_init(bd_t *bis) } #endif +#ifdef CONFIG_SPL_BUILD +void spl_board_init(void) +{ + spl_init_keystone_plls(); + preloader_console_init(); +} + +u32 spl_boot_device(void) +{ +#if defined(CONFIG_SPL_SPI_LOAD) + return BOOT_DEVICE_SPI; +#else + puts("Unknown boot device\n"); + hang(); +#endif +} +#endif + #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { @@ -225,5 +255,7 @@ void ft_board_setup_ex(void *blob, bd_t *bd) reserve_start += 2; } } + + ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE); } #endif diff --git a/board/ti/ks2_evm/board.h b/board/ti/ks2_evm/board.h index d91ef73612..2bbd79245b 100644 --- a/board/ti/ks2_evm/board.h +++ b/board/ti/ks2_evm/board.h @@ -10,10 +10,11 @@ #ifndef _KS2_BOARD #define _KS2_BOARD -#include <asm/arch/emac_defs.h> +#include <asm/ti-common/keystone_net.h> extern struct eth_priv_t eth_priv_cfg[]; int get_num_eth_ports(void); +void spl_init_keystone_plls(void); #endif diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c index 5472a43c43..43dfc48a53 100644 --- a/board/ti/ks2_evm/board_k2e.c +++ b/board/ti/ks2_evm/board_k2e.c @@ -10,6 +10,7 @@ #include <common.h> #include <asm/arch/ddr3.h> #include <asm/arch/hardware.h> +#include <asm/ti-common/keystone_net.h> DECLARE_GLOBAL_DATA_PTR; @@ -35,10 +36,75 @@ static struct pll_init_data core_pll_config[] = { CORE_PLL_1500, }; - static struct pll_init_data pa_pll_config = PASS_PLL_1000; +#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET +struct eth_priv_t eth_priv_cfg[] = { + { + .int_name = "K2E_EMAC0", + .rx_flow = 0, + .phy_addr = 0, + .slave_port = 1, + .sgmii_link_type = SGMII_LINK_MAC_PHY, + }, + { + .int_name = "K2E_EMAC1", + .rx_flow = 8, + .phy_addr = 1, + .slave_port = 2, + .sgmii_link_type = SGMII_LINK_MAC_PHY, + }, + { + .int_name = "K2E_EMAC2", + .rx_flow = 16, + .phy_addr = 2, + .slave_port = 3, + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + }, + { + .int_name = "K2E_EMAC3", + .rx_flow = 24, + .phy_addr = 3, + .slave_port = 4, + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + }, + { + .int_name = "K2E_EMAC4", + .rx_flow = 32, + .phy_addr = 4, + .slave_port = 5, + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + }, + { + .int_name = "K2E_EMAC5", + .rx_flow = 40, + .phy_addr = 5, + .slave_port = 6, + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + }, + { + .int_name = "K2E_EMAC6", + .rx_flow = 48, + .phy_addr = 6, + .slave_port = 7, + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + }, + { + .int_name = "K2E_EMAC7", + .rx_flow = 56, + .phy_addr = 7, + .slave_port = 8, + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + }, +}; + +int get_num_eth_ports(void) +{ + return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t); +} +#endif + #if defined(CONFIG_BOARD_EARLY_INIT_F) int board_early_init_f(void) { @@ -52,3 +118,14 @@ int board_early_init_f(void) return 0; } #endif + +#ifdef CONFIG_SPL_BUILD +static struct pll_init_data spl_pll_config[] = { + CORE_PLL_800, +}; + +void spl_init_keystone_plls(void) +{ + init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config); +} +#endif diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c index 6fb3d2123d..ed181f44b8 100644 --- a/board/ti/ks2_evm/board_k2hk.c +++ b/board/ti/ks2_evm/board_k2hk.c @@ -10,7 +10,7 @@ #include <common.h> #include <asm/arch/clock.h> #include <asm/arch/hardware.h> -#include <asm/arch/emac_defs.h> +#include <asm/ti-common/keystone_net.h> DECLARE_GLOBAL_DATA_PTR; @@ -100,3 +100,15 @@ int board_early_init_f(void) return 0; } #endif + +#ifdef CONFIG_SPL_BUILD +static struct pll_init_data spl_pll_config[] = { + CORE_PLL_799, + TETRIS_PLL_500, +}; + +void spl_init_keystone_plls(void) +{ + init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config); +} +#endif diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c new file mode 100644 index 0000000000..559d20ca88 --- /dev/null +++ b/board/ti/ks2_evm/board_k2l.c @@ -0,0 +1,72 @@ +/* + * K2L EVM : Board initialization + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/ddr3.h> +#include <asm/arch/hardware.h> +#include <asm/ti-common/ti-aemif.h> + +DECLARE_GLOBAL_DATA_PTR; + +unsigned int external_clk[ext_clk_count] = { + [sys_clk] = 122880000, + [alt_core_clk] = 100000000, + [pa_clk] = 122880000, + [tetris_clk] = 122880000, + [ddr3_clk] = 100000000, + [pcie_clk] = 100000000, + [sgmii_clk] = 156250000, + [usb_clk] = 100000000, +}; + +static struct pll_init_data core_pll_config[] = { + CORE_PLL_799, + CORE_PLL_1000, + CORE_PLL_1198, +}; + +static struct pll_init_data tetris_pll_config[] = { + TETRIS_PLL_799, + TETRIS_PLL_1000, + TETRIS_PLL_1198, + TETRIS_PLL_1352, + TETRIS_PLL_1401, +}; + +static struct pll_init_data pa_pll_config = + PASS_PLL_983; + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ + int speed; + + speed = get_max_dev_speed(); + init_pll(&core_pll_config[speed]); + + init_pll(&pa_pll_config); + + speed = get_max_arm_speed(); + init_pll(&tetris_pll_config[speed]); + + return 0; +} +#endif + +#ifdef CONFIG_SPL_BUILD +static struct pll_init_data spl_pll_config[] = { + CORE_PLL_799, + TETRIS_PLL_491, +}; + +void spl_init_keystone_plls(void) +{ + init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config); +} +#endif diff --git a/board/ti/ks2_evm/ddr3_cfg.c b/board/ti/ks2_evm/ddr3_cfg.c index f7da9f2bcb..ab44676793 100644 --- a/board/ti/ks2_evm/ddr3_cfg.c +++ b/board/ti/ks2_evm/ddr3_cfg.c @@ -133,6 +133,42 @@ struct ddr3_emif_config ddr3_1600_4g = { }; #endif +struct ddr3_phy_config ddr3phy_1600_2g = { + .pllcr = 0x0001C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x0D861A80ul, + .ptr4 = 0x0C827100ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), + .dcr_val = ((1 << 10)), + .dtpr0 = 0x9D5CBB66ul, + .dtpr1 = 0x12868300ul, + .dtpr2 = 0x5002D200ul, + .mr0 = 0x00001C70ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000018ul, + .dtcr = 0x710035C7ul, + .pgcr2 = 0x00F07A12ul, + .zq0cr1 = 0x0001005Dul, + .zq1cr1 = 0x0001005Bul, + .zq2cr1 = 0x0001005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + +struct ddr3_emif_config ddr3_1600_2g = { + .sdcfg = 0x6200CE62ul, + .sdtim1 = 0x166C9855ul, + .sdtim2 = 0x00001D4Aul, + .sdtim3 = 0x435DFF53ul, + .sdtim4 = 0x543F0CFFul, + .zqcfg = 0x70073200ul, + .sdrfc = 0x00001869ul, +}; + int ddr3_get_dimm_params(char *dimm_name) { int ret; diff --git a/board/ti/ks2_evm/ddr3_cfg.h b/board/ti/ks2_evm/ddr3_cfg.h index 15fcf52ef1..5bd786cff8 100644 --- a/board/ti/ks2_evm/ddr3_cfg.h +++ b/board/ti/ks2_evm/ddr3_cfg.h @@ -19,6 +19,9 @@ extern struct ddr3_emif_config ddr3_1333_2g; extern struct ddr3_phy_config ddr3phy_1600_4g; extern struct ddr3_emif_config ddr3_1600_4g; +extern struct ddr3_phy_config ddr3phy_1600_2g; +extern struct ddr3_emif_config ddr3_1600_2g; + int ddr3_get_dimm_params(char *dimm_name); #endif /* __DDR3_CFG_H */ diff --git a/board/ti/ks2_evm/ddr3_k2hk.c b/board/ti/ks2_evm/ddr3_k2hk.c index 6070a99770..a1c3d05f8e 100644 --- a/board/ti/ks2_evm/ddr3_k2hk.c +++ b/board/ti/ks2_evm/ddr3_k2hk.c @@ -12,6 +12,8 @@ #include <asm/arch/ddr3.h> #include <asm/arch/hardware.h> +static int ddr3_size; + struct pll_init_data ddr3a_333 = DDR3_PLL_333(A); struct pll_init_data ddr3a_400 = DDR3_PLL_400(A); @@ -44,12 +46,14 @@ void ddr3_init(void) ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_8g); printf("DRAM: Capacity 8 GiB (includes reported below)\n"); + ddr3_size = 8; } else { ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g); ddr3_1600_8g.sdcfg |= 0x1000; ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_8g); printf("DRAM: Capacity 4 GiB (includes reported below)\n"); + ddr3_size = 4; } } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) { init_pll(&ddr3a_333); @@ -70,11 +74,15 @@ void ddr3_init(void) } ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_2g); + ddr3_size = 2; + printf("DRAM: 2 GiB"); } else { ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_2g); ddr3_1333_2g.sdcfg |= 0x1000; ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_2g); + ddr3_size = 1; + printf("DRAM: 1 GiB"); } } else { printf("Unknown SO-DIMM. Cannot configure DDR3\n"); @@ -86,3 +94,11 @@ void ddr3_init(void) if (cpu_revision() <= 1) ddr3_err_reset_workaround(); } + +/** + * ddr3_get_size - return ddr3 size in GiB + */ +int ddr3_get_size(void) +{ + return ddr3_size; +} diff --git a/board/ti/ks2_evm/ddr3_k2l.c b/board/ti/ks2_evm/ddr3_k2l.c new file mode 100644 index 0000000000..15a14f2aaf --- /dev/null +++ b/board/ti/ks2_evm/ddr3_k2l.c @@ -0,0 +1,38 @@ +/* + * Keystone2: DDR3 initialization + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include "ddr3_cfg.h" +#include <asm/arch/ddr3.h> + +static int ddr3_size; +static struct pll_init_data ddr3_400 = DDR3_PLL_400; + +void ddr3_init(void) +{ + init_pll(&ddr3_400); + + /* No SO-DIMM, 2GB discreet DDR */ + printf("DRAM: 2 GiB\n"); + ddr3_size = 2; + + /* Reset DDR3 PHY after PLL enabled */ + ddr3_reset_ddrphy(); + + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_2g); + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_2g); +} + +/** + * ddr3_get_size - return ddr3 size in GiB + */ +int ddr3_get_size(void) +{ + return ddr3_size; +} diff --git a/board/ti/sdp3430/sdp.h b/board/ti/sdp3430/sdp.h index 2acb302591..0e631897e3 100644 --- a/board/ti/sdp3430/sdp.h +++ b/board/ti/sdp3430/sdp.h @@ -265,7 +265,7 @@ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0))\ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0))\ MUX_VAL(CP(SYS_CLKOUT2), (OFF_IN_PD | IEN | PTU | EN | M4))/*GPIO_186*/\ - MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0))\ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0))\ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0))\ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0))\ |