diff options
Diffstat (limited to 'board')
| -rw-r--r-- | board/compulab/cm_t54/cm_t54.c | 6 | ||||
| -rw-r--r-- | board/ti/am335x/Kconfig | 9 | ||||
| -rw-r--r-- | board/ti/am335x/board.c | 19 | ||||
| -rw-r--r-- | board/ti/am335x/mux.c | 156 | ||||
| -rw-r--r-- | board/ti/am43xx/board.c | 1 | ||||
| -rw-r--r-- | board/ti/am43xx/mux.c | 43 | ||||
| -rw-r--r-- | board/ti/dra7xx/evm.c | 31 | ||||
| -rw-r--r-- | board/ti/dra7xx/mux_data.h | 61 | ||||
| -rw-r--r-- | board/ti/ks2_evm/board_k2e.c | 23 | ||||
| -rw-r--r-- | board/ti/ks2_evm/board_k2hk.c | 29 |
10 files changed, 270 insertions, 108 deletions
diff --git a/board/compulab/cm_t54/cm_t54.c b/board/compulab/cm_t54/cm_t54.c index fadfddc077..944b7234d6 100644 --- a/board/compulab/cm_t54/cm_t54.c +++ b/board/compulab/cm_t54/cm_t54.c @@ -43,7 +43,7 @@ const struct omap_sysinfo sysinfo = { */ int board_init(void) { - gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); /* boot param addr */ + gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); return 0; } @@ -89,7 +89,7 @@ uint mmc_get_env_part(struct mmc *mmc) * If booted from eMMC boot partition then force eMMC * FIRST boot partition to be env storage */ - if (bootmode == BOOT_DEVICE_MMC2_2) + if (bootmode == BOOT_DEVICE_MMC2) bootpart = 1; return bootpart; @@ -169,7 +169,7 @@ static int handle_mac_address(void) return 0; ret = cl_eeprom_read_mac_addr(enetaddr); - if (!ret || !is_valid_ether_addr(enetaddr)) + if (ret || !is_valid_ether_addr(enetaddr)) generate_mac_addr(enetaddr); if (!is_valid_ether_addr(enetaddr)) diff --git a/board/ti/am335x/Kconfig b/board/ti/am335x/Kconfig index c3b61af263..0e5149c69c 100644 --- a/board/ti/am335x/Kconfig +++ b/board/ti/am335x/Kconfig @@ -20,4 +20,13 @@ config SYS_CONFIG_NAME string default "am335x_evm" +config CONS_INDEX + int "UART used for console" + default 1 + help + The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced + in documentation, etc) available to it. Depending on your specific + board you may want something other than UART0 as for example the IDK + uses UART3 so enter 4 here. + endif diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index d81eec90b4..0739e6021a 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -383,24 +383,19 @@ const struct dpll_params *get_dpll_ddr_params(void) void set_uart_mux_conf(void) { -#ifdef CONFIG_SERIAL1 +#if CONFIG_CONS_INDEX == 1 enable_uart0_pin_mux(); -#endif /* CONFIG_SERIAL1 */ -#ifdef CONFIG_SERIAL2 +#elif CONFIG_CONS_INDEX == 2 enable_uart1_pin_mux(); -#endif /* CONFIG_SERIAL2 */ -#ifdef CONFIG_SERIAL3 +#elif CONFIG_CONS_INDEX == 3 enable_uart2_pin_mux(); -#endif /* CONFIG_SERIAL3 */ -#ifdef CONFIG_SERIAL4 +#elif CONFIG_CONS_INDEX == 4 enable_uart3_pin_mux(); -#endif /* CONFIG_SERIAL4 */ -#ifdef CONFIG_SERIAL5 +#elif CONFIG_CONS_INDEX == 5 enable_uart4_pin_mux(); -#endif /* CONFIG_SERIAL5 */ -#ifdef CONFIG_SERIAL6 +#elif CONFIG_CONS_INDEX == 6 enable_uart5_pin_mux(); -#endif /* CONFIG_SERIAL6 */ +#endif } void set_mux_conf_regs(void) diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index b2bfda5ea9..f4bb9f890b 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -171,91 +171,75 @@ static struct module_pin_mux mii1_pin_mux[] = { {-1}, }; +#ifdef CONFIG_NAND static struct module_pin_mux nand_pin_mux[] = { - {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ - {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ - {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ - {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ - {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ - {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ - {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ - {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ - {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ - {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ - {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ - {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ - {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ - {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ - {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ + {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */ +#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT + {OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8 */ + {OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9 */ + {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */ + {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */ + {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */ + {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */ + {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */ + {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */ +#endif + {OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* nWAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* nWP */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* nCS */ + {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* WEN */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* OE */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* ADV_ALE */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* BE_CLE */ {-1}, }; - -#if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT) +#elif defined(CONFIG_NOR) static struct module_pin_mux bone_norcape_pin_mux[] = { - {OFFSET(lcd_data0), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A0 */ - {OFFSET(lcd_data1), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A1 */ - {OFFSET(lcd_data2), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A2 */ - {OFFSET(lcd_data3), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A3 */ - {OFFSET(lcd_data4), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A4 */ - {OFFSET(lcd_data5), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A5 */ - {OFFSET(lcd_data6), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A6 */ - {OFFSET(lcd_data7), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A7 */ - {OFFSET(lcd_vsync), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A8 */ - {OFFSET(lcd_hsync), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A9 */ - {OFFSET(lcd_pclk), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A10 */ - {OFFSET(lcd_ac_bias_en), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A11 */ - {OFFSET(lcd_data8), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A12 */ - {OFFSET(lcd_data9), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A13 */ - {OFFSET(lcd_data10), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A14 */ - {OFFSET(lcd_data11), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A15 */ - {OFFSET(lcd_data12), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A16 */ - {OFFSET(lcd_data13), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A17 */ - {OFFSET(lcd_data14), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A18 */ - {OFFSET(lcd_data15), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A19 */ - {OFFSET(gpmc_ad0), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD0 */ - {OFFSET(gpmc_ad1), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD1 */ - {OFFSET(gpmc_ad2), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD2 */ - {OFFSET(gpmc_ad3), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD3 */ - {OFFSET(gpmc_ad4), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD4 */ - {OFFSET(gpmc_ad5), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD5 */ - {OFFSET(gpmc_ad6), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD6 */ - {OFFSET(gpmc_ad7), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD7 */ - {OFFSET(gpmc_ad8), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD8 */ - {OFFSET(gpmc_ad9), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD9 */ - {OFFSET(gpmc_ad10), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD10 */ - {OFFSET(gpmc_ad11), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD11 */ - {OFFSET(gpmc_ad12), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD12 */ - {OFFSET(gpmc_ad13), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD13 */ - {OFFSET(gpmc_ad14), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD14 */ - {OFFSET(gpmc_ad15), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD15 */ - - {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN) | RXACTIVE}, /* NOR_CE */ - {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN) | RXACTIVE}, /* NOR_ADVN_ALE */ - {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_OE */ - {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_BE0N_CLE */ - {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN | RXACTIVE)}, /* NOR_WEN */ - {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUDEN)}, /* NOR WAIT */ + {OFFSET(gpmc_a0), MODE(0) | PULLUDDIS}, /* NOR_A0 */ + {OFFSET(gpmc_a1), MODE(0) | PULLUDDIS}, /* NOR_A1 */ + {OFFSET(gpmc_a2), MODE(0) | PULLUDDIS}, /* NOR_A2 */ + {OFFSET(gpmc_a3), MODE(0) | PULLUDDIS}, /* NOR_A3 */ + {OFFSET(gpmc_a4), MODE(0) | PULLUDDIS}, /* NOR_A4 */ + {OFFSET(gpmc_a5), MODE(0) | PULLUDDIS}, /* NOR_A5 */ + {OFFSET(gpmc_a6), MODE(0) | PULLUDDIS}, /* NOR_A6 */ + {OFFSET(gpmc_a7), MODE(0) | PULLUDDIS}, /* NOR_A7 */ + {OFFSET(gpmc_ad0), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD0 */ + {OFFSET(gpmc_ad1), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD1 */ + {OFFSET(gpmc_ad2), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD2 */ + {OFFSET(gpmc_ad3), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD3 */ + {OFFSET(gpmc_ad4), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD4 */ + {OFFSET(gpmc_ad5), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD5 */ + {OFFSET(gpmc_ad6), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD6 */ + {OFFSET(gpmc_ad7), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD7 */ + {OFFSET(gpmc_ad8), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD8 */ + {OFFSET(gpmc_ad9), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD9 */ + {OFFSET(gpmc_ad10), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD10 */ + {OFFSET(gpmc_ad11), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD11 */ + {OFFSET(gpmc_ad12), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD12 */ + {OFFSET(gpmc_ad13), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD13 */ + {OFFSET(gpmc_ad14), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD14 */ + {OFFSET(gpmc_ad15), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD15 */ + {OFFSET(gpmc_csn0), MODE(0) | PULLUDEN | PULLUP_EN}, /* CE */ + {OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* ALE */ + {OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN | PULLDOWN_EN},/* OEn_REN */ + {OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN | PULLDOWN_EN},/* unused */ + {OFFSET(gpmc_wen), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* WEN */ + {OFFSET(gpmc_wait0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},/*WAIT*/ {-1}, }; #endif #if defined(CONFIG_NOR_BOOT) -static struct module_pin_mux norboot_pin_mux[] = { - {OFFSET(lcd_data1), MODE(1) | PULLUDDIS}, - {OFFSET(lcd_data2), MODE(1) | PULLUDDIS}, - {OFFSET(lcd_data3), MODE(1) | PULLUDDIS}, - {OFFSET(lcd_data4), MODE(1) | PULLUDDIS}, - {OFFSET(lcd_data5), MODE(1) | PULLUDDIS}, - {OFFSET(lcd_data6), MODE(1) | PULLUDDIS}, - {OFFSET(lcd_data7), MODE(1) | PULLUDDIS}, - {OFFSET(lcd_data8), MODE(1) | PULLUDDIS}, - {OFFSET(lcd_data9), MODE(1) | PULLUDDIS}, - {-1}, -}; - void enable_norboot_pin_mux(void) { - configure_module_pin_mux(norboot_pin_mux); + configure_module_pin_mux(bone_norcape_pin_mux); } #endif @@ -336,11 +320,12 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header) configure_module_pin_mux(i2c1_pin_mux); configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); -#ifndef CONFIG_NOR - configure_module_pin_mux(mmc1_pin_mux); -#endif -#if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT) +#if defined(CONFIG_NAND) + configure_module_pin_mux(nand_pin_mux); +#elif defined(CONFIG_NOR) configure_module_pin_mux(bone_norcape_pin_mux); +#else + configure_module_pin_mux(mmc1_pin_mux); #endif } else if (board_is_gp_evm(header)) { /* General Purpose EVM */ @@ -351,19 +336,16 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header) if (profile & ~PROFILE_2) configure_module_pin_mux(i2c1_pin_mux); /* Profiles 2 & 3 don't have NAND */ +#ifdef CONFIG_NAND if (profile & ~(PROFILE_2 | PROFILE_3)) configure_module_pin_mux(nand_pin_mux); +#endif else if (profile == PROFILE_2) { configure_module_pin_mux(mmc1_pin_mux); configure_module_pin_mux(spi0_pin_mux); } } else if (board_is_idk(header)) { - /* - * Industrial Motor Control (IDK) - * note: IDK console is on UART3 by default. - * So u-boot mus be build with CONFIG_SERIAL4 and - * CONFIG_CONS_INDEX=4 - */ + /* Industrial Motor Control (IDK) */ configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_no_cd_pin_mux); } else if (board_is_evm_sk(header)) { @@ -377,7 +359,13 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header) configure_module_pin_mux(i2c1_pin_mux); configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); +#if defined(CONFIG_NAND) + configure_module_pin_mux(nand_pin_mux); +#elif defined(CONFIG_NOR) + configure_module_pin_mux(bone_norcape_pin_mux); +#else configure_module_pin_mux(mmc1_pin_mux); +#endif } else { puts("Unknown board, cannot configure pinmux."); hang(); diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 51fa9e04a3..a1c3c17fed 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -626,6 +626,7 @@ int board_init(void) modena_init0_bw_integer, modena_init0_watermark_0; gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gpmc_init(); /* Clear all important bits for DSS errata that may need to be tweaked*/ mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK & diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c index 50967e1a82..a670b0b2ff 100644 --- a/board/ti/am43xx/mux.c +++ b/board/ti/am43xx/mux.c @@ -73,7 +73,38 @@ static struct module_pin_mux gpio5_7_pin_mux[] = { {-1}, }; -static struct module_pin_mux qspi_pin_mux[] = { +#ifdef CONFIG_NAND +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */ +#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT + {OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8 */ + {OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9 */ + {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */ + {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */ + {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */ + {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */ + {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */ + {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */ +#endif + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* Wait */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* Write Protect */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* Chip-Select */ + {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* Write Enable */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* Read Enable */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* Addr Latch Enable*/ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* Byte Enable */ + {-1}, +}; +#endif + +static __maybe_unused struct module_pin_mux qspi_pin_mux[] = { {OFFSET(gpmc_csn0), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_CS0 */ {OFFSET(gpmc_csn3), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* QSPI_CLK */ {OFFSET(gpmc_advn_ale), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D0 */ @@ -97,12 +128,22 @@ void enable_board_pin_mux(void) if (board_is_gpevm()) { configure_module_pin_mux(gpio5_7_pin_mux); configure_module_pin_mux(rgmii1_pin_mux); +#if defined(CONFIG_NAND) + configure_module_pin_mux(nand_pin_mux); +#endif } else if (board_is_sk()) { configure_module_pin_mux(rgmii1_pin_mux); +#if defined(CONFIG_NAND) + printf("Error: NAND flash not present on this board\n"); +#endif configure_module_pin_mux(qspi_pin_mux); } else if (board_is_eposevm()) { configure_module_pin_mux(rmii1_pin_mux); +#if defined(CONFIG_NAND) + configure_module_pin_mux(nand_pin_mux); +#else configure_module_pin_mux(qspi_pin_mux); +#endif } } diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index ae50d88c57..5592fc5def 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -13,6 +13,8 @@ #include <common.h> #include <palmas.h> #include <sata.h> +#include <asm/gpio.h> +#include <asm/arch/gpio.h> #include <asm/arch/sys_proto.h> #include <asm/arch/mmc_host_def.h> #include <asm/arch/sata.h> @@ -26,6 +28,9 @@ DECLARE_GLOBAL_DATA_PTR; +/* GPIO 7_11 */ +#define GPIO_DDR_VTT_EN 203 + const struct omap_sysinfo sysinfo = { "Board: DRA7xx\n" }; @@ -272,3 +277,29 @@ int board_eth_init(bd_t *bis) return ret; } #endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +/* VTT regulator enable */ +static inline void vtt_regulator_enable(void) +{ + if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) + return; + + /* Do not enable VTT for DRA722 */ + if (omap_revision() == DRA722_ES1_0) + return; + + /* + * EVM Rev G and later use gpio7_11 for DDR3 termination. + * This is safe enough to do on older revs. + */ + gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); + gpio_direction_output(GPIO_DDR_VTT_EN, 1); +} + +int board_early_init_f(void) +{ + vtt_regulator_enable(); + return 0; +} +#endif diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index 7db70324e9..7276014f1d 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -21,6 +21,37 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */ {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */ {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */ +#if defined(CONFIG_NOR) + /* NOR only pin-mux */ + {GPMC_A0 , M0 | IDIS | PDIS}, /* nor.GPMC_A[0 ] */ + {GPMC_A1 , M0 | IDIS | PDIS}, /* nor.GPMC_A[1 ] */ + {GPMC_A2 , M0 | IDIS | PDIS}, /* nor.GPMC_A[2 ] */ + {GPMC_A3 , M0 | IDIS | PDIS}, /* nor.GPMC_A[3 ] */ + {GPMC_A4 , M0 | IDIS | PDIS}, /* nor.GPMC_A[4 ] */ + {GPMC_A5 , M0 | IDIS | PDIS}, /* nor.GPMC_A[5 ] */ + {GPMC_A6 , M0 | IDIS | PDIS}, /* nor.GPMC_A[6 ] */ + {GPMC_A7 , M0 | IDIS | PDIS}, /* nor.GPMC_A[7 ] */ + {GPMC_A8 , M0 | IDIS | PDIS}, /* nor.GPMC_A[8 ] */ + {GPMC_A9 , M0 | IDIS | PDIS}, /* nor.GPMC_A[9 ] */ + {GPMC_A10 , M0 | IDIS | PDIS}, /* nor.GPMC_A[10] */ + {GPMC_A11 , M0 | IDIS | PDIS}, /* nor.GPMC_A[11] */ + {GPMC_A12 , M0 | IDIS | PDIS}, /* nor.GPMC_A[12] */ + {GPMC_A13 , M0 | IDIS | PDIS}, /* nor.GPMC_A[13] */ + {GPMC_A14 , M0 | IDIS | PDIS}, /* nor.GPMC_A[14] */ + {GPMC_A15 , M0 | IDIS | PDIS}, /* nor.GPMC_A[15] */ + {GPMC_A16 , M0 | IDIS | PDIS}, /* nor.GPMC_A[16] */ + {GPMC_A17 , M0 | IDIS | PDIS}, /* nor.GPMC_A[17] */ + {GPMC_A18 , M0 | IDIS | PDIS}, /* nor.GPMC_A[18] */ + {GPMC_A19 , M0 | IDIS | PDIS}, /* nor.GPMC_A[19] */ + {GPMC_A20 , M0 | IDIS | PDIS}, /* nor.GPMC_A[20] */ + {GPMC_A21 , M0 | IDIS | PDIS}, /* nor.GPMC_A[21] */ + {GPMC_A22 , M0 | IDIS | PDIS}, /* nor.GPMC_A[22] */ + {GPMC_A23 , M0 | IDIS | PDIS}, /* nor.GPMC_A[23] */ + {GPMC_A24 , M0 | IDIS | PDIS}, /* nor.GPMC_A[24] */ + {GPMC_A25 , M0 | IDIS | PDIS}, /* nor.GPMC_A[25] */ + {GPMC_A26 , M0 | IDIS | PDIS}, /* nor.GPMC_A[26] */ +#else + /* eMMC pinmux */ {GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */ {GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */ {GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */ @@ -31,6 +62,7 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */ {GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */ {GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */ +#endif #if (CONFIG_CONS_INDEX == 1) {UART1_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_RXD */ {UART1_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_TXD */ @@ -68,6 +100,33 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {VIN2A_D21, (IEN | M3)}, {VIN2A_D22, (IEN | M3)}, {VIN2A_D23, (IEN | M3)}, +#if defined(CONFIG_NAND) || defined(CONFIG_NOR) + /* NAND / NOR pin-mux */ + {GPMC_AD0 , M0 | IEN | PDIS}, /* GPMC_AD0 */ + {GPMC_AD1 , M0 | IEN | PDIS}, /* GPMC_AD1 */ + {GPMC_AD2 , M0 | IEN | PDIS}, /* GPMC_AD2 */ + {GPMC_AD3 , M0 | IEN | PDIS}, /* GPMC_AD3 */ + {GPMC_AD4 , M0 | IEN | PDIS}, /* GPMC_AD4 */ + {GPMC_AD5 , M0 | IEN | PDIS}, /* GPMC_AD5 */ + {GPMC_AD6 , M0 | IEN | PDIS}, /* GPMC_AD6 */ + {GPMC_AD7 , M0 | IEN | PDIS}, /* GPMC_AD7 */ + {GPMC_AD8 , M0 | IEN | PDIS}, /* GPMC_AD8 */ + {GPMC_AD9 , M0 | IEN | PDIS}, /* GPMC_AD9 */ + {GPMC_AD10, M0 | IEN | PDIS}, /* GPMC_AD10 */ + {GPMC_AD11, M0 | IEN | PDIS}, /* GPMC_AD11 */ + {GPMC_AD12, M0 | IEN | PDIS}, /* GPMC_AD12 */ + {GPMC_AD13, M0 | IEN | PDIS}, /* GPMC_AD13 */ + {GPMC_AD14, M0 | IEN | PDIS}, /* GPMC_AD14 */ + {GPMC_AD15, M0 | IEN | PDIS}, /* GPMC_AD15 */ + {GPMC_CS0, M0 | IDIS | PEN | PTU}, /* GPMC chip-select */ + {GPMC_ADVN_ALE, M0 | IDIS | PEN | PTD}, /* GPMC Addr latch */ + {GPMC_OEN_REN, M0 | IDIS | PEN | PTU}, /* GPMC Read enable */ + {GPMC_WEN, M0 | IDIS | PEN | PTU}, /* GPMC Write enable_n */ + {GPMC_BEN0, M0 | IDIS | PEN | PTD}, /* GPMC Byte/Column En */ + {GPMC_WAIT0, M0 | IEN | PEN | PTU}, /* GPMC Wait/Ready */ + /* GPMC_WPN (Write Protect) is controlled by DIP Switch SW10(12) */ +#else + /* QSPI pin-mux */ {GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */ {GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */ {GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */ @@ -78,6 +137,8 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {GPMC_A4, (IEN | PDIS | M1)}, /* QSPI1_CS3 */ {GPMC_CS2, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS0 */ {GPMC_CS3, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS1*/ +#endif /* CONFIG_NAND || CONFIG_NOR */ {USB2_DRVVBUS, (M0 | IEN | FSC) }, + {SPI1_CS1, (PEN | IDIS | M14) }, }; #endif /* _MUX_DATA_DRA7XX_H_ */ diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c index d2499b7244..5472a43c43 100644 --- a/board/ti/ks2_evm/board_k2e.c +++ b/board/ti/ks2_evm/board_k2e.c @@ -25,15 +25,30 @@ unsigned int external_clk[ext_clk_count] = { [usb_clk] = 100000000, }; -static struct pll_init_data pll_config[] = { - CORE_PLL_1200, - PASS_PLL_1000, +static struct pll_init_data core_pll_config[] = { + CORE_PLL_800, + CORE_PLL_850, + CORE_PLL_1000, + CORE_PLL_1250, + CORE_PLL_1350, + CORE_PLL_1400, + CORE_PLL_1500, }; + +static struct pll_init_data pa_pll_config = + PASS_PLL_1000; + #if defined(CONFIG_BOARD_EARLY_INIT_F) int board_early_init_f(void) { - init_plls(ARRAY_SIZE(pll_config), pll_config); + int speed; + + speed = get_max_dev_speed(); + init_pll(&core_pll_config[speed]); + + init_pll(&pa_pll_config); + return 0; } #endif diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c index a369d6bd63..6fb3d2123d 100644 --- a/board/ti/ks2_evm/board_k2hk.c +++ b/board/ti/ks2_evm/board_k2hk.c @@ -8,6 +8,7 @@ */ #include <common.h> +#include <asm/arch/clock.h> #include <asm/arch/hardware.h> #include <asm/arch/emac_defs.h> @@ -28,12 +29,23 @@ unsigned int external_clk[ext_clk_count] = { [rp1_clk] = 123456789 }; -static struct pll_init_data pll_config[] = { - CORE_PLL_1228, - PASS_PLL_983, +static struct pll_init_data core_pll_config[] = { + CORE_PLL_799, + CORE_PLL_999, + CORE_PLL_1200, +}; + +static struct pll_init_data tetris_pll_config[] = { + TETRIS_PLL_800, + TETRIS_PLL_1000, TETRIS_PLL_1200, + TETRIS_PLL_1350, + TETRIS_PLL_1400, }; +static struct pll_init_data pa_pll_config = + PASS_PLL_983; + #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET struct eth_priv_t eth_priv_cfg[] = { { @@ -75,7 +87,16 @@ int get_num_eth_ports(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { - init_plls(ARRAY_SIZE(pll_config), pll_config); + int speed; + + speed = get_max_dev_speed(); + init_pll(&core_pll_config[speed]); + + init_pll(&pa_pll_config); + + speed = get_max_arm_speed(); + init_pll(&tetris_pll_config[speed]); + return 0; } #endif |