8 files changed, 2951 insertions, 0 deletions

diff --git a/board/renesas/koelsch/Makefile b/board/renesas/koelsch/Makefile
new file mode 100644
index 0000000000..b4d0183b3b
--- /dev/null
+++ b/board/renesas/koelsch/Makefile
@@ -0,0 +1,9 @@
+#
+# board/renesas/koelsch/Makefile
+#
+# Copyright (C) 2013 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y	:= koelsch.o qos.o
diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c
new file mode 100644
index 0000000000..7153f652b5
--- /dev/null
+++ b/board/renesas/koelsch/koelsch.c
@@ -0,0 +1,283 @@
+/*
+ * board/renesas/koelsch/koelsch.c
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <i2c.h>
+#include "qos.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define s_init_wait(cnt) \
+	({	\
+		u32 i = 0x10000 * cnt;	\
+		while (i > 0)	\
+			i--;	\
+	})
+
+
+#define dbpdrgd_check(bsc) \
+	({	\
+		while ((readl(&bsc->dbpdrgd) & 0x1) != 0x1)	\
+			;	\
+	})
+
+#if defined(CONFIG_NORFLASH)
+static void bsc_init(void)
+{
+	struct r8a7791_lbsc *lbsc = (struct r8a7791_lbsc *)LBSC_BASE;
+	struct r8a7791_dbsc3 *dbsc3_0 = (struct r8a7791_dbsc3 *)DBSC3_0_BASE;
+
+	/* LBSC */
+	writel(0x00000020, &lbsc->cs0ctrl);
+	writel(0x00000020, &lbsc->cs1ctrl);
+	writel(0x00002020, &lbsc->ecs0ctrl);
+	writel(0x00002020, &lbsc->ecs1ctrl);
+
+	writel(0x077F077F, &lbsc->cswcr0);
+	writel(0x077F077F, &lbsc->cswcr1);
+	writel(0x077F077F, &lbsc->ecswcr0);
+	writel(0x077F077F, &lbsc->ecswcr1);
+
+	/* DBSC3 */
+	s_init_wait(10);
+
+	writel(0x0000A55A, &dbsc3_0->dbpdlck);
+	writel(0x00000001, &dbsc3_0->dbpdrga);
+	writel(0x80000000, &dbsc3_0->dbpdrgd);
+	writel(0x00000004, &dbsc3_0->dbpdrga);
+	dbpdrgd_check(dbsc3_0);
+
+	writel(0x00000006, &dbsc3_0->dbpdrga);
+	writel(0x0001C000, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000023, &dbsc3_0->dbpdrga);
+	writel(0x00FD2480, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000010, &dbsc3_0->dbpdrga);
+	writel(0xF004649B, &dbsc3_0->dbpdrgd);
+
+	writel(0x0000000F, &dbsc3_0->dbpdrga);
+	writel(0x00181EE4, &dbsc3_0->dbpdrgd);
+
+	writel(0x0000000E, &dbsc3_0->dbpdrga);
+	writel(0x33C03812, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000003, &dbsc3_0->dbpdrga);
+	writel(0x0300C481, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000007, &dbsc3_0->dbkind);
+	writel(0x10030A02, &dbsc3_0->dbconf0);
+	writel(0x00000001, &dbsc3_0->dbphytype);
+	writel(0x00000000, &dbsc3_0->dbbl);
+	writel(0x0000000B, &dbsc3_0->dbtr0);
+	writel(0x00000008, &dbsc3_0->dbtr1);
+	writel(0x00000000, &dbsc3_0->dbtr2);
+	writel(0x0000000B, &dbsc3_0->dbtr3);
+	writel(0x000C000B, &dbsc3_0->dbtr4);
+	writel(0x00000027, &dbsc3_0->dbtr5);
+	writel(0x0000001C, &dbsc3_0->dbtr6);
+	writel(0x00000005, &dbsc3_0->dbtr7);
+	writel(0x00000018, &dbsc3_0->dbtr8);
+	writel(0x00000008, &dbsc3_0->dbtr9);
+	writel(0x0000000C, &dbsc3_0->dbtr10);
+	writel(0x00000009, &dbsc3_0->dbtr11);
+	writel(0x00000012, &dbsc3_0->dbtr12);
+	writel(0x000000D0, &dbsc3_0->dbtr13);
+	writel(0x00140005, &dbsc3_0->dbtr14);
+	writel(0x00050004, &dbsc3_0->dbtr15);
+	writel(0x70233005, &dbsc3_0->dbtr16);
+	writel(0x000C0000, &dbsc3_0->dbtr17);
+	writel(0x00000300, &dbsc3_0->dbtr18);
+	writel(0x00000040, &dbsc3_0->dbtr19);
+	writel(0x00000001, &dbsc3_0->dbrnk0);
+	writel(0x00020001, &dbsc3_0->dbadj0);
+	writel(0x20082008, &dbsc3_0->dbadj2);
+	writel(0x00020002, &dbsc3_0->dbwt0cnf0);
+	writel(0x0000000F, &dbsc3_0->dbwt0cnf4);
+
+	writel(0x00000015, &dbsc3_0->dbpdrga);
+	writel(0x00000D70, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000016, &dbsc3_0->dbpdrga);
+	writel(0x00000006, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000017, &dbsc3_0->dbpdrga);
+	writel(0x00000018, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000012, &dbsc3_0->dbpdrga);
+	writel(0x9D5CBB66, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000013, &dbsc3_0->dbpdrga);
+	writel(0x1A868300, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000023, &dbsc3_0->dbpdrga);
+	writel(0x00FDB6C0, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000014, &dbsc3_0->dbpdrga);
+	writel(0x300214D8, &dbsc3_0->dbpdrgd);
+
+	writel(0x0000001A, &dbsc3_0->dbpdrga);
+	writel(0x930035C7, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000060, &dbsc3_0->dbpdrga);
+	writel(0x330657B2, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000011, &dbsc3_0->dbpdrga);
+	writel(0x1000040B, &dbsc3_0->dbpdrgd);
+
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x00000001, &dbsc3_0->dbpdrga);
+	writel(0x00000071, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000004, &dbsc3_0->dbpdrga);
+	dbpdrgd_check(dbsc3_0);
+
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x2100FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+
+	writel(0x110000DB, &dbsc3_0->dbcmd);
+
+	writel(0x00000001, &dbsc3_0->dbpdrga);
+	writel(0x00000181, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000004, &dbsc3_0->dbpdrga);
+	dbpdrgd_check(dbsc3_0);
+
+	writel(0x00000001, &dbsc3_0->dbpdrga);
+	writel(0x0000FE01, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000004, &dbsc3_0->dbpdrga);
+	dbpdrgd_check(dbsc3_0);
+
+	writel(0x00000000, &dbsc3_0->dbbs0cnt1);
+	writel(0x01004C20, &dbsc3_0->dbcalcnf);
+	writel(0x014000AA, &dbsc3_0->dbcaltr);
+	writel(0x00000140, &dbsc3_0->dbrfcnf0);
+	writel(0x00081860, &dbsc3_0->dbrfcnf1);
+	writel(0x00010000, &dbsc3_0->dbrfcnf2);
+	writel(0x00000001, &dbsc3_0->dbrfen);
+	writel(0x00000001, &dbsc3_0->dbacen);
+}
+#else
+#define bsc_init() do {} while (0)
+#endif /* CONFIG_NORFLASH */
+
+void s_init(void)
+{
+	struct r8a7791_rwdt *rwdt = (struct r8a7791_rwdt *)RWDT_BASE;
+	struct r8a7791_swdt *swdt = (struct r8a7791_swdt *)SWDT_BASE;
+
+	/* Watchdog init */
+	writel(0xA5A5A500, &rwdt->rwtcsra);
+	writel(0xA5A5A500, &swdt->swtcsra);
+
+	/* QoS */
+	qos_init();
+
+	/* BSC */
+	bsc_init();
+}
+
+#define MSTPSR1		0xE6150038
+#define SMSTPCR1	0xE6150134
+#define TMU0_MSTP125	(1 << 25)
+
+#define MSTPSR7		0xE61501C4
+#define SMSTPCR7	0xE615014C
+#define SCIF0_MSTP721	(1 << 21)
+
+#define PMMR	0xE6060000
+#define GPSR4	0xE6060014
+#define IPSR14	0xE6060058
+
+#define set_guard_reg(addr, mask, value)	\
+{ \
+	u32 val; \
+	val = (readl(addr) & ~(mask)) | (value); \
+	writel(~val, PMMR); \
+	writel(val, addr); \
+}
+
+#define mstp_setbits(type, addr, saddr, set) \
+	out_##type((saddr), in_##type(addr) | (set))
+#define mstp_clrbits(type, addr, saddr, clear) \
+	out_##type((saddr), in_##type(addr) & ~(clear))
+#define mstp_setbits_le32(addr, saddr, set) \
+	mstp_setbits(le32, addr, saddr, set)
+#define mstp_clrbits_le32(addr, saddr, clear)   \
+	mstp_clrbits(le32, addr, saddr, clear)
+
+int board_early_init_f(void)
+{
+	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+
+#if defined(CONFIG_NORFLASH)
+	/* SCIF0 */
+	set_guard_reg(GPSR4, 0x34000000, 0x00000000);
+	set_guard_reg(IPSR14, 0x00000FC7, 0x00000481);
+	set_guard_reg(GPSR4, 0x00000000, 0x34000000);
+#endif
+
+	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = KOELSCH_SDRAM_BASE + 0x100;
+
+	/* Init PFC controller */
+	r8a7791_pinmux_init();
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+const struct rmobile_sysinfo sysinfo = {
+	CONFIG_RMOBILE_BOARD_STRING
+};
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = KOELSCH_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = KOELSCH_SDRAM_SIZE;
+}
+
+int board_late_init(void)
+{
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+}
diff --git a/board/renesas/koelsch/qos.c b/board/renesas/koelsch/qos.c
new file mode 100644
index 0000000000..7f88f7da8d
--- /dev/null
+++ b/board/renesas/koelsch/qos.c
@@ -0,0 +1,1220 @@
+/*
+ * board/renesas/koelsch/qos.c
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/arch/rmobile.h>
+
+/* QoS version 0.23 */
+
+enum {
+	DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
+	DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
+	DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
+	DBSC3_15,
+	DBSC3_NR,
+};
+
+static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_0_QOS_R0_BASE,
+	[DBSC3_01] = DBSC3_0_QOS_R1_BASE,
+	[DBSC3_02] = DBSC3_0_QOS_R2_BASE,
+	[DBSC3_03] = DBSC3_0_QOS_R3_BASE,
+	[DBSC3_04] = DBSC3_0_QOS_R4_BASE,
+	[DBSC3_05] = DBSC3_0_QOS_R5_BASE,
+	[DBSC3_06] = DBSC3_0_QOS_R6_BASE,
+	[DBSC3_07] = DBSC3_0_QOS_R7_BASE,
+	[DBSC3_08] = DBSC3_0_QOS_R8_BASE,
+	[DBSC3_09] = DBSC3_0_QOS_R9_BASE,
+	[DBSC3_10] = DBSC3_0_QOS_R10_BASE,
+	[DBSC3_11] = DBSC3_0_QOS_R11_BASE,
+	[DBSC3_12] = DBSC3_0_QOS_R12_BASE,
+	[DBSC3_13] = DBSC3_0_QOS_R13_BASE,
+	[DBSC3_14] = DBSC3_0_QOS_R14_BASE,
+	[DBSC3_15] = DBSC3_0_QOS_R15_BASE,
+};
+
+static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_0_QOS_W0_BASE,
+	[DBSC3_01] = DBSC3_0_QOS_W1_BASE,
+	[DBSC3_02] = DBSC3_0_QOS_W2_BASE,
+	[DBSC3_03] = DBSC3_0_QOS_W3_BASE,
+	[DBSC3_04] = DBSC3_0_QOS_W4_BASE,
+	[DBSC3_05] = DBSC3_0_QOS_W5_BASE,
+	[DBSC3_06] = DBSC3_0_QOS_W6_BASE,
+	[DBSC3_07] = DBSC3_0_QOS_W7_BASE,
+	[DBSC3_08] = DBSC3_0_QOS_W8_BASE,
+	[DBSC3_09] = DBSC3_0_QOS_W9_BASE,
+	[DBSC3_10] = DBSC3_0_QOS_W10_BASE,
+	[DBSC3_11] = DBSC3_0_QOS_W11_BASE,
+	[DBSC3_12] = DBSC3_0_QOS_W12_BASE,
+	[DBSC3_13] = DBSC3_0_QOS_W13_BASE,
+	[DBSC3_14] = DBSC3_0_QOS_W14_BASE,
+	[DBSC3_15] = DBSC3_0_QOS_W15_BASE,
+};
+
+static u32 dbsc3_1_r_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_1_QOS_R0_BASE,
+	[DBSC3_01] = DBSC3_1_QOS_R1_BASE,
+	[DBSC3_02] = DBSC3_1_QOS_R2_BASE,
+	[DBSC3_03] = DBSC3_1_QOS_R3_BASE,
+	[DBSC3_04] = DBSC3_1_QOS_R4_BASE,
+	[DBSC3_05] = DBSC3_1_QOS_R5_BASE,
+	[DBSC3_06] = DBSC3_1_QOS_R6_BASE,
+	[DBSC3_07] = DBSC3_1_QOS_R7_BASE,
+	[DBSC3_08] = DBSC3_1_QOS_R8_BASE,
+	[DBSC3_09] = DBSC3_1_QOS_R9_BASE,
+	[DBSC3_10] = DBSC3_1_QOS_R10_BASE,
+	[DBSC3_11] = DBSC3_1_QOS_R11_BASE,
+	[DBSC3_12] = DBSC3_1_QOS_R12_BASE,
+	[DBSC3_13] = DBSC3_1_QOS_R13_BASE,
+	[DBSC3_14] = DBSC3_1_QOS_R14_BASE,
+	[DBSC3_15] = DBSC3_1_QOS_R15_BASE,
+};
+
+static u32 dbsc3_1_w_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_1_QOS_W0_BASE,
+	[DBSC3_01] = DBSC3_1_QOS_W1_BASE,
+	[DBSC3_02] = DBSC3_1_QOS_W2_BASE,
+	[DBSC3_03] = DBSC3_1_QOS_W3_BASE,
+	[DBSC3_04] = DBSC3_1_QOS_W4_BASE,
+	[DBSC3_05] = DBSC3_1_QOS_W5_BASE,
+	[DBSC3_06] = DBSC3_1_QOS_W6_BASE,
+	[DBSC3_07] = DBSC3_1_QOS_W7_BASE,
+	[DBSC3_08] = DBSC3_1_QOS_W8_BASE,
+	[DBSC3_09] = DBSC3_1_QOS_W9_BASE,
+	[DBSC3_10] = DBSC3_1_QOS_W10_BASE,
+	[DBSC3_11] = DBSC3_1_QOS_W11_BASE,
+	[DBSC3_12] = DBSC3_1_QOS_W12_BASE,
+	[DBSC3_13] = DBSC3_1_QOS_W13_BASE,
+	[DBSC3_14] = DBSC3_1_QOS_W14_BASE,
+	[DBSC3_15] = DBSC3_1_QOS_W15_BASE,
+};
+
+void qos_init(void)
+{
+	int i;
+	struct r8a7791_s3c *s3c;
+	struct r8a7791_s3c_qos *s3c_qos;
+	struct r8a7791_dbsc3_qos *qos_addr;
+	struct r8a7791_mxi *mxi;
+	struct r8a7791_mxi_qos *mxi_qos;
+	struct r8a7791_axi_qos *axi_qos;
+
+	/* DBSC DBADJ2 */
+	writel(0x20042004, DBSC3_0_DBADJ2);
+
+	/* S3C -QoS */
+	s3c = (struct r8a7791_s3c *)S3C_BASE;
+	writel(0x00FF1B1D, &s3c->s3cadsplcr);
+	writel(0x1F0D0C0C, &s3c->s3crorr);
+	writel(0x1F0D0C0A, &s3c->s3cworr);
+
+	/* QoS Control Registers */
+	s3c_qos = (struct r8a7791_s3c_qos *)S3C_QOS_CCI0_BASE;
+	writel(0x00890089, &s3c_qos->s3cqos0);
+	writel(0x20960010, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA2200, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960010, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA2200, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct r8a7791_s3c_qos *)S3C_QOS_CCI1_BASE;
+	writel(0x00890089, &s3c_qos->s3cqos0);
+	writel(0x20960010, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA2200, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960010, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA2200, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct r8a7791_s3c_qos *)S3C_QOS_MXI_BASE;
+	writel(0x00820082, &s3c_qos->s3cqos0);
+	writel(0x20960020, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA20DC, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960020, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA20DC, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct r8a7791_s3c_qos *)S3C_QOS_AXI_BASE;
+	writel(0x00820082, &s3c_qos->s3cqos0);
+	writel(0x20960020, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA20FA, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960020, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA20FA, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	/* DBSC -QoS */
+	/* DBSC0 - Read */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct r8a7791_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x00002096, &qos_addr->dbtmval0);
+		writel(0x00002064, &qos_addr->dbtmval1);
+		writel(0x00002032, &qos_addr->dbtmval2);
+		writel(0x00001FB0, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002078, &qos_addr->dbthres0);
+		writel(0x0000204B, &qos_addr->dbthres1);
+		writel(0x00001FE7, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* DBSC0 - Write */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct r8a7791_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x000020EB, &qos_addr->dbtmval0);
+		writel(0x0000206E, &qos_addr->dbtmval1);
+		writel(0x00002050, &qos_addr->dbtmval2);
+		writel(0x0000203A, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002078, &qos_addr->dbthres0);
+		writel(0x0000205A, &qos_addr->dbthres1);
+		writel(0x0000203C, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* DBSC1 - Read */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct r8a7791_dbsc3_qos *)dbsc3_1_r_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x00002096, &qos_addr->dbtmval0);
+		writel(0x00002064, &qos_addr->dbtmval1);
+		writel(0x00002032, &qos_addr->dbtmval2);
+		writel(0x00001FB0, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002078, &qos_addr->dbthres0);
+		writel(0x0000204B, &qos_addr->dbthres1);
+		writel(0x00001FE7, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* DBSC1 - Write */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct r8a7791_dbsc3_qos *)dbsc3_1_w_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x000020EB, &qos_addr->dbtmval0);
+		writel(0x0000206E, &qos_addr->dbtmval1);
+		writel(0x00002050, &qos_addr->dbtmval2);
+		writel(0x0000203A, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002078, &qos_addr->dbthres0);
+		writel(0x0000205A, &qos_addr->dbthres1);
+		writel(0x0000203C, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* CCI-400 -QoS */
+	writel(0x20001000, CCI_400_MAXOT_1);
+	writel(0x20001000, CCI_400_MAXOT_2);
+	writel(0x0000000C, CCI_400_QOSCNTL_1);
+	writel(0x0000000C, CCI_400_QOSCNTL_2);
+
+	/* MXI -QoS */
+	/* Transaction Control (MXI) */
+	mxi = (struct r8a7791_mxi *)MXI_BASE;
+	writel(0x00000013, &mxi->mxrtcr);
+	writel(0x00000013, &mxi->mxwtcr);
+	writel(0x00780080, &mxi->mxsaar0);
+	writel(0x02000800, &mxi->mxsaar1);
+
+	/* QoS Control (MXI) */
+	mxi_qos = (struct r8a7791_mxi_qos *)MXI_QOS_BASE;
+	writel(0x0000000C, &mxi_qos->vspdu0);
+	writel(0x0000000C, &mxi_qos->vspdu1);
+	writel(0x0000000D, &mxi_qos->du0);
+	writel(0x0000000D, &mxi_qos->du1);
+
+	/* AXI -QoS */
+	/* Transaction Control (MXI) */
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_AVB_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_G2D_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_IMP0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002021, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_IMP1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002037, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_IMUX0_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_IMUX1_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_IMUX2_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_LBS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MMUDS_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MMUM_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MMUR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MMUS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MMUS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MTSB0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002021, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MTSB1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002021, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_PCI_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_RTX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SDS0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SDS1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_USB20_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_USB21_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_USB22_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_USB30_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_AX2M_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_CC50_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_CCI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_CS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_DDM_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_ETH_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MPXM_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SAT0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SAT1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SDM0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SDM1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_TRAB_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_UDM0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_UDM1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (RT-AXI) */
+	axi_qos = (struct r8a7791_axi_qos *)RT_AXI_SHX_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)RT_AXI_DBG_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)RT_AXI_RDM_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002299, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)RT_AXI_RDS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)RT_AXI_RTX64TO128_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)RT_AXI_STPRO_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)RT_AXI_SY2RT_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (MP-AXI) */
+	axi_qos = (struct r8a7791_axi_qos *)MP_AXI_ADSP_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002037, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MP_AXI_ASDS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MP_AXI_ASDS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MP_AXI_MLP_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MP_AXI_MMUMP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MP_AXI_SPU_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MP_AXI_SPUC_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000206E, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (SYS-AXI256) */
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI256_SYX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI256_MPX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI256_MXI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (CCI-AXI) */
+	axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_SYX2_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUDS_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUM_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MXI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUMP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (Media-AXI) */
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_MXR_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020DC, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x000020AA, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_MXW_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020DC, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x000020AA, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_JPR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_JPW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_TDMR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_TDMW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_FDP0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_FDP0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_IMSR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_IMSW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSP1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSP1W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_FDP1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_FDP1W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_IMRR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_IMRW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_DU0R_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002063, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_DU0W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002063, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VPC0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+}
diff --git a/board/renesas/koelsch/qos.h b/board/renesas/koelsch/qos.h
new file mode 100644
index 0000000000..9a6c0461be
--- /dev/null
+++ b/board/renesas/koelsch/qos.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __QOS_H__
+#define __QOS_H__
+
+void qos_init(void);
+
+#endif
diff --git a/board/renesas/lager/Makefile b/board/renesas/lager/Makefile
new file mode 100644
index 0000000000..034c6f8c07
--- /dev/null
+++ b/board/renesas/lager/Makefile
@@ -0,0 +1,9 @@
+#
+# board/renesas/lager/Makefile
+#
+# Copyright (C) 2013 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y	:= lager.o qos.o
diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c
new file mode 100644
index 0000000000..5c99fc9b58
--- /dev/null
+++ b/board/renesas/lager/lager.c
@@ -0,0 +1,287 @@
+/*
+ * board/renesas/lager/lager.c
+ *     This file is lager board support.
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include "qos.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define s_init_wait(cnt) \
+	({	\
+		u32 i = 0x10000 * cnt;	\
+		while (i > 0)	\
+			i--;	\
+	})
+
+#define dbpdrgd_check(bsc) \
+	({	\
+		while ((readl(&bsc->dbpdrgd) & 0x1) != 0x1)	\
+			;	\
+	})
+
+#if defined(CONFIG_NORFLASH)
+static void bsc_init(void)
+{
+	struct r8a7790_lbsc *lbsc = (struct r8a7790_lbsc *)LBSC_BASE;
+	struct r8a7790_dbsc3 *dbsc3_0 = (struct r8a7790_dbsc3 *)DBSC3_0_BASE;
+
+	/* LBSC */
+	writel(0x00000020, &lbsc->cs0ctrl);
+	writel(0x00000020, &lbsc->cs1ctrl);
+	writel(0x00002020, &lbsc->ecs0ctrl);
+	writel(0x00002020, &lbsc->ecs1ctrl);
+
+	writel(0x077F077F, &lbsc->cswcr0);
+	writel(0x077F077F, &lbsc->cswcr1);
+	writel(0x077F077F, &lbsc->ecswcr0);
+	writel(0x077F077F, &lbsc->ecswcr1);
+
+	/* DBSC3 */
+	s_init_wait(10);
+
+	writel(0x0000A55A, &dbsc3_0->dbpdlck);
+	writel(0x00000001, &dbsc3_0->dbpdrga);
+	writel(0x80000000, &dbsc3_0->dbpdrgd);
+	writel(0x00000004, &dbsc3_0->dbpdrga);
+	dbpdrgd_check(dbsc3_0);
+
+	writel(0x00000006, &dbsc3_0->dbpdrga);
+	writel(0x0001C000, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000023, &dbsc3_0->dbpdrga);
+	writel(0x00FD2480, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000010, &dbsc3_0->dbpdrga);
+	writel(0xF004649B, &dbsc3_0->dbpdrgd);
+
+	writel(0x0000000F, &dbsc3_0->dbpdrga);
+	writel(0x00181EE4, &dbsc3_0->dbpdrgd);
+
+	writel(0x0000000E, &dbsc3_0->dbpdrga);
+	writel(0x33C03812, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000003, &dbsc3_0->dbpdrga);
+	writel(0x0300C481, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000007, &dbsc3_0->dbkind);
+	writel(0x10030A02, &dbsc3_0->dbconf0);
+	writel(0x00000001, &dbsc3_0->dbphytype);
+	writel(0x00000000, &dbsc3_0->dbbl);
+	writel(0x0000000B, &dbsc3_0->dbtr0);
+	writel(0x00000008, &dbsc3_0->dbtr1);
+	writel(0x00000000, &dbsc3_0->dbtr2);
+	writel(0x0000000B, &dbsc3_0->dbtr3);
+	writel(0x000C000B, &dbsc3_0->dbtr4);
+	writel(0x00000027, &dbsc3_0->dbtr5);
+	writel(0x0000001C, &dbsc3_0->dbtr6);
+	writel(0x00000005, &dbsc3_0->dbtr7);
+	writel(0x00000018, &dbsc3_0->dbtr8);
+	writel(0x00000008, &dbsc3_0->dbtr9);
+	writel(0x0000000C, &dbsc3_0->dbtr10);
+	writel(0x00000009, &dbsc3_0->dbtr11);
+	writel(0x00000012, &dbsc3_0->dbtr12);
+	writel(0x000000D0, &dbsc3_0->dbtr13);
+	writel(0x00140005, &dbsc3_0->dbtr14);
+	writel(0x00050004, &dbsc3_0->dbtr15);
+	writel(0x70233005, &dbsc3_0->dbtr16);
+	writel(0x000C0000, &dbsc3_0->dbtr17);
+	writel(0x00000300, &dbsc3_0->dbtr18);
+	writel(0x00000040, &dbsc3_0->dbtr19);
+	writel(0x00000001, &dbsc3_0->dbrnk0);
+	writel(0x00020001, &dbsc3_0->dbadj0);
+	writel(0x20082008, &dbsc3_0->dbadj2);
+	writel(0x00020002, &dbsc3_0->dbwt0cnf0);
+	writel(0x0000000F, &dbsc3_0->dbwt0cnf4);
+
+	writel(0x00000015, &dbsc3_0->dbpdrga);
+	writel(0x00000D70, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000016, &dbsc3_0->dbpdrga);
+	writel(0x00000006, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000017, &dbsc3_0->dbpdrga);
+	writel(0x00000018, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000012, &dbsc3_0->dbpdrga);
+	writel(0x9D5CBB66, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000013, &dbsc3_0->dbpdrga);
+	writel(0x1A868300, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000023, &dbsc3_0->dbpdrga);
+	writel(0x00FDB6C0, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000014, &dbsc3_0->dbpdrga);
+	writel(0x300214D8, &dbsc3_0->dbpdrgd);
+
+	writel(0x0000001A, &dbsc3_0->dbpdrga);
+	writel(0x930035C7, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000060, &dbsc3_0->dbpdrga);
+	writel(0x330657B2, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000011, &dbsc3_0->dbpdrga);
+	writel(0x1000040B, &dbsc3_0->dbpdrgd);
+
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x00000001, &dbsc3_0->dbpdrga);
+	writel(0x00000071, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000004, &dbsc3_0->dbpdrga);
+	dbpdrgd_check(dbsc3_0);
+
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x2100FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+
+	writel(0x110000DB, &dbsc3_0->dbcmd);
+
+	writel(0x00000001, &dbsc3_0->dbpdrga);
+	writel(0x00000181, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000004, &dbsc3_0->dbpdrga);
+	dbpdrgd_check(dbsc3_0);
+
+	writel(0x00000001, &dbsc3_0->dbpdrga);
+	writel(0x0000FE01, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000004, &dbsc3_0->dbpdrga);
+	dbpdrgd_check(dbsc3_0);
+
+	writel(0x00000000, &dbsc3_0->dbbs0cnt1);
+	writel(0x01004C20, &dbsc3_0->dbcalcnf);
+	writel(0x014000AA, &dbsc3_0->dbcaltr);
+	writel(0x00000140, &dbsc3_0->dbrfcnf0);
+	writel(0x00081860, &dbsc3_0->dbrfcnf1);
+	writel(0x00010000, &dbsc3_0->dbrfcnf2);
+	writel(0x00000001, &dbsc3_0->dbrfen);
+	writel(0x00000001, &dbsc3_0->dbacen);
+}
+#else
+#define bsc_init() do {} while (0)
+#endif /* CONFIG_NORFLASH */
+
+void s_init(void)
+{
+	struct r8a7790_rwdt *rwdt = (struct r8a7790_rwdt *)RWDT_BASE;
+	struct r8a7790_swdt *swdt = (struct r8a7790_swdt *)SWDT_BASE;
+
+	/* Watchdog init */
+	writel(0xA5A5A500, &rwdt->rwtcsra);
+	writel(0xA5A5A500, &swdt->swtcsra);
+
+	/* QoS(Quality-of-Service) Init */
+	qos_init();
+
+	/* BSC init */
+	bsc_init();
+}
+
+#define MSTPSR1	0xE6150038
+#define SMSTPCR1	0xE6150134
+#define TMU0_MSTP125	(1 << 25)
+
+#define MSTPSR7	0xE61501C4
+#define SMSTPCR7	0xE615014C
+#define SCIF0_MSTP721	(1 << 21)
+
+#define PMMR	0xE6060000
+#define GPSR4	0xE6060014
+#define IPSR14	0xE6060058
+
+#define	set_guard_reg(addr, mask, value)	\
+{ \
+	u32	val; \
+	val = (readl(addr) & ~(mask)) | (value);	\
+	writel(~val, PMMR);	\
+	writel(val, addr);	\
+}
+
+#define mstp_setbits(type, addr, saddr, set) \
+	out_##type((saddr), in_##type(addr) | (set))
+#define mstp_clrbits(type, addr, saddr, clear) \
+	out_##type((saddr), in_##type(addr) & ~(clear))
+#define mstp_setbits_le32(addr, saddr, set)	\
+		mstp_setbits(le32, addr, saddr, set)
+#define mstp_clrbits_le32(addr, saddr, clear)	\
+		mstp_clrbits(le32, addr, saddr, clear)
+
+int board_early_init_f(void)
+{
+	/* TMU0 */
+	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+
+#if defined(CONFIG_NORFLASH)
+	/* SCIF0 */
+	set_guard_reg(GPSR4, 0x34000000, 0x00000000);
+	set_guard_reg(IPSR14, 0x00000FC7, 0x00000481);
+	set_guard_reg(GPSR4,  0x00000000, 0x34000000);
+#endif
+
+	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
+
+	return 0;
+}
+
+DECLARE_GLOBAL_DATA_PTR;
+int board_init(void)
+{
+	/* board id for linux */
+	gd->bd->bi_arch_number = MACH_TYPE_LAGER;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LAGER_SDRAM_BASE + 0x100;
+
+	/* Init PFC controller */
+	r8a7790_pinmux_init();
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+const struct rmobile_sysinfo sysinfo = {
+	CONFIG_RMOBILE_BOARD_STRING
+};
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = LAGER_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = LAGER_SDRAM_SIZE;
+}
+
+int board_late_init(void)
+{
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+}
diff --git a/board/renesas/lager/qos.c b/board/renesas/lager/qos.c
new file mode 100644
index 0000000000..b88511a326
--- /dev/null
+++ b/board/renesas/lager/qos.c
@@ -0,0 +1,1119 @@
+/*
+ * board/renesas/lager/qos.c
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/arch/rmobile.h>
+
+/* QoS version 0.954 */
+
+enum {
+	DBSC3_R00, DBSC3_R01, DBSC3_R02, DBSC3_R03, DBSC3_R04,
+	DBSC3_R05, DBSC3_R06, DBSC3_R07, DBSC3_R08, DBSC3_R09,
+	DBSC3_R10, DBSC3_R11, DBSC3_R12, DBSC3_R13, DBSC3_R14,
+	DBSC3_R15,
+	DBSC3_W00, DBSC3_W01, DBSC3_W02, DBSC3_W03, DBSC3_W04,
+	DBSC3_W05, DBSC3_W06, DBSC3_W07, DBSC3_W08, DBSC3_W09,
+	DBSC3_W10, DBSC3_W11, DBSC3_W12, DBSC3_W13, DBSC3_W14,
+	DBSC3_W15,
+	DBSC3_NR,
+};
+
+static const u32 dbsc3_qos_addr[DBSC3_NR] = {
+	[DBSC3_R00] = DBSC3_0_QOS_R0_BASE,
+	[DBSC3_R01] = DBSC3_0_QOS_R1_BASE,
+	[DBSC3_R02] = DBSC3_0_QOS_R2_BASE,
+	[DBSC3_R03] = DBSC3_0_QOS_R3_BASE,
+	[DBSC3_R04] = DBSC3_0_QOS_R4_BASE,
+	[DBSC3_R05] = DBSC3_0_QOS_R5_BASE,
+	[DBSC3_R06] = DBSC3_0_QOS_R6_BASE,
+	[DBSC3_R07] = DBSC3_0_QOS_R7_BASE,
+	[DBSC3_R08] = DBSC3_0_QOS_R8_BASE,
+	[DBSC3_R09] = DBSC3_0_QOS_R9_BASE,
+	[DBSC3_R10] = DBSC3_0_QOS_R10_BASE,
+	[DBSC3_R11] = DBSC3_0_QOS_R11_BASE,
+	[DBSC3_R12] = DBSC3_0_QOS_R12_BASE,
+	[DBSC3_R13] = DBSC3_0_QOS_R13_BASE,
+	[DBSC3_R14] = DBSC3_0_QOS_R14_BASE,
+	[DBSC3_R15] = DBSC3_0_QOS_R15_BASE,
+	[DBSC3_W00] = DBSC3_0_QOS_W0_BASE,
+	[DBSC3_W01] = DBSC3_0_QOS_W1_BASE,
+	[DBSC3_W02] = DBSC3_0_QOS_W2_BASE,
+	[DBSC3_W03] = DBSC3_0_QOS_W3_BASE,
+	[DBSC3_W04] = DBSC3_0_QOS_W4_BASE,
+	[DBSC3_W05] = DBSC3_0_QOS_W5_BASE,
+	[DBSC3_W06] = DBSC3_0_QOS_W6_BASE,
+	[DBSC3_W07] = DBSC3_0_QOS_W7_BASE,
+	[DBSC3_W08] = DBSC3_0_QOS_W8_BASE,
+	[DBSC3_W09] = DBSC3_0_QOS_W9_BASE,
+	[DBSC3_W10] = DBSC3_0_QOS_W10_BASE,
+	[DBSC3_W11] = DBSC3_0_QOS_W11_BASE,
+	[DBSC3_W12] = DBSC3_0_QOS_W12_BASE,
+	[DBSC3_W13] = DBSC3_0_QOS_W13_BASE,
+	[DBSC3_W14] = DBSC3_0_QOS_W14_BASE,
+	[DBSC3_W15] = DBSC3_0_QOS_W15_BASE,
+};
+
+void qos_init(void)
+{
+	int i;
+	struct r8a7790_s3c *s3c;
+	struct r8a7790_s3c_qos *s3c_qos;
+	struct r8a7790_dbsc3_qos *qos_addr;
+	struct r8a7790_mxi *mxi;
+	struct r8a7790_mxi_qos *mxi_qos;
+	struct r8a7790_axi_qos *axi_qos;
+
+	/* DBSC DBADJ2 */
+	writel(0x20042004, DBSC3_0_DBADJ2);
+
+	/* S3C -QoS */
+	s3c = (struct r8a7790_s3c *)S3C_BASE;
+	writel(0x80FF1C1E, &s3c->s3cadsplcr);
+	writel(0x1F060505, &s3c->s3crorr);
+	writel(0x1F020100, &s3c->s3cworr);
+
+	/* QoS Control Registers */
+	s3c_qos = (struct r8a7790_s3c_qos *)S3C_QOS_CCI0_BASE;
+	writel(0x00800080, &s3c_qos->s3cqos0);
+	writel(0x22000010, &s3c_qos->s3cqos1);
+	writel(0x22002200, &s3c_qos->s3cqos2);
+	writel(0x2F002200, &s3c_qos->s3cqos3);
+	writel(0x2F002F00, &s3c_qos->s3cqos4);
+	writel(0x22000010, &s3c_qos->s3cqos5);
+	writel(0x22002200, &s3c_qos->s3cqos6);
+	writel(0x2F002200, &s3c_qos->s3cqos7);
+	writel(0x2F002F00, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct r8a7790_s3c_qos *)S3C_QOS_CCI1_BASE;
+	writel(0x00800080, &s3c_qos->s3cqos0);
+	writel(0x22000010, &s3c_qos->s3cqos1);
+	writel(0x22002200, &s3c_qos->s3cqos2);
+	writel(0x2F002200, &s3c_qos->s3cqos3);
+	writel(0x2F002F00, &s3c_qos->s3cqos4);
+	writel(0x22000010, &s3c_qos->s3cqos5);
+	writel(0x22002200, &s3c_qos->s3cqos6);
+	writel(0x2F002200, &s3c_qos->s3cqos7);
+	writel(0x2F002F00, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct r8a7790_s3c_qos *)S3C_QOS_MXI_BASE;
+	writel(0x80918099, &s3c_qos->s3cqos0);
+	writel(0x20410010, &s3c_qos->s3cqos1);
+	writel(0x200A2023, &s3c_qos->s3cqos2);
+	writel(0x20502001, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20410FFF, &s3c_qos->s3cqos5);
+	writel(0x200A2023, &s3c_qos->s3cqos6);
+	writel(0x20502001, &s3c_qos->s3cqos7);
+	writel(0x20142032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct r8a7790_s3c_qos *)S3C_QOS_AXI_BASE;
+
+	writel(0x00810089, &s3c_qos->s3cqos0);
+	writel(0x20410001, &s3c_qos->s3cqos1);
+	writel(0x200A2023, &s3c_qos->s3cqos2);
+	writel(0x20502001, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20410FFF, &s3c_qos->s3cqos5);
+	writel(0x200A2023, &s3c_qos->s3cqos6);
+	writel(0x20502001, &s3c_qos->s3cqos7);
+	writel(0x20142032, &s3c_qos->s3cqos8);
+
+	writel(0x00200808, &s3c->s3carcr11);
+
+	/* DBSC -QoS */
+	/* DBSC0 - Read/Write */
+	for (i = DBSC3_R00; i < DBSC3_NR; i++) {
+		qos_addr = (struct r8a7790_dbsc3_qos *)dbsc3_qos_addr[i];
+		writel(0x00000203, &qos_addr->dblgcnt);
+		writel(0x00002064, &qos_addr->dbtmval0);
+		writel(0x00002048, &qos_addr->dbtmval1);
+		writel(0x00002032, &qos_addr->dbtmval2);
+		writel(0x00002019, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002019, &qos_addr->dbthres0);
+		writel(0x00002019, &qos_addr->dbthres1);
+		writel(0x00002019, &qos_addr->dbthres2);
+		writel(0x00000000, &qos_addr->dblgqon);
+	}
+	/* CCI-400 -QoS */
+	writel(0x20001000, CCI_400_MAXOT_1);
+	writel(0x20001000, CCI_400_MAXOT_2);
+	writel(0x0000000C, CCI_400_QOSCNTL_1);
+	writel(0x0000000C, CCI_400_QOSCNTL_2);
+
+	/* MXI -QoS */
+	/* Transaction Control (MXI) */
+	mxi = (struct r8a7790_mxi *)MXI_BASE;
+	writel(0x00000013, &mxi->mxrtcr);
+	writel(0x00000013, &mxi->mxwtcr);
+	writel(0x00B800C0, &mxi->mxsaar0);
+	writel(0x02000800, &mxi->mxsaar1);
+	writel(0x00200000, &mxi->mxs3cracr);
+	writel(0x00200000, &mxi->mxs3cwacr);
+	writel(0x00200000, &mxi->mxaxiracr);
+	writel(0x00200000, &mxi->mxaxiwacr);
+
+	/* QoS Control (MXI) */
+	mxi_qos = (struct r8a7790_mxi_qos *)MXI_QOS_BASE;
+	writel(0x0000000C, &mxi_qos->vspdu0);
+	writel(0x0000000C, &mxi_qos->vspdu1);
+	writel(0x0000000D, &mxi_qos->du0);
+	writel(0x0000000D, &mxi_qos->du1);
+
+	/* AXI -QoS */
+	/* Transaction Control (MXI) */
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_AVB_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200A, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_G2D_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200A, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMP0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002002, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMP1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMUX0_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMUX1_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMUX2_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_LBS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUDS_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUM_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MTSB0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002002, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MTSB1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002002, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_PCI_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_RTX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_SDS0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200A, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_SDS1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200A, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_USB20_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002005, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_USB21_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002005, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_USB22_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002005, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_USB30_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (RT-AXI) */
+	axi_qos = (struct r8a7790_axi_qos *)RT_AXI_SHX_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002005, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)RT_AXI_RDS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)RT_AXI_RTX64TO128_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)RT_AXI_STPRO_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002003, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (MP-AXI) */
+	axi_qos = (struct r8a7790_axi_qos *)MP_AXI_ADSP_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MP_AXI_ASDS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MP_AXI_ASDS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MP_AXI_MLP_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002002, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MP_AXI_MMUMP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MP_AXI_SPU_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MP_AXI_SPUC_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200D, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (SYS-AXI256) */
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI256_SYX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI256_MPX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI256_MXI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (CCI-AXI) */
+	axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_SYX2_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUDS_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUM_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MXI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUMP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (Media-AXI) */
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_JPR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_JPW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_GCU0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_GCU0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_GCU1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_GCU1W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_TDMR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_TDMW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_IMSR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_IMSW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP1W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP1W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_IMRR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_IMRW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP2R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP2W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_DU0R_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_DU0W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_DU1R_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_DU1W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VPC0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP1CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP1CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP1VR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP1VW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VPC1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000000, &axi_qos->qosqon);
+}
diff --git a/board/renesas/lager/qos.h b/board/renesas/lager/qos.h
new file mode 100644
index 0000000000..9a6c0461be
--- /dev/null
+++ b/board/renesas/lager/qos.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __QOS_H__
+#define __QOS_H__
+
+void qos_init(void);
+
+#endif