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-rw-r--r--board/freescale/ls1012afrdm/Kconfig36
-rw-r--r--board/freescale/ls1012afrdm/MAINTAINERS7
-rw-r--r--board/freescale/ls1012afrdm/ls1012afrdm.c68
3 files changed, 103 insertions, 8 deletions
diff --git a/board/freescale/ls1012afrdm/Kconfig b/board/freescale/ls1012afrdm/Kconfig
index fd33807ae3..5255bce0d2 100644
--- a/board/freescale/ls1012afrdm/Kconfig
+++ b/board/freescale/ls1012afrdm/Kconfig
@@ -12,9 +12,14 @@ config SYS_SOC
config SYS_CONFIG_NAME
default "ls1012afrdm"
+config SYS_LS_PFE_FW_ADDR
+ hex "Flash address of PFE firmware"
+ default 0x40a00000
+
config SYS_LS_PPA_FW_ADDR
hex "PPA Firmware Addr"
default 0x40400000
+endif
if FSL_PFE
@@ -22,10 +27,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select PHYLIB
imply PHY_REALTEK
-
-config SYS_LS_PFE_FW_ADDR
- hex "Flash address of PFE firmware"
- default 0x40a00000
+ imply PHY_ATHEROS
config DDR_PFE_PHYS_BASEADDR
hex "PFE DDR physical base address"
@@ -45,6 +47,30 @@ config PFE_EMAC2_PHY_ADDR
endif
-source "board/freescale/common/Kconfig"
+if TARGET_LS1012AFRWY
+
+config SYS_BOARD
+ default "ls1012afrdm"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "fsl-layerscape"
+config SYS_CONFIG_NAME
+ default "ls1012afrwy"
+
+config SYS_LS_PFE_FW_ADDR
+ hex "Flash address of PFE firmware"
+ default 0x40020000
+
+config SYS_LS_PPA_FW_ADDR
+ hex "PPA Firmware Addr"
+ default 0x40060000
+
+endif
+
+if TARGET_LS1012AFRDM || TARGET_LS1012AFRWY
+source "board/freescale/common/Kconfig"
endif
diff --git a/board/freescale/ls1012afrdm/MAINTAINERS b/board/freescale/ls1012afrdm/MAINTAINERS
index 842f86f861..36e3e5ac73 100644
--- a/board/freescale/ls1012afrdm/MAINTAINERS
+++ b/board/freescale/ls1012afrdm/MAINTAINERS
@@ -4,3 +4,10 @@ S: Maintained
F: board/freescale/ls1012afrdm/
F: include/configs/ls1012afrdm.h
F: configs/ls1012afrdm_qspi_defconfig
+
+LS1012AFRWY BOARD
+M: Bhaskar Upadhaya <bhaskar.upadhaya@nxp.com>
+S: Maintained
+F: board/freescale/ls1012afrwy/
+F: include/configs/ls1012afrwy.h
+F: configs/ls1012afrwy_qspi_defconfig
diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
index f8908e0571..e30ad6edcf 100644
--- a/board/freescale/ls1012afrdm/ls1012afrdm.c
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
*/
#include <common.h>
@@ -13,6 +13,7 @@
#endif
#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
+#include <fsl_esdhc.h>
#include <hwconfig.h>
#include <environment.h>
#include <fsl_mmdc.h>
@@ -20,16 +21,66 @@
DECLARE_GLOBAL_DATA_PTR;
+static inline int get_board_version(void)
+{
+ struct ccsr_gpio *pgpio = (void *)(GPIO1_BASE_ADDR);
+ int val;
+
+ val = in_be32(&pgpio->gpdat);
+
+ return val;
+}
+
int checkboard(void)
{
+#ifdef CONFIG_TARGET_LS1012AFRDM
puts("Board: LS1012AFRDM ");
+#else
+ int rev;
+
+ rev = get_board_version();
+
+ puts("Board: FRWY-LS1012A ");
+
+ puts("Version");
+
+ switch (rev) {
+ case BOARD_REV_A:
+ puts(": RevA ");
+ break;
+ case BOARD_REV_B:
+ puts(": RevB ");
+ break;
+ default:
+ puts(": unknown");
+ break;
+ }
+#endif
+
+ return 0;
+}
+#ifdef CONFIG_TARGET_LS1012AFRWY
+int esdhc_status_fixup(void *blob, const char *compat)
+{
+ char esdhc0_path[] = "/soc/esdhc@1560000";
+ char esdhc1_path[] = "/soc/esdhc@1580000";
+
+ do_fixup_by_path(blob, esdhc0_path, "status", "okay",
+ sizeof("okay"), 1);
+
+ do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
+ sizeof("disabled"), 1);
return 0;
}
+#endif
int dram_init(void)
{
- static const struct fsl_mmdc_info mparam = {
+#ifdef CONFIG_TARGET_LS1012AFRWY
+ int board_rev;
+#endif
+ struct fsl_mmdc_info mparam = {
0x04180000, /* mdctl */
0x00030035, /* mdpdc */
0x12554000, /* mdotc */
@@ -45,9 +96,20 @@ int dram_init(void)
0xa1390003, /* mpzqhwctrl */
};
- mmdc_init(&mparam);
+#ifdef CONFIG_TARGET_LS1012AFRWY
+ board_rev = get_board_version();
+ if (board_rev & BOARD_REV_B) {
+ mparam.mdctl = 0x05180000;
+ gd->ram_size = SYS_SDRAM_SIZE_1024;
+ } else {
+ gd->ram_size = SYS_SDRAM_SIZE_512;
+ }
+#else
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+#endif
+ mmdc_init(&mparam);
+
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();