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-rw-r--r--board/freescale/m53017evb/m53017evb.c28
-rw-r--r--board/freescale/m5329evb/m5329evb.c28
-rw-r--r--board/freescale/m5329evb/nand.c14
-rw-r--r--board/freescale/m5373evb/m5373evb.c28
-rw-r--r--board/freescale/m5373evb/nand.c18
5 files changed, 61 insertions, 55 deletions
diff --git a/board/freescale/m53017evb/m53017evb.c b/board/freescale/m53017evb/m53017evb.c
index f331786bf7..142485f0ed 100644
--- a/board/freescale/m53017evb/m53017evb.c
+++ b/board/freescale/m53017evb/m53017evb.c
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -27,6 +27,7 @@
#include <config.h>
#include <common.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -39,7 +40,7 @@ int checkboard(void)
phys_size_t initdram(int board_type)
{
- volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+ sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
@@ -50,34 +51,35 @@ phys_size_t initdram(int board_type)
}
i--;
- sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
#ifdef CONFIG_SYS_SDRAM_BASE1
- sdram->cs1 = (CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i);
#endif
- sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
- sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+ out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
udelay(500);
/* Issue PALL */
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
asm("nop");
/* Perform two refresh cycles */
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
asm("nop");
/* Issue LEMR */
- sdram->mode = CONFIG_SYS_SDRAM_MODE;
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
asm("nop");
- sdram->mode = CONFIG_SYS_SDRAM_EMOD;
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
asm("nop");
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
asm("nop");
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
+ out_be32(&sdram->ctrl,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
asm("nop");
udelay(100);
diff --git a/board/freescale/m5329evb/m5329evb.c b/board/freescale/m5329evb/m5329evb.c
index b4df22f1f2..1c14b83a9d 100644
--- a/board/freescale/m5329evb/m5329evb.c
+++ b/board/freescale/m5329evb/m5329evb.c
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -27,6 +27,7 @@
#include <config.h>
#include <common.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -39,7 +40,7 @@ int checkboard(void)
phys_size_t initdram(int board_type)
{
- volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+ sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
@@ -50,29 +51,30 @@ phys_size_t initdram(int board_type)
}
i--;
- sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
- sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
- sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+ out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
/* Issue PALL */
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Issue LEMR */
- sdram->mode = CONFIG_SYS_SDRAM_EMOD;
- sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
- sdram->mode = CONFIG_SYS_SDRAM_MODE;
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
+ out_be32(&sdram->ctrl,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
udelay(100);
diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c
index 16025f91e2..c70c98c8a1 100644
--- a/board/freescale/m5329evb/nand.c
+++ b/board/freescale/m5329evb/nand.c
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -67,18 +67,18 @@ static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
int board_nand_init(struct nand_chip *nand)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/*
* set up pin configuration - enabled 2nd output buffer's signals
* (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
* to use nCE signal
*/
- gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
- gpio->pddr_timer |= 0x08;
- gpio->ppd_timer |= 0x08;
- gpio->pclrr_timer = 0;
- gpio->podr_timer = 0;
+ clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3);
+ setbits_8(&gpio->pddr_timer, 0x08);
+ setbits_8(&gpio->ppd_timer, 0x08);
+ out_8(&gpio->pclrr_timer, 0);
+ out_8(&gpio->podr_timer, 0);
nand->chip_delay = 60;
nand->ecc.mode = NAND_ECC_SOFT;
diff --git a/board/freescale/m5373evb/m5373evb.c b/board/freescale/m5373evb/m5373evb.c
index 376de4b952..8eb3512dae 100644
--- a/board/freescale/m5373evb/m5373evb.c
+++ b/board/freescale/m5373evb/m5373evb.c
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -27,6 +27,7 @@
#include <config.h>
#include <common.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -39,7 +40,7 @@ int checkboard(void)
phys_size_t initdram(int board_type)
{
- volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+ sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
@@ -50,29 +51,30 @@ phys_size_t initdram(int board_type)
}
i--;
- sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
- sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
- sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+ out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
/* Issue PALL */
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Issue LEMR */
- sdram->mode = CONFIG_SYS_SDRAM_EMOD;
- sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
- sdram->mode = CONFIG_SYS_SDRAM_MODE;
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
+ out_be32(&sdram->ctrl,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
udelay(100);
diff --git a/board/freescale/m5373evb/nand.c b/board/freescale/m5373evb/nand.c
index df8c03b8a2..ed79e395c1 100644
--- a/board/freescale/m5373evb/nand.c
+++ b/board/freescale/m5373evb/nand.c
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -68,21 +68,21 @@ static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
int board_nand_init(struct nand_chip *nand)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
- fbcs->csmr2 &= ~FBCS_CSMR_WP;
+ clrbits_be32(&fbcs->csmr2, FBCS_CSMR_WP);
/*
* set up pin configuration - enabled 2nd output buffer's signals
* (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
* to use nCE signal
*/
- gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
- gpio->pddr_timer |= 0x08;
- gpio->ppd_timer |= 0x08;
- gpio->pclrr_timer = 0;
- gpio->podr_timer = 0;
+ clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3);
+ setbits_8(&gpio->pddr_timer, 0x08);
+ setbits_8(&gpio->ppd_timer, 0x08);
+ out_8(&gpio->pclrr_timer, 0);
+ out_8(&gpio->podr_timer, 0);
nand->chip_delay = 60;
nand->ecc.mode = NAND_ECC_SOFT;
generated by cgit (git 2.34.1) at 2024-12-25 05:44:26 +0000