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-rw-r--r--board/imx31_phycore/Kconfig12
-rw-r--r--board/imx31_phycore/MAINTAINERS11
-rw-r--r--board/imx31_phycore/Makefile9
-rw-r--r--board/imx31_phycore/imx31_phycore.c154
-rw-r--r--board/imx31_phycore/lowlevel_init.S88
5 files changed, 0 insertions, 274 deletions
diff --git a/board/imx31_phycore/Kconfig b/board/imx31_phycore/Kconfig
deleted file mode 100644
index e897ee1c3a..0000000000
--- a/board/imx31_phycore/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_IMX31_PHYCORE || TARGET_IMX31_PHYCORE_EET
-
-config SYS_BOARD
- default "imx31_phycore"
-
-config SYS_SOC
- default "mx31"
-
-config SYS_CONFIG_NAME
- default "imx31_phycore"
-
-endif
diff --git a/board/imx31_phycore/MAINTAINERS b/board/imx31_phycore/MAINTAINERS
deleted file mode 100644
index 41f6cae81b..0000000000
--- a/board/imx31_phycore/MAINTAINERS
+++ /dev/null
@@ -1,11 +0,0 @@
-IMX31_PHYCORE BOARD
-#M: -
-S: Maintained
-F: board/imx31_phycore/
-F: include/configs/imx31_phycore.h
-F: configs/imx31_phycore_defconfig
-
-IMX31_PHYCORE_EET BOARD
-#M: (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
-S: Orphan (since 2013-09)
-F: configs/imx31_phycore_eet_defconfig
diff --git a/board/imx31_phycore/Makefile b/board/imx31_phycore/Makefile
deleted file mode 100644
index e781c13936..0000000000
--- a/board/imx31_phycore/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := imx31_phycore.o
-obj-y += lowlevel_init.o
diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c
deleted file mode 100644
index 653246615f..0000000000
--- a/board/imx31_phycore/imx31_phycore.c
+++ /dev/null
@@ -1,154 +0,0 @@
-/*
- *
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-#include <common.h>
-#include <s6e63d6.h>
-#include <netdev.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/mach-types.h>
-#include <asm/arch/sys_proto.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int dram_init(void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
- PHYS_SDRAM_1_SIZE);
- return 0;
-}
-
-int board_init(void)
-{
-
- gd->bd->bi_arch_number = MACH_TYPE_PCM037; /* board id for linux */
- gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
-
- return 0;
-}
-
-int board_early_init_f(void)
-{
- /* CS0: Nor Flash */
- static const struct mxc_weimcs cs0 = {
- /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
- CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3),
- /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
- CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1),
- /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
- CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0)
- };
-
- /* CS1: Network Controller */
- static const struct mxc_weimcs cs1 = {
- /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
- CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 31, 0, 0, 6),
- /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
- CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1),
- /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
- CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0)
- };
-
- /* CS4: SRAM */
- static const struct mxc_weimcs cs4 = {
- /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
- CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3),
- /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
- CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1),
- /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
- CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0)
- };
-
- mxc_setup_weimcs(0, &cs0);
- mxc_setup_weimcs(1, &cs1);
- mxc_setup_weimcs(4, &cs4);
-
- /* setup pins for UART1 */
- mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
- mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
- mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
- mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
-
- /* setup pins for I2C2 (for EEPROM, RTC) */
- mx31_gpio_mux(MUX_CSPI2_MOSI__I2C2_SCL);
- mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SDA);
-
- return 0;
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
-#ifdef CONFIG_S6E63D6
- struct s6e63d6 data = {
- /*
- * See comment in mxc_spi.c::decode_cs() for .cs field format.
- * We use GPIO 57 as a chipselect for the S6E63D6 and chipselect
- * 2 of the SPI controller #1, since it is unused.
- */
- .cs = 2 | (57 << 8),
- .bus = 0,
- .id = 0,
- };
- int ret;
-
- /* SPI1 */
- mx31_gpio_mux(MUX_CSPI1_SCLK__CSPI1_CLK);
- mx31_gpio_mux(MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B);
- mx31_gpio_mux(MUX_CSPI1_MOSI__CSPI1_MOSI);
- mx31_gpio_mux(MUX_CSPI1_MISO__CSPI1_MISO);
- mx31_gpio_mux(MUX_CSPI1_SS0__CSPI1_SS0_B);
- mx31_gpio_mux(MUX_CSPI1_SS1__CSPI1_SS1_B);
- mx31_gpio_mux(MUX_CSPI1_SS2__CSPI1_SS2_B);
-
- /* start SPI1 clock */
- __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 2);
-
- /* GPIO 57 */
- /* sw_mux_ctl_key_col4_key_col5_key_col6_key_col7 */
- mx31_gpio_mux(IOMUX_MODE(0x63, MUX_CTL_GPIO));
-
- /* SPI1 CS2 is free */
- ret = s6e63d6_init(&data);
- if (ret)
- return ret;
-
- /*
- * This is a "magic" sequence to initialise a C0240QGLA / C0283QGLC
- * OLED display connected to a S6E63D6 SPI display controller in the
- * 18 bit RGB mode
- */
- s6e63d6_index(&data, 2);
- s6e63d6_param(&data, 0x0182);
- s6e63d6_index(&data, 3);
- s6e63d6_param(&data, 0x8130);
- s6e63d6_index(&data, 0x10);
- s6e63d6_param(&data, 0x0000);
- s6e63d6_index(&data, 5);
- s6e63d6_param(&data, 0x0001);
- s6e63d6_index(&data, 0x22);
-#endif
- return 0;
-}
-#endif
-
-int checkboard (void)
-{
- printf("Board: Phytec phyCore i.MX31\n");
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC911X
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#endif
- return rc;
-}
diff --git a/board/imx31_phycore/lowlevel_init.S b/board/imx31_phycore/lowlevel_init.S
deleted file mode 100644
index 6ea3878ef9..0000000000
--- a/board/imx31_phycore/lowlevel_init.S
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- *
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/arch/imx-regs.h>
-
-.macro REG reg, val
- ldr r2, =\reg
- ldr r3, =\val
- str r3, [r2]
-.endm
-
-.macro REG8 reg, val
- ldr r2, =\reg
- ldr r3, =\val
- strb r3, [r2]
-.endm
-
-.macro DELAY loops
- ldr r2, =\loops
-1:
- subs r2, r2, #1
- nop
- bcs 1b
-.endm
-
-.globl lowlevel_init
-lowlevel_init:
-
- REG IPU_CONF, IPU_CONF_DI_EN
- REG CCM_CCMR, 0x074B0BF5
-
- DELAY 0x40000
-
- REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE
- REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
-
- REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)
-
- REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0xe) | PLL_MFI(9) | PLL_MFN(0xd)
-
- REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(0x43) | PLL_MFI(12) | PLL_MFN(1)
-
- REG 0x43FAC26C, 0 /* SDCLK */
- REG 0x43FAC270, 0 /* CAS */
- REG 0x43FAC274, 0 /* RAS */
- REG 0x43FAC27C, 0x1000 /* CS2 (CSD0) */
- REG 0x43FAC284, 0 /* DQM3 */
- REG 0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
- REG 0x43FAC28C, 0
- REG 0x43FAC290, 0
- REG 0x43FAC294, 0
- REG 0x43FAC298, 0
- REG 0x43FAC29C, 0
- REG 0x43FAC2A0, 0
- REG 0x43FAC2A4, 0
- REG 0x43FAC2A8, 0
- REG 0x43FAC2AC, 0
- REG 0x43FAC2B0, 0
- REG 0x43FAC2B4, 0
- REG 0x43FAC2B8, 0
- REG 0x43FAC2BC, 0
- REG 0x43FAC2C0, 0
- REG 0x43FAC2C4, 0
- REG 0x43FAC2C8, 0
- REG 0x43FAC2CC, 0
- REG 0x43FAC2D0, 0
- REG 0x43FAC2D4, 0
- REG 0x43FAC2D8, 0
- REG 0x43FAC2DC, 0
- REG 0xB8001010, 0x00000004
- REG 0xB8001004, 0x006ac73a
- REG 0xB8001000, 0x92100000
- REG 0x80000f00, 0x12344321
- REG 0xB8001000, 0xa2100000
- REG 0x80000000, 0x12344321
- REG 0x80000000, 0x12344321
- REG 0xB8001000, 0xb2100000
- REG8 0x80000033, 0xda
- REG8 0x81000000, 0xff
- REG 0xB8001000, 0x82226080
- REG 0x80000000, 0xDEADBEEF
- REG 0xB8001010, 0x0000000c
-
- mov pc, lr
generated by cgit (git 2.34.1) at 2025-01-27 18:38:28 +0000