diff options
Diffstat (limited to 'board')
55 files changed, 3161 insertions, 1993 deletions
diff --git a/board/CarMediaLab/flea3/flea3.c b/board/CarMediaLab/flea3/flea3.c index f2b4284267..af5338eb5f 100644 --- a/board/CarMediaLab/flea3/flea3.c +++ b/board/CarMediaLab/flea3/flea3.c @@ -29,8 +29,7 @@ #include <asm/errno.h> #include <asm/arch/imx-regs.h> #include <asm/arch/crm_regs.h> -#include <asm/arch/mx35_pins.h> -#include <asm/arch/iomux.h> +#include <asm/arch/iomux-mx35.h> #include <i2c.h> #include <linux/types.h> #include <asm/gpio.h> @@ -165,62 +164,68 @@ static void board_setup_sdram(void) static void setup_iomux_uart3(void) { - mxc_request_iomux(MX35_PIN_RTS2, MUX_CONFIG_ALT7); - mxc_request_iomux(MX35_PIN_CTS2, MUX_CONFIG_ALT7); + static const iomux_v3_cfg_t uart3_pads[] = { + MX35_PAD_RTS2__UART3_RXD_MUX, + MX35_PAD_CTS2__UART3_TXD_MUX, + }; + + imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); } +#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE) + static void setup_iomux_i2c(void) { - int pad; - - mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION); - mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION); - - pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \ - | PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain); + static const iomux_v3_cfg_t i2c_pads[] = { + NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL), + NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL), - mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad); - mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad); + NEW_PAD_CTRL(MX35_PAD_TX3_RX2__I2C3_SCL, I2C_PAD_CTRL), + NEW_PAD_CTRL(MX35_PAD_TX2_RX3__I2C3_SDA, I2C_PAD_CTRL), + }; - mxc_request_iomux(MX35_PIN_TX3_RX2, MUX_CONFIG_ALT1); - mxc_request_iomux(MX35_PIN_TX2_RX3, MUX_CONFIG_ALT1); - - mxc_iomux_set_pad(MX35_PIN_TX3_RX2, pad); - mxc_iomux_set_pad(MX35_PIN_TX2_RX3, pad); + imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads)); } static void setup_iomux_spi(void) { - mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_SION); - mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_SION); - mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_SION); - mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_SION); - mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION); + static const iomux_v3_cfg_t spi_pads[] = { + MX35_PAD_CSPI1_MOSI__CSPI1_MOSI, + MX35_PAD_CSPI1_MISO__CSPI1_MISO, + MX35_PAD_CSPI1_SS0__CSPI1_SS0, + MX35_PAD_CSPI1_SS1__CSPI1_SS1, + MX35_PAD_CSPI1_SCLK__CSPI1_SCLK, + }; + + imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads)); } static void setup_iomux_fec(void) { - /* setup pins for FEC */ - mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC); + static const iomux_v3_cfg_t fec_pads[] = { + MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, + MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, + MX35_PAD_FEC_RX_DV__FEC_RX_DV, + MX35_PAD_FEC_COL__FEC_COL, + MX35_PAD_FEC_RDATA0__FEC_RDATA_0, + MX35_PAD_FEC_TDATA0__FEC_TDATA_0, + MX35_PAD_FEC_TX_EN__FEC_TX_EN, + MX35_PAD_FEC_MDC__FEC_MDC, + MX35_PAD_FEC_MDIO__FEC_MDIO, + MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, + MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, + MX35_PAD_FEC_CRS__FEC_CRS, + MX35_PAD_FEC_RDATA1__FEC_RDATA_1, + MX35_PAD_FEC_TDATA1__FEC_TDATA_1, + MX35_PAD_FEC_RDATA2__FEC_RDATA_2, + MX35_PAD_FEC_TDATA2__FEC_TDATA_2, + MX35_PAD_FEC_RDATA3__FEC_RDATA_3, + MX35_PAD_FEC_TDATA3__FEC_TDATA_3, + }; + /* setup pins for FEC */ + imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); } int board_early_init_f(void) @@ -229,7 +234,7 @@ int board_early_init_f(void) (struct ccm_regs *)IMX_CCM_BASE; /* setup GPIO3_1 to set HighVCore signal */ - mxc_request_iomux(MX35_PIN_ATA_DA1, MUX_CONFIG_ALT5); + imx_iomux_v3_setup_pad(MX35_PAD_ATA_DA1__GPIO3_1); gpio_direction_output(65, 1); /* initialize PLL and clock configuration */ diff --git a/board/a3m071/a3m071.c b/board/a3m071/a3m071.c index 0f9f883e90..c62ba62172 100644 --- a/board/a3m071/a3m071.c +++ b/board/a3m071/a3m071.c @@ -8,7 +8,7 @@ * (C) Copyright 2006 * MicroSys GmbH * - * Copyright 2012 Stefan Roese <sr@denx.de> + * Copyright 2012-2013 Stefan Roese <sr@denx.de> * * See file CREDITS for list of people who contributed to this * project. @@ -241,12 +241,26 @@ void spl_board_init(void) /* And write new value back to register */ out_be32(&mm->ipbi_ws_ctrl, val); -#endif - /* - * No need to change the pin multiplexing (MPC5XXX_GPS_PORT_CONFIG) - * as all 3 config versions (failsave level) have the same setup. - */ + + /* Setup pin multiplexing */ + if (failsavelevel == 2) { + /* fpga-version ok */ +#if defined(CONFIG_SYS_GPS_PORT_CONFIG_2) + out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG_2); +#endif + } else if (failsavelevel == 1) { + /* digiboard-version ok - fpga not */ +#if defined(CONFIG_SYS_GPS_PORT_CONFIG_1) + out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG_1); +#endif + } else { + /* full failsave-mode */ +#if defined(CONFIG_SYS_GPS_PORT_CONFIG) + out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG); +#endif + } +#endif /* * Setup gpio_wkup_7 as watchdog AS INPUT to disable it - see diff --git a/board/boundary/nitrogen6x/clocks.cfg b/board/boundary/nitrogen6x/clocks.cfg index e7d1f86cdb..0a3b47b5d0 100644 --- a/board/boundary/nitrogen6x/clocks.cfg +++ b/board/boundary/nitrogen6x/clocks.cfg @@ -44,3 +44,14 @@ DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ DATA 4, MX6_IOMUXC_GPR6, 0x007F007F DATA 4, MX6_IOMUXC_GPR7, 0x007F007F + +/* + * Setup CCM_CCOSR register as follows: + * + * cko1_en = 1 --> CKO1 enabled + * cko1_div = 111 --> divide by 8 + * cko1_sel = 1011 --> ahb_clk_root + * + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + */ +DATA 4, CCM_CCOSR, 0x000000fb diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index cc071d6d38..e155556ce2 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -47,40 +47,34 @@ DECLARE_GLOBAL_DATA_PTR; -#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) -#define SPI_PAD_CTRL (PAD_CTL_HYS | \ - PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) -#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) -#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_ODE | PAD_CTL_SRE_FAST) -#define WEAK_PULLUP (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ +#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_SRE_SLOW) -#define WEAK_PULLDOWN (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_SRE_SLOW) +#define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_HYS | PAD_CTL_SRE_SLOW) #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) diff --git a/board/denx/m53evk/Makefile b/board/denx/m53evk/Makefile new file mode 100644 index 0000000000..bfb040a075 --- /dev/null +++ b/board/denx/m53evk/Makefile @@ -0,0 +1,40 @@ +# +# DENX M53EVK +# Copyright (C) 2012-2013 Marek Vasut <marex@denx.de> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := m53evk.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/denx/m53evk/imximage.cfg b/board/denx/m53evk/imximage.cfg new file mode 100644 index 0000000000..27c593a5e0 --- /dev/null +++ b/board/denx/m53evk/imximage.cfg @@ -0,0 +1,108 @@ +/* + * DENX M53 DRAM init values + * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ +#include <asm/imx-common/imximage.cfg> + +/* image version */ +IMAGE_VERSION 2 + + +/* Boot Offset 0x400, valid for both SD and NAND boot. */ +BOOT_OFFSET FLASH_OFFSET_STANDARD + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x53fa86f4 0x00000000 /* GRP_DDRMODE_CTL */ +DATA 4 0x53fa8714 0x00000000 /* GRP_DDRMODE */ +DATA 4 0x53fa86fc 0x00000000 /* GRP_DDRPKE */ +DATA 4 0x53fa8724 0x04000000 /* GRP_DDR_TYPE */ + +DATA 4 0x53fa872c 0x00300000 /* GRP_B3DS */ +DATA 4 0x53fa8554 0x00300000 /* DRAM_DQM3 */ +DATA 4 0x53fa8558 0x00300040 /* DRAM_SDQS3 */ + +DATA 4 0x53fa8728 0x00300000 /* GRP_B2DS */ +DATA 4 0x53fa8560 0x00300000 /* DRAM_DQM2 */ +DATA 4 0x53fa8568 0x00300040 /* DRAM_SDQS2 */ + +DATA 4 0x53fa871c 0x00300000 /* GRP_B1DS */ +DATA 4 0x53fa8594 0x00300000 /* DRAM_DQM1 */ +DATA 4 0x53fa8590 0x00300040 /* DRAM_SDQS1 */ + +DATA 4 0x53fa8718 0x00300000 /* GRP_B0DS */ +DATA 4 0x53fa8584 0x00300000 /* DRAM_DQM0 */ +DATA 4 0x53fa857c 0x00300040 /* DRAM_SDQS0 */ + +DATA 4 0x53fa8578 0x00300000 /* DRAM_SDCLK_0 */ +DATA 4 0x53fa8570 0x00300000 /* DRAM_SDCLK_1 */ + +DATA 4 0x53fa8574 0x00300000 /* DRAM_CAS */ +DATA 4 0x53fa8588 0x00300000 /* DRAM_RAS */ +DATA 4 0x53fa86f0 0x00300000 /* GRP_ADDDS */ +DATA 4 0x53fa8720 0x00300000 /* GRP_CTLDS */ + +DATA 4 0x53fa8564 0x00300040 /* DRAM_SDODT1 */ +DATA 4 0x53fa8580 0x00300040 /* DRAM_SDODT0 */ + +/* ESDCTL */ +DATA 4 0x63fd9088 0x32383535 +DATA 4 0x63fd9090 0x40383538 +DATA 4 0x63fd907c 0x0136014d +DATA 4 0x63fd9080 0x01510141 + +DATA 4 0x63fd9018 0x00011740 +DATA 4 0x63fd9000 0xc3190000 +DATA 4 0x63fd900c 0x555952e3 +DATA 4 0x63fd9010 0xb68e8b63 +DATA 4 0x63fd9014 0x01ff00db +DATA 4 0x63fd902c 0x000026d2 +DATA 4 0x63fd9030 0x009f0e21 +DATA 4 0x63fd9008 0x12273030 +DATA 4 0x63fd9004 0x0002002d +DATA 4 0x63fd901c 0x00008032 +DATA 4 0x63fd901c 0x00008033 +DATA 4 0x63fd901c 0x00028031 +DATA 4 0x63fd901c 0x092080b0 +DATA 4 0x63fd901c 0x04008040 +DATA 4 0x63fd901c 0x0000803a +DATA 4 0x63fd901c 0x0000803b +DATA 4 0x63fd901c 0x00028039 +DATA 4 0x63fd901c 0x09208138 +DATA 4 0x63fd901c 0x04008048 +DATA 4 0x63fd9020 0x00001800 +DATA 4 0x63fd9040 0x04b80003 +DATA 4 0x63fd9058 0x00022227 +DATA 4 0x63fd901c 0x00000000 diff --git a/board/denx/m53evk/m53evk.c b/board/denx/m53evk/m53evk.c new file mode 100644 index 0000000000..12917fd311 --- /dev/null +++ b/board/denx/m53evk/m53evk.c @@ -0,0 +1,328 @@ +/* + * DENX M53 module + * + * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/clock.h> +#include <asm/arch/iomux-mx53.h> +#include <asm/arch/spl.h> +#include <asm/errno.h> +#include <netdev.h> +#include <i2c.h> +#include <mmc.h> +#include <spl.h> +#include <fsl_esdhc.h> +#include <asm/gpio.h> +#include <usb/ehci-fsl.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + u32 size1, size2; + + size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); + + gd->ram_size = size1 + size2; + + return 0; +} +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; +} + +static void setup_iomux_uart(void) +{ + static const iomux_v3_cfg_t uart_pads[] = { + MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX, + MX53_PAD_PATA_DMARQ__UART2_TXD_MUX, + }; + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); +} + +#ifdef CONFIG_USB_EHCI_MX5 +int board_ehci_hcd_init(int port) +{ + if (port == 0) { + /* USB OTG PWRON */ + imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4, + PAD_CTL_PKE | PAD_CTL_DSE_HIGH)); + gpio_direction_output(IMX_GPIO_NR(1, 4), 0); + + /* USB OTG Over Current */ + imx_iomux_v3_setup_pad(MX53_PAD_GPIO_18__GPIO7_13); + } else if (port == 1) { + /* USB Host PWRON */ + imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2, + PAD_CTL_PKE | PAD_CTL_DSE_HIGH)); + gpio_direction_output(IMX_GPIO_NR(1, 2), 0); + + /* USB Host Over Current */ + imx_iomux_v3_setup_pad(MX53_PAD_GPIO_3__USBOH3_USBH1_OC); + } + + return 0; +} +#endif + +static void setup_iomux_fec(void) +{ + static const iomux_v3_cfg_t fec_pads[] = { + /* MDIO pads */ + NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS | + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE), + NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH), + + /* FEC 0 pads */ + NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH), + + /* FEC 1 pads */ + NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH), + }; + + imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); +} + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg esdhc_cfg = { + MMC_SDHC1_BASE_ADDR, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1); + gpio_direction_input(IMX_GPIO_NR(1, 1)); + + return !gpio_get_value(IMX_GPIO_NR(1, 1)); +} + +#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP) +#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ + PAD_CTL_DSE_HIGH) + +int board_mmc_init(bd_t *bis) +{ + static const iomux_v3_cfg_t sd1_pads[] = { + NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL), + MX53_PAD_EIM_DA13__GPIO3_13, + + MX53_PAD_EIM_EB3__GPIO2_31, /* SD power */ + }; + + esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + + imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads)); + + /* GPIO 2_31 is SD power */ + gpio_direction_output(IMX_GPIO_NR(2, 31), 0); + + return fsl_esdhc_initialize(bis, &esdhc_cfg); +} +#endif + +#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) + +static void setup_iomux_i2c(void) +{ + static const iomux_v3_cfg_t i2c_pads[] = { + NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL), + }; + + imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads)); +} + +static void setup_iomux_nand(void) +{ + static const iomux_v3_cfg_t nand_pads[] = { + NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B, + PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B, + PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE, + PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE, + PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B, + PAD_CTL_PUS_100K_UP), + NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0, + PAD_CTL_PUS_100K_UP), + NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0, + PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0, + PAD_CTL_DSE_HIGH | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1, + PAD_CTL_DSE_HIGH | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2, + PAD_CTL_DSE_HIGH | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3, + PAD_CTL_DSE_HIGH | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4, + PAD_CTL_DSE_HIGH | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5, + PAD_CTL_DSE_HIGH | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6, + PAD_CTL_DSE_HIGH | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7, + PAD_CTL_DSE_HIGH | PAD_CTL_PKE), + }; + + imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads)); +} + +static void m53_set_clock(void) +{ + int ret; + const uint32_t ref_clk = MXC_HCLK; + const uint32_t dramclk = 400; + uint32_t cpuclk; + + imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0, + PAD_CTL_DSE_HIGH | PAD_CTL_PKE)); + gpio_direction_input(IMX_GPIO_NR(4, 0)); + + /* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */ + cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800; + + ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK); + if (ret) + printf("CPU: Switch CPU clock to %dMHz failed\n", cpuclk); + + ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK); + if (ret) { + printf("CPU: Switch peripheral clock to %dMHz failed\n", + dramclk); + } + + ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK); + if (ret) + printf("CPU: Switch DDR clock to %dMHz failed\n", dramclk); +} + +static void m53_set_nand(void) +{ + u32 i; + + /* NAND flash is muxed on ATA pins */ + setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK); + + /* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */ + for (i = 0x4; i < 0x94; i += 0x18) { + clrbits_le32(WEIM_BASE_ADDR + i, + WEIM_GCR2_MUX16_BYP_GRANT_MASK); + } + + mxc_set_clock(0, 33, MXC_NFC_CLK); + enable_nfc_clk(1); +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + setup_iomux_fec(); + setup_iomux_i2c(); + setup_iomux_nand(); + + m53_set_clock(); + + mxc_set_sata_internal_clock(); + + /* NAND clock @ 33MHz */ + m53_set_nand(); + + return 0; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +int checkboard(void) +{ + puts("Board: DENX M53EVK\n"); + + return 0; +} + +/* + * NAND SPL + */ +#ifdef CONFIG_SPL_BUILD +void spl_board_init(void) +{ + setup_iomux_nand(); + m53_set_clock(); + m53_set_nand(); +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_NAND; +} +#endif diff --git a/board/esg/ima3-mx53/ima3-mx53.c b/board/esg/ima3-mx53/ima3-mx53.c index 41d6bb6a9c..051fa6e4dc 100644 --- a/board/esg/ima3-mx53/ima3-mx53.c +++ b/board/esg/ima3-mx53/ima3-mx53.c @@ -23,11 +23,10 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> -#include <asm/arch/mx5x_pins.h> #include <asm/arch/sys_proto.h> #include <asm/arch/crm_regs.h> #include <asm/arch/clock.h> -#include <asm/arch/iomux.h> +#include <asm/arch/iomux-mx53.h> #include <asm/errno.h> #include <netdev.h> #include <mmc.h> @@ -66,109 +65,53 @@ int dram_init(void) return 0; } +#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) + static void setup_iomux_uart(void) { - /* UART4 RXD */ - mxc_request_iomux(MX53_PIN_CSI0_D13, IOMUX_CONFIG_ALT2); - mxc_iomux_set_pad(MX53_PIN_CSI0_D13, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | - PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE); - mxc_iomux_set_input(MX53_UART4_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3); - - /* UART4 TXD */ - mxc_request_iomux(MX53_PIN_CSI0_D12, IOMUX_CONFIG_ALT2); - mxc_iomux_set_pad(MX53_PIN_CSI0_D12, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | - PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE); + static const iomux_v3_cfg_t uart_pads[] = { + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT13__UART4_RXD_MUX, UART_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT12__UART4_TXD_MUX, UART_PAD_CTRL), + }; + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); } static void setup_iomux_fec(void) { - /*FEC_MDIO*/ - mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_MDIO, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU | - PAD_CTL_ODE_OPENDRAIN_ENABLE); - mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1); - - /*FEC_MDC*/ - mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH); - - /* FEC RXD3 */ - mxc_request_iomux(MX53_PIN_KEY_COL0, IOMUX_CONFIG_ALT6); - mxc_iomux_set_pad(MX53_PIN_KEY_COL0, PAD_CTL_HYS_ENABLE | - PAD_CTL_PKE_ENABLE); - - /* FEC RXD2 */ - mxc_request_iomux(MX53_PIN_KEY_COL2, IOMUX_CONFIG_ALT6); - mxc_iomux_set_pad(MX53_PIN_KEY_COL2, PAD_CTL_HYS_ENABLE | - PAD_CTL_PKE_ENABLE); - - /* FEC RXD1 */ - mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, PAD_CTL_HYS_ENABLE | - PAD_CTL_PKE_ENABLE); - - /* FEC RXD0 */ - mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, PAD_CTL_HYS_ENABLE | - PAD_CTL_PKE_ENABLE); - - /* FEC TXD3 */ - mxc_request_iomux(MX53_PIN_GPIO_19, IOMUX_CONFIG_ALT6); - mxc_iomux_set_pad(MX53_PIN_GPIO_19, PAD_CTL_DRV_HIGH); - - /* FEC TXD2 */ - mxc_request_iomux(MX53_PIN_KEY_ROW2, IOMUX_CONFIG_ALT6); - mxc_iomux_set_pad(MX53_PIN_KEY_ROW2, PAD_CTL_DRV_HIGH); - - /* FEC TXD1 */ - mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH); - - /* FEC TXD0 */ - mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH); - - /* FEC TX_EN */ - mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH); - - /* FEC TX_CLK */ - mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, PAD_CTL_HYS_ENABLE | - PAD_CTL_PKE_ENABLE); - - /* FEC RX_ER */ - mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, PAD_CTL_HYS_ENABLE | - PAD_CTL_PKE_ENABLE); - - /* FEC RX_DV */ - mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, PAD_CTL_HYS_ENABLE | - PAD_CTL_PKE_ENABLE); - - /* FEC CRS */ - mxc_request_iomux(MX53_PIN_KEY_COL3, IOMUX_CONFIG_ALT6); - mxc_iomux_set_pad(MX53_PIN_KEY_COL3, PAD_CTL_HYS_ENABLE | - PAD_CTL_PKE_ENABLE); - - /* FEC COL */ - mxc_request_iomux(MX53_PIN_KEY_ROW1, IOMUX_CONFIG_ALT6); - mxc_iomux_set_pad(MX53_PIN_KEY_ROW1, PAD_CTL_HYS_ENABLE | - PAD_CTL_PKE_ENABLE); - mxc_iomux_set_input(MX53_FEC_FEC_COL_SELECT_INPUT, 0x0); - - /* FEC RX_CLK */ - mxc_request_iomux(MX53_PIN_KEY_COL1, IOMUX_CONFIG_ALT6); - mxc_iomux_set_pad(MX53_PIN_KEY_COL1, PAD_CTL_HYS_ENABLE | - PAD_CTL_PKE_ENABLE); - mxc_iomux_set_input(MX53_FEC_FEC_RX_CLK_SELECT_INPUT, 0x0); + static const iomux_v3_cfg_t fec_pads[] = { + NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS | + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE), + NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK, + PAD_CTL_HYS | PAD_CTL_PKE), + }; + + imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); } #ifdef CONFIG_FSL_ESDHC @@ -178,76 +121,51 @@ int board_mmc_getcd(struct mmc *mmc) { int ret; - ret = !gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_1)); + ret = !gpio_get_value(IMX_GPIO_NR(1, 1)); return ret; } +#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP) +#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ + PAD_CTL_DSE_HIGH) +#define SD_CD_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_HYS | PAD_CTL_PKE) + int board_mmc_init(bd_t *bis) { - mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX53_PIN_GPIO_1, - PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | - PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU | - PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_PKE_ENABLE); - gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_GPIO_1)); - - mxc_iomux_set_pad(MX53_PIN_SD1_CMD, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | - PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX53_PIN_SD1_CLK, - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | - PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH); - mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | - PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); - mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | - PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); - mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | - PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); - mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | - PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + static const iomux_v3_cfg_t sd1_pads[] = { + NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_GPIO_1__GPIO1_1, SD_CD_PAD_CTRL), + }; + + imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads)); + gpio_direction_input(IMX_GPIO_NR(1, 1)); esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); return fsl_esdhc_initialize(bis, &esdhc_cfg); } #endif +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP) + static void setup_iomux_spi(void) { - /* SCLK */ - mxc_request_iomux(MX53_PIN_CSI0_D8, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX53_PIN_CSI0_D8, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | - PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); - mxc_iomux_set_input(MX53_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT, 0x1); - /* MOSI */ - mxc_request_iomux(MX53_PIN_CSI0_D9, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX53_PIN_CSI0_D9, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | - PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); - mxc_iomux_set_input(MX53_ECSPI2_IPP_IND_MOSI_SELECT_INPUT, 0x1); - /* MISO */ - mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX53_PIN_CSI0_D10, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | - PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); - mxc_iomux_set_input(MX53_ECSPI2_IPP_IND_MISO_SELECT_INPUT, 0x1); - /* SSEL 0 */ - mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX53_PIN_CSI0_D11, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | - PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); - gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_D11), 1); + static const iomux_v3_cfg_t spi_pads[] = { + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__ECSPI2_SCLK, SPI_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__ECSPI2_MOSI, SPI_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__ECSPI2_MISO, SPI_PAD_CTRL), + /* SSEL 0 */ + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__GPIO5_29, SPI_PAD_CTRL), + }; + + imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads)); + gpio_direction_output(IMX_GPIO_NR(5, 29), 1); } int board_early_init_f(void) diff --git a/board/freescale/b4860qds/tlb.c b/board/freescale/b4860qds/tlb.c index 373cb7848c..6d634bf690 100644 --- a/board/freescale/b4860qds/tlb.c +++ b/board/freescale/b4860qds/tlb.c @@ -111,8 +111,6 @@ struct fsl_e_tlb_entry tlb_table[] = { #ifdef CONFIG_SYS_NAND_BASE /* * *I*G - NAND - * entry 14 and 15 has been used hard coded, they will be disabled - * in cpu_init_f, so we use entry 16 for nand. */ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -122,6 +120,23 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 12, BOOKE_PAGESZ_4K, 1), + /* + * *I*G - SRIO + * entry 14 and 15 has been used hard coded, they will be disabled + * in cpu_init_f, so we use entry 16 for SRIO2. + */ +#ifdef CONFIG_SYS_SRIO1_MEM_PHYS + /* *I*G* - SRIO1 */ + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 13, BOOKE_PAGESZ_256M, 1), +#endif +#ifdef CONFIG_SYS_SRIO2_MEM_PHYS + /* *I*G* - SRIO2 */ + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO2_MEM_VIRT, CONFIG_SYS_SRIO2_MEM_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 16, BOOKE_PAGESZ_256M, 1), +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 75725b49ad..72bb56cac4 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -33,10 +33,14 @@ COBJS-$(CONFIG_FSL_CADMUS) += cadmus.o COBJS-$(CONFIG_FSL_VIA) += cds_via.o COBJS-$(CONFIG_FMAN_ENET) += fman.o COBJS-$(CONFIG_FSL_PIXIS) += pixis.o +ifndef CONFIG_SPL_BUILD COBJS-$(CONFIG_FSL_NGPIXIS) += ngpixis.o +endif COBJS-$(CONFIG_FSL_QIXIS) += qixis.o COBJS-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o +ifndef CONFIG_SPL_BUILD COBJS-$(CONFIG_ID_EEPROM) += sys_eeprom.o +endif COBJS-$(CONFIG_FSL_SGMII_RISER) += sgmii_riser.o ifndef CONFIG_RAMBOOT_PBL COBJS-$(CONFIG_FSL_FIXED_MMC_LOCATION) += sdhc_boot.o @@ -48,7 +52,9 @@ COBJS-$(CONFIG_MPC8555CDS) += cds_pci_ft.o COBJS-$(CONFIG_MPC8536DS) += ics307_clk.o COBJS-$(CONFIG_MPC8572DS) += ics307_clk.o +ifndef CONFIG_SPL_BUILD COBJS-$(CONFIG_P1022DS) += ics307_clk.o +endif COBJS-$(CONFIG_P2020DS) += ics307_clk.o COBJS-$(CONFIG_P3041DS) += ics307_clk.o COBJS-$(CONFIG_P4080DS) += ics307_clk.o diff --git a/board/freescale/common/cds_pci_ft.c b/board/freescale/common/cds_pci_ft.c index 8a09f99cc4..32233db405 100644 --- a/board/freescale/common/cds_pci_ft.c +++ b/board/freescale/common/cds_pci_ft.c @@ -31,7 +31,8 @@ static void cds_pci_fixup(void *blob) int node; const char *path; int len, slot, i; - u32 *map = NULL; + u32 *map = NULL, *piccells = NULL; + int off, cells; node = fdt_path_offset(blob, "/aliases"); if (node >= 0) { @@ -41,6 +42,25 @@ static void cds_pci_fixup(void *blob) if (node >= 0) { map = fdt_getprop_w(blob, node, "interrupt-map", &len); } + /* Each item in "interrupt-map" property is translated with + * following cells: + * PCI #address-cells, PCI #interrupt-cells, + * PIC address, PIC #address-cells, PIC #interrupt-cells. + */ + cells = fdt_getprop_u32_default(blob, path, "#address-cells", 1); + cells += fdt_getprop_u32_default(blob, path, "#interrupt-cells", 1); + off = fdt_node_offset_by_phandle(blob, fdt32_to_cpu(*(map+cells))); + if (off <= 0) + return; + cells += 1; + piccells = (u32 *)fdt_getprop(blob, off, "#address-cells", NULL); + if (piccells == NULL) + return; + cells += *piccells; + piccells = (u32 *)fdt_getprop(blob, off, "#interrupt-cells", NULL); + if (piccells == NULL) + return; + cells += *piccells; } } @@ -49,12 +69,12 @@ static void cds_pci_fixup(void *blob) slot = get_pci_slot(); - for (i=0;i<len;i+=7) { + for (i=0;i<len;i+=cells) { /* We rotate the interrupt pins so that the mapping * changes depending on the slot the carrier card is in. */ map[3] = ((map[3] + slot - 2) % 4) + 1; - map+=7; + map+=cells; } } } diff --git a/board/freescale/common/sdhc_boot.c b/board/freescale/common/sdhc_boot.c index e4323181fc..fd0e910d7b 100644 --- a/board/freescale/common/sdhc_boot.c +++ b/board/freescale/common/sdhc_boot.c @@ -32,7 +32,7 @@ #define ESDHC_BOOT_IMAGE_SIZE 0x48 #define ESDHC_BOOT_IMAGE_ADDR 0x50 -int mmc_get_env_addr(struct mmc *mmc, u32 *env_addr) +int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr) { u8 *tmp_buf; u32 blklen, code_offset, code_len, n; diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index f4cae5eeb9..996d788ddc 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -172,3 +172,14 @@ DATA 4 0x020e0010 0xF00000CF /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ DATA 4 0x020e0018 0x007F007F DATA 4 0x020e001c 0x007F007F + +/* + * Setup CCM_CCOSR register as follows: + * + * cko1_en = 1 --> CKO1 enabled + * cko1_div = 111 --> divide by 8 + * cko1_sel = 1011 --> ahb_clk_root + * + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + */ +DATA 4 0x020c4060 0x000000fb diff --git a/board/freescale/mx23evk/spl_boot.c b/board/freescale/mx23evk/spl_boot.c index b6f4e7eff2..6be8c8d9d0 100644 --- a/board/freescale/mx23evk/spl_boot.c +++ b/board/freescale/mx23evk/spl_boot.c @@ -25,8 +25,8 @@ #include <asm/arch/imx-regs.h> #include <asm/arch/sys_proto.h> -#define MUX_CONFIG_SSP1 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_16MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_SSP1 (MXS_PAD_8MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP) const iomux_cfg_t iomux_setup[] = { /* DUART */ diff --git a/board/freescale/mx25pdk/mx25pdk.c b/board/freescale/mx25pdk/mx25pdk.c index d73e27e540..5e6047f834 100644 --- a/board/freescale/mx25pdk/mx25pdk.c +++ b/board/freescale/mx25pdk/mx25pdk.c @@ -21,8 +21,7 @@ #include <asm/io.h> #include <asm/gpio.h> #include <asm/arch/imx-regs.h> -#include <asm/arch/imx25-pinmux.h> -#include <asm/arch/sys_proto.h> +#include <asm/arch/iomux-mx25.h> #include <asm/arch/clock.h> #include <mmc.h> #include <fsl_esdhc.h> @@ -31,8 +30,8 @@ #include <fsl_pmic.h> #include <mc34704.h> -#define FEC_RESET_B IMX_GPIO_NR(2, 3) -#define FEC_ENABLE_B IMX_GPIO_NR(4, 8) +#define FEC_RESET_B IMX_GPIO_NR(4, 8) +#define FEC_ENABLE_B IMX_GPIO_NR(2, 3) #define CARD_DETECT IMX_GPIO_NR(2, 1) DECLARE_GLOBAL_DATA_PTR; @@ -43,29 +42,42 @@ struct fsl_esdhc_cfg esdhc_cfg[1] = { }; #endif +/* + * FIXME: need to revisit this + * The original code enabled PUE and 100-k pull-down without PKE, so the right + * value here is likely: + * 0 for no pull + * or: + * PAD_CTL_PUS_100K_DOWN for 100-k pull-down + */ +#define FEC_OUT_PAD_CTRL 0 + +#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \ + PAD_CTL_ODE) + static void mx25pdk_fec_init(void) { - struct iomuxc_mux_ctl *muxctl; - struct iomuxc_pad_ctl *padctl; - u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5); - u32 gpio_mux_mode0_sion = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION; - - /* FEC pin init is generic */ - mx25_fec_init_pins(); - - muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; - padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; - /* - * Set up FEC_RESET_B and FEC_ENABLE_B - * - * FEC_RESET_B: gpio2_3 is ALT 5 mode of pin D12 - * FEC_ENABLE_B: gpio4_8 is ALT 5 mode of pin A17 - */ - writel(gpio_mux_mode, &muxctl->pad_d12); - writel(gpio_mux_mode, &muxctl->pad_a17); - - writel(0x0, &padctl->pad_d12); - writel(0x0, &padctl->pad_a17); + static const iomux_v3_cfg_t fec_pads[] = { + MX25_PAD_FEC_TX_CLK__FEC_TX_CLK, + MX25_PAD_FEC_RX_DV__FEC_RX_DV, + MX25_PAD_FEC_RDATA0__FEC_RDATA0, + NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL), + NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL), + NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL), + MX25_PAD_FEC_MDIO__FEC_MDIO, + MX25_PAD_FEC_RDATA1__FEC_RDATA1, + NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL), + + NEW_PAD_CTRL(MX25_PAD_D12__GPIO_4_8, 0), /* FEC_RESET_B */ + NEW_PAD_CTRL(MX25_PAD_A17__GPIO_2_3, 0), /* FEC_ENABLE_B */ + }; + + static const iomux_v3_cfg_t i2c_pads[] = { + NEW_PAD_CTRL(MX25_PAD_I2C1_CLK__I2C1_CLK, I2C_PAD_CTRL), + NEW_PAD_CTRL(MX25_PAD_I2C1_DAT__I2C1_DAT, I2C_PAD_CTRL), + }; + + imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); /* Assert RESET and ENABLE low */ gpio_direction_output(FEC_RESET_B, 0); @@ -78,10 +90,7 @@ static void mx25pdk_fec_init(void) gpio_set_value(FEC_ENABLE_B, 1); /* Setup I2C pins so that PMIC can turn on PHY supply */ - writel(gpio_mux_mode0_sion, &muxctl->pad_i2c1_clk); - writel(gpio_mux_mode0_sion, &muxctl->pad_i2c1_dat); - writel(0x1E8, &padctl->pad_i2c1_clk); - writel(0x1E8, &padctl->pad_i2c1_dat); + imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads)); } int dram_init(void) @@ -92,9 +101,35 @@ int dram_init(void) return 0; } +/* + * Set up input pins with hysteresis and 100-k pull-ups + */ +#define UART1_IN_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP) +/* + * FIXME: need to revisit this + * The original code enabled PUE and 100-k pull-down without PKE, so the right + * value here is likely: + * 0 for no pull + * or: + * PAD_CTL_PUS_100K_DOWN for 100-k pull-down + */ +#define UART1_OUT_PAD_CTRL 0 + +static void mx25pdk_uart1_init(void) +{ + static const iomux_v3_cfg_t uart1_pads[] = { + NEW_PAD_CTRL(MX25_PAD_UART1_RXD__UART1_RXD, UART1_IN_PAD_CTRL), + NEW_PAD_CTRL(MX25_PAD_UART1_TXD__UART1_TXD, UART1_OUT_PAD_CTRL), + NEW_PAD_CTRL(MX25_PAD_UART1_RTS__UART1_RTS, UART1_OUT_PAD_CTRL), + NEW_PAD_CTRL(MX25_PAD_UART1_CTS__UART1_CTS, UART1_IN_PAD_CTRL), + }; + + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + int board_early_init_f(void) { - mx25_uart1_init_pins(); + mx25pdk_uart1_init(); return 0; } @@ -131,21 +166,8 @@ int board_late_init(void) #ifdef CONFIG_FSL_ESDHC int board_mmc_getcd(struct mmc *mmc) { - struct iomuxc_mux_ctl *muxctl; - struct iomuxc_pad_ctl *padctl; - u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5); - - /* - * Set up the Card Detect pin. - * - * SD1_GPIO_CD: gpio2_1 is ALT 5 mode of pin A15 - * - */ - muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; - padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; - - writel(gpio_mux_mode, &muxctl->pad_a15); - writel(0x0, &padctl->pad_a15); + /* Set up the Card Detect pin. */ + imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX25_PAD_A15__GPIO_2_1, 0)); gpio_direction_input(CARD_DETECT); return !gpio_get_value(CARD_DETECT); @@ -153,16 +175,16 @@ int board_mmc_getcd(struct mmc *mmc) int board_mmc_init(bd_t *bis) { - struct iomuxc_mux_ctl *muxctl; - u32 sdhc1_mux_mode = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION; - - muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; - writel(sdhc1_mux_mode, &muxctl->pad_sd1_cmd); - writel(sdhc1_mux_mode, &muxctl->pad_sd1_clk); - writel(sdhc1_mux_mode, &muxctl->pad_sd1_data0); - writel(sdhc1_mux_mode, &muxctl->pad_sd1_data1); - writel(sdhc1_mux_mode, &muxctl->pad_sd1_data2); - writel(sdhc1_mux_mode, &muxctl->pad_sd1_data3); + static const iomux_v3_cfg_t sdhc1_pads[] = { + NEW_PAD_CTRL(MX25_PAD_SD1_CMD__SD1_CMD, NO_PAD_CTRL), + NEW_PAD_CTRL(MX25_PAD_SD1_CLK__SD1_CLK, NO_PAD_CTRL), + NEW_PAD_CTRL(MX25_PAD_SD1_DATA0__SD1_DATA0, NO_PAD_CTRL), + NEW_PAD_CTRL(MX25_PAD_SD1_DATA1__SD1_DATA1, NO_PAD_CTRL), + NEW_PAD_CTRL(MX25_PAD_SD1_DATA2__SD1_DATA2, NO_PAD_CTRL), + NEW_PAD_CTRL(MX25_PAD_SD1_DATA3__SD1_DATA3, NO_PAD_CTRL), + }; + + imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads)); esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK); return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c index b7f474e5ef..9f667d2dea 100644 --- a/board/freescale/mx35pdk/mx35pdk.c +++ b/board/freescale/mx35pdk/mx35pdk.c @@ -28,8 +28,7 @@ #include <asm/arch/imx-regs.h> #include <asm/arch/crm_regs.h> #include <asm/arch/clock.h> -#include <asm/arch/mx35_pins.h> -#include <asm/arch/iomux.h> +#include <asm/arch/iomux-mx35.h> #include <i2c.h> #include <power/pmic.h> #include <fsl_pmic.h> @@ -73,114 +72,88 @@ void dram_init_banksize(void) gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; } +#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE) + static void setup_iomux_i2c(void) { - int pad; + static const iomux_v3_cfg_t i2c1_pads[] = { + NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL), + NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL), + }; /* setup pins for I2C1 */ - mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION); - mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION); - - pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \ - | PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain); - - mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad); - mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad); + imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads)); } static void setup_iomux_spi(void) { - mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_SION); - mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_SION); - mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_SION); - mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_SION); - mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION); + static const iomux_v3_cfg_t spi_pads[] = { + MX35_PAD_CSPI1_MOSI__CSPI1_MOSI, + MX35_PAD_CSPI1_MISO__CSPI1_MISO, + MX35_PAD_CSPI1_SS0__CSPI1_SS0, + MX35_PAD_CSPI1_SS1__CSPI1_SS1, + MX35_PAD_CSPI1_SCLK__CSPI1_SCLK, + }; + + imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads)); } +#define USBOTG_IN_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | \ + PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW) +#define USBOTG_OUT_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW) + static void setup_iomux_usbotg(void) { - int in_pad, out_pad; + static const iomux_v3_cfg_t usbotg_pads[] = { + NEW_PAD_CTRL(MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR, + USBOTG_OUT_PAD_CTRL), + NEW_PAD_CTRL(MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC, + USBOTG_IN_PAD_CTRL), + }; /* Set up pins for USBOTG. */ - mxc_request_iomux(MX35_PIN_USBOTG_PWR, - MUX_CONFIG_SION | MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_USBOTG_OC, - MUX_CONFIG_SION | MUX_CONFIG_FUNC); - - in_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | - PAD_CTL_PUE_PUD | PAD_CTL_100K_PD | PAD_CTL_ODE_CMOS | - PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW; - out_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_CMOS | PAD_CTL_PKE_NONE | - PAD_CTL_ODE_CMOS | PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW; - - mxc_iomux_set_pad(MX35_PIN_USBOTG_PWR, out_pad); - mxc_iomux_set_pad(MX35_PIN_USBOTG_OC, in_pad); + imx_iomux_v3_setup_multiple_pads(usbotg_pads, ARRAY_SIZE(usbotg_pads)); } +#define FEC_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW) + static void setup_iomux_fec(void) { - int pad; + static const iomux_v3_cfg_t fec_pads[] = { + NEW_PAD_CTRL(MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, FEC_PAD_CTRL | + PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), + NEW_PAD_CTRL(MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, FEC_PAD_CTRL | + PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), + NEW_PAD_CTRL(MX35_PAD_FEC_RX_DV__FEC_RX_DV, FEC_PAD_CTRL | + PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), + NEW_PAD_CTRL(MX35_PAD_FEC_COL__FEC_COL, FEC_PAD_CTRL | + PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), + NEW_PAD_CTRL(MX35_PAD_FEC_RDATA0__FEC_RDATA_0, FEC_PAD_CTRL | + PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), + NEW_PAD_CTRL(MX35_PAD_FEC_TDATA0__FEC_TDATA_0, FEC_PAD_CTRL), + NEW_PAD_CTRL(MX35_PAD_FEC_TX_EN__FEC_TX_EN, FEC_PAD_CTRL), + NEW_PAD_CTRL(MX35_PAD_FEC_MDC__FEC_MDC, FEC_PAD_CTRL), + NEW_PAD_CTRL(MX35_PAD_FEC_MDIO__FEC_MDIO, FEC_PAD_CTRL | + PAD_CTL_HYS | PAD_CTL_PUS_22K_UP), + NEW_PAD_CTRL(MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, FEC_PAD_CTRL), + NEW_PAD_CTRL(MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, FEC_PAD_CTRL | + PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), + NEW_PAD_CTRL(MX35_PAD_FEC_CRS__FEC_CRS, FEC_PAD_CTRL | + PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), + NEW_PAD_CTRL(MX35_PAD_FEC_RDATA1__FEC_RDATA_1, FEC_PAD_CTRL | + PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), + NEW_PAD_CTRL(MX35_PAD_FEC_TDATA1__FEC_TDATA_1, FEC_PAD_CTRL), + NEW_PAD_CTRL(MX35_PAD_FEC_RDATA2__FEC_RDATA_2, FEC_PAD_CTRL | + PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), + NEW_PAD_CTRL(MX35_PAD_FEC_TDATA2__FEC_TDATA_2, FEC_PAD_CTRL), + NEW_PAD_CTRL(MX35_PAD_FEC_RDATA3__FEC_RDATA_3, FEC_PAD_CTRL | + PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), + NEW_PAD_CTRL(MX35_PAD_FEC_TDATA3__FEC_TDATA_3, FEC_PAD_CTRL), + }; /* setup pins for FEC */ - mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC); - - pad = (PAD_CTL_DRV_3_3V | PAD_CTL_PUE_PUD | PAD_CTL_ODE_CMOS | \ - PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW); - - mxc_iomux_set_pad(MX35_PIN_FEC_TX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \ - PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX35_PIN_FEC_RX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \ - PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX35_PIN_FEC_RX_DV, pad | PAD_CTL_HYS_SCHMITZ | \ - PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX35_PIN_FEC_COL, pad | PAD_CTL_HYS_SCHMITZ | \ - PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX35_PIN_FEC_RDATA0, pad | PAD_CTL_HYS_SCHMITZ | \ - PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX35_PIN_FEC_TDATA0, pad | PAD_CTL_HYS_CMOS | \ - PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX35_PIN_FEC_TX_EN, pad | PAD_CTL_HYS_CMOS | \ - PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX35_PIN_FEC_MDC, pad | PAD_CTL_HYS_CMOS | \ - PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX35_PIN_FEC_MDIO, pad | PAD_CTL_HYS_SCHMITZ | \ - PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU); - mxc_iomux_set_pad(MX35_PIN_FEC_TX_ERR, pad | PAD_CTL_HYS_CMOS | \ - PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX35_PIN_FEC_RX_ERR, pad | PAD_CTL_HYS_SCHMITZ | \ - PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX35_PIN_FEC_CRS, pad | PAD_CTL_HYS_SCHMITZ | \ - PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX35_PIN_FEC_RDATA1, pad | PAD_CTL_HYS_SCHMITZ | \ - PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX35_PIN_FEC_TDATA1, pad | PAD_CTL_HYS_CMOS | \ - PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX35_PIN_FEC_RDATA2, pad | PAD_CTL_HYS_SCHMITZ | \ - PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX35_PIN_FEC_TDATA2, pad | PAD_CTL_HYS_CMOS | \ - PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX35_PIN_FEC_RDATA3, pad | PAD_CTL_HYS_SCHMITZ | \ - PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX35_PIN_FEC_TDATA3, pad | PAD_CTL_HYS_CMOS | \ - PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); } int board_early_init_f(void) @@ -262,8 +235,7 @@ int board_late_init(void) if (pmic_detect()) { p = pmic_get("FSL_PMIC"); - mxc_request_iomux(MX35_PIN_WATCHDOG_RST, MUX_CONFIG_SION | - MUX_CONFIG_ALT1); + imx_iomux_v3_setup_pad(MX35_PAD_WDOG_RST__WDOG_WDOG_B); pmic_reg_read(p, REG_SETTING_0, &pmic_val); pmic_reg_write(p, REG_SETTING_0, @@ -271,10 +243,9 @@ int board_late_init(void) pmic_reg_read(p, REG_MODE_0, &pmic_val); pmic_reg_write(p, REG_MODE_0, pmic_val | VGEN3EN); - mxc_request_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO); - mxc_iomux_set_input(MUX_IN_GPIO1_IN_5, INPUT_CTL_PATH0); + imx_iomux_v3_setup_pad(MX35_PAD_COMPARE__GPIO1_5); - gpio_direction_output(IMX_GPIO_NR(2, 5), 1); + gpio_direction_output(IMX_GPIO_NR(1, 5), 1); } val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04; @@ -312,13 +283,17 @@ struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR}; int board_mmc_init(bd_t *bis) { + static const iomux_v3_cfg_t sdhc1_pads[] = { + MX35_PAD_SD1_CMD__ESDHC1_CMD, + MX35_PAD_SD1_CLK__ESDHC1_CLK, + MX35_PAD_SD1_DATA0__ESDHC1_DAT0, + MX35_PAD_SD1_DATA1__ESDHC1_DAT1, + MX35_PAD_SD1_DATA2__ESDHC1_DAT2, + MX35_PAD_SD1_DATA3__ESDHC1_DAT3, + }; + /* configure pins for SDHC1 only */ - mxc_request_iomux(MX35_PIN_SD1_CMD, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_SD1_CLK, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_SD1_DATA0, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_SD1_DATA1, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_SD1_DATA2, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_SD1_DATA3, MUX_CONFIG_FUNC); + imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads)); esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK); return fsl_esdhc_initialize(bis, &esdhc_cfg); diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index 54c16b1f9d..369da6de5b 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -24,8 +24,7 @@ #include <asm/io.h> #include <asm/gpio.h> #include <asm/arch/imx-regs.h> -#include <asm/arch/mx5x_pins.h> -#include <asm/arch/iomux.h> +#include <asm/arch/iomux-mx51.h> #include <asm/errno.h> #include <asm/arch/sys_proto.h> #include <asm/arch/crm_regs.h> @@ -64,160 +63,103 @@ u32 get_board_rev(void) return rev; } +#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH) + static void setup_iomux_uart(void) { - unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | - PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH; - - mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST); - mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST); - mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad); - mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad); + static const iomux_v3_cfg_t uart_pads[] = { + MX51_PAD_UART1_RXD__UART1_RXD, + MX51_PAD_UART1_TXD__UART1_TXD, + NEW_PAD_CTRL(MX51_PAD_UART1_RTS__UART1_RTS, UART_PAD_CTRL), + NEW_PAD_CTRL(MX51_PAD_UART1_CTS__UART1_CTS, UART_PAD_CTRL), + }; + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); } static void setup_iomux_fec(void) { - /*FEC_MDIO*/ - mxc_request_iomux(MX51_PIN_EIM_EB2 , IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_EIM_EB2 , 0x1FD); - - /*FEC_MDC*/ - mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004); - - /* FEC RDATA[3] */ - mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180); - - /* FEC RDATA[2] */ - mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180); - - /* FEC RDATA[1] */ - mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180); - - /* FEC RDATA[0] */ - mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2); - mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180); - - /* FEC TDATA[3] */ - mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004); - - /* FEC TDATA[2] */ - mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004); - - /* FEC TDATA[1] */ - mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004); - - /* FEC TDATA[0] */ - mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2); - mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004); - - /* FEC TX_EN */ - mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004); - - /* FEC TX_ER */ - mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004); - - /* FEC TX_CLK */ - mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180); - - /* FEC TX_COL */ - mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180); - - /* FEC RX_CLK */ - mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180); - - /* FEC RX_CRS */ - mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180); - - /* FEC RX_ER */ - mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180); - - /* FEC RX_DV */ - mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2); - mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180); + static const iomux_v3_cfg_t fec_pads[] = { + NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, PAD_CTL_HYS | + PAD_CTL_PUS_22K_UP | PAD_CTL_ODE | + PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST), + MX51_PAD_NANDF_CS3__FEC_MDC, + NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2), + NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2), + NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2), + MX51_PAD_NANDF_D9__FEC_RDATA0, + MX51_PAD_NANDF_CS6__FEC_TDATA3, + MX51_PAD_NANDF_CS5__FEC_TDATA2, + MX51_PAD_NANDF_CS4__FEC_TDATA1, + MX51_PAD_NANDF_D8__FEC_TDATA0, + MX51_PAD_NANDF_CS7__FEC_TX_EN, + MX51_PAD_NANDF_CS2__FEC_TX_ER, + MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK, + NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4), + NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4), + MX51_PAD_EIM_CS5__FEC_CRS, + MX51_PAD_EIM_CS4__FEC_RX_ER, + NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, MX51_PAD_CTRL_4), + }; + + imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); } #ifdef CONFIG_MXC_SPI static void setup_iomux_spi(void) { - /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */ - mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, 0x105); - - /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */ - mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, 0x105); - - /* de-select SS1 of instance: ecspi1. */ - mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x85); - - /* 000: Select mux mode: ALT0 mux port: SS0 ecspi1 */ - mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x185); - - /* 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. */ - mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x180); - - /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */ - mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, 0x105); + static const iomux_v3_cfg_t spi_pads[] = { + NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS | + PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS | + PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1, + MX51_GPIO_PAD_CTRL), + MX51_PAD_CSPI1_SS0__ECSPI1_SS0, + NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__ECSPI1_RDY, MX51_PAD_CTRL_2), + NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS | + PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST), + }; + + imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads)); } #endif #ifdef CONFIG_USB_EHCI_MX5 -#define MX51EVK_USBH1_HUB_RST IOMUX_TO_GPIO(MX51_PIN_GPIO1_7) /* GPIO1_7 */ -#define MX51EVK_USBH1_STP IOMUX_TO_GPIO(MX51_PIN_USBH1_STP) /* GPIO1_27 */ -#define MX51EVK_USB_CLK_EN_B IOMUX_TO_GPIO(MX51_PIN_EIM_D18) /* GPIO2_1 */ -#define MX51EVK_USB_PHY_RESET IOMUX_TO_GPIO(MX51_PIN_EIM_D21) /* GPIO2_5 */ - -#define USBH1_PAD (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | \ - PAD_CTL_100K_PU | PAD_CTL_PUE_PULL | \ - PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE) -#define GPIO_PAD (PAD_CTL_DRV_HIGH | PAD_CTL_PKE_ENABLE | \ - PAD_CTL_SRE_FAST) -#define NO_PAD (1 << 16) +#define MX51EVK_USBH1_HUB_RST IMX_GPIO_NR(1, 7) +#define MX51EVK_USBH1_STP IMX_GPIO_NR(1, 27) +#define MX51EVK_USB_CLK_EN_B IMX_GPIO_NR(2, 2) +#define MX51EVK_USB_PHY_RESET IMX_GPIO_NR(2, 5) static void setup_usb_h1(void) { - setup_iomux_usb_h1(); - - /* GPIO_1_7 for USBH1 hub reset */ - mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_GPIO1_7, NO_PAD); - - /* GPIO_2_1 */ - mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_EIM_D17, GPIO_PAD); - - /* GPIO_2_5 for USB PHY reset */ - mxc_request_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_EIM_D21, GPIO_PAD); + static const iomux_v3_cfg_t usb_h1_pads[] = { + MX51_PAD_USBH1_CLK__USBH1_CLK, + MX51_PAD_USBH1_DIR__USBH1_DIR, + MX51_PAD_USBH1_STP__USBH1_STP, + MX51_PAD_USBH1_NXT__USBH1_NXT, + MX51_PAD_USBH1_DATA0__USBH1_DATA0, + MX51_PAD_USBH1_DATA1__USBH1_DATA1, + MX51_PAD_USBH1_DATA2__USBH1_DATA2, + MX51_PAD_USBH1_DATA3__USBH1_DATA3, + MX51_PAD_USBH1_DATA4__USBH1_DATA4, + MX51_PAD_USBH1_DATA5__USBH1_DATA5, + MX51_PAD_USBH1_DATA6__USBH1_DATA6, + MX51_PAD_USBH1_DATA7__USBH1_DATA7, + + NEW_PAD_CTRL(MX51_PAD_GPIO1_7__GPIO1_7, 0), /* H1 hub reset */ + MX51_PAD_EIM_D17__GPIO2_1, + MX51_PAD_EIM_D21__GPIO2_5, /* PHY reset */ + }; + + imx_iomux_v3_setup_multiple_pads(usb_h1_pads, ARRAY_SIZE(usb_h1_pads)); } int board_ehci_hcd_init(int port) { /* Set USBH1_STP to GPIO and toggle it */ - mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USBH1_PAD); + imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_USBH1_STP__GPIO1_27, + MX51_USBH_PAD_CTRL)); gpio_direction_output(MX51EVK_USBH1_STP, 0); gpio_direction_output(MX51EVK_USB_PHY_RESET, 0); @@ -225,8 +167,7 @@ int board_ehci_hcd_init(int port) gpio_set_value(MX51EVK_USBH1_STP, 1); /* Set back USBH1_STP to be function */ - mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USBH1_PAD); + imx_iomux_v3_setup_pad(MX51_PAD_USBH1_STP__USBH1_STP); /* De-assert USB PHY RESETB */ gpio_set_value(MX51EVK_USB_PHY_RESET, 1); @@ -328,7 +269,8 @@ static void power_init(void) VVIDEOEN | VAUDIOEN | VSDEN; pmic_reg_write(p, REG_MODE_1, val); - mxc_request_iomux(MX51_PIN_EIM_A20, IOMUX_CONFIG_ALT1); + imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_EIM_A20__GPIO2_14, + NO_PAD_CTRL)); gpio_direction_output(IMX_GPIO_NR(2, 14), 0); udelay(500); @@ -342,9 +284,11 @@ int board_mmc_getcd(struct mmc *mmc) struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; int ret; - mxc_request_iomux(MX51_PIN_GPIO1_0, IOMUX_CONFIG_ALT1); + imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_0__GPIO1_0, + NO_PAD_CTRL)); gpio_direction_input(IMX_GPIO_NR(1, 0)); - mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0); + imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6, + NO_PAD_CTRL)); gpio_direction_input(IMX_GPIO_NR(1, 6)); if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) @@ -357,6 +301,40 @@ int board_mmc_getcd(struct mmc *mmc) int board_mmc_init(bd_t *bis) { + static const iomux_v3_cfg_t sd1_pads[] = { + NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX | + PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX | + PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX | + PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX | + PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX | + PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX | + PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS), + NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS), + }; + + static const iomux_v3_cfg_t sd2_pads[] = { + NEW_PAD_CTRL(MX51_PAD_SD2_CMD__SD2_CMD, + PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_SD2_CLK__SD2_CLK, + PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_SD2_DATA0__SD2_DATA0, + PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_SD2_DATA1__SD2_DATA1, + PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_SD2_DATA2__SD2_DATA2, + PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_SD2_DATA3__SD2_DATA3, + PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6, PAD_CTL_HYS), + NEW_PAD_CTRL(MX51_PAD_GPIO1_5__GPIO1_5, PAD_CTL_HYS), + }; + u32 index; s32 status = 0; @@ -367,98 +345,12 @@ int board_mmc_init(bd_t *bis) index++) { switch (index) { case 0: - mxc_request_iomux(MX51_PIN_SD1_CMD, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_request_iomux(MX51_PIN_SD1_CLK, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_request_iomux(MX51_PIN_SD1_DATA0, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_request_iomux(MX51_PIN_SD1_DATA1, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_request_iomux(MX51_PIN_SD1_DATA2, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_request_iomux(MX51_PIN_SD1_DATA3, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_SD1_CMD, - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | - PAD_CTL_PUE_PULL | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_SD1_CLK, - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | - PAD_CTL_HYS_NONE | PAD_CTL_47K_PU | - PAD_CTL_PUE_PULL | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | - PAD_CTL_PUE_PULL | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | - PAD_CTL_PUE_PULL | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | - PAD_CTL_PUE_PULL | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | - PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD | - PAD_CTL_PUE_PULL | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - mxc_request_iomux(MX51_PIN_GPIO1_0, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_GPIO1_0, - PAD_CTL_HYS_ENABLE); - mxc_request_iomux(MX51_PIN_GPIO1_1, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_GPIO1_1, - PAD_CTL_HYS_ENABLE); + imx_iomux_v3_setup_multiple_pads(sd1_pads, + ARRAY_SIZE(sd1_pads)); break; case 1: - mxc_request_iomux(MX51_PIN_SD2_CMD, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_request_iomux(MX51_PIN_SD2_CLK, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_request_iomux(MX51_PIN_SD2_DATA0, - IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX51_PIN_SD2_DATA1, - IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX51_PIN_SD2_DATA2, - IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX51_PIN_SD2_DATA3, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD2_CMD, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | - PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_SD2_CLK, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | - PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_SD2_DATA0, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | - PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_SD2_DATA1, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | - PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_SD2_DATA2, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | - PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_SD2_DATA3, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | - PAD_CTL_SRE_FAST); - mxc_request_iomux(MX51_PIN_SD2_CMD, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_request_iomux(MX51_PIN_GPIO1_6, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_GPIO1_6, - PAD_CTL_HYS_ENABLE); - mxc_request_iomux(MX51_PIN_GPIO1_5, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_GPIO1_5, - PAD_CTL_HYS_ENABLE); + imx_iomux_v3_setup_multiple_pads(sd2_pads, + ARRAY_SIZE(sd2_pads)); break; default: printf("Warning: you configured more ESDHC controller" diff --git a/board/freescale/mx51evk/mx51evk_video.c b/board/freescale/mx51evk/mx51evk_video.c index 7be5c9befc..556cb38ca6 100644 --- a/board/freescale/mx51evk/mx51evk_video.c +++ b/board/freescale/mx51evk/mx51evk_video.c @@ -24,7 +24,7 @@ #include <common.h> #include <linux/list.h> #include <asm/gpio.h> -#include <asm/arch/iomux.h> +#include <asm/arch/iomux-mx51.h> #include <linux/fb.h> #include <ipu_pixfmt.h> @@ -67,25 +67,25 @@ static struct fb_videomode const dvi = { void setup_iomux_lcd(void) { /* DI2_PIN15 */ - mxc_request_iomux(MX51_PIN_DI_GP4, IOMUX_CONFIG_ALT4); + imx_iomux_v3_setup_pad(MX51_PAD_DI_GP4__DI2_PIN15); - /* Pad settings for MX51_PIN_DI2_DISP_CLK */ - mxc_iomux_set_pad(MX51_PIN_DI2_DISP_CLK, PAD_CTL_HYS_NONE | - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_MAX | PAD_CTL_SRE_SLOW); + /* Pad settings for DI2_DISP_CLK */ + imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK, + PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW)); /* Turn on 3.3V voltage for LCD */ - mxc_request_iomux(MX51_PIN_CSI2_D12, IOMUX_CONFIG_ALT3); + imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_CSI2_D12__GPIO4_9, + NO_PAD_CTRL)); gpio_direction_output(MX51EVK_LCD_3V3, 1); /* Turn on 5V voltage for LCD */ - mxc_request_iomux(MX51_PIN_CSI2_D13, IOMUX_CONFIG_ALT3); + imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_CSI2_D13__GPIO4_10, + NO_PAD_CTRL)); gpio_direction_output(MX51EVK_LCD_5V, 1); /* Turn on GPIO backlight */ - mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4); - mxc_iomux_set_input(MX51_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT, - INPUT_CTL_PATH1); + imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_DI1_D1_CS__GPIO3_4, + NO_PAD_CTRL)); gpio_direction_output(MX51EVK_LCD_BACKLIGHT, 1); } diff --git a/board/freescale/mx53ard/mx53ard.c b/board/freescale/mx53ard/mx53ard.c index 8d433a3d86..e2dbf63523 100644 --- a/board/freescale/mx53ard/mx53ard.c +++ b/board/freescale/mx53ard/mx53ard.c @@ -23,11 +23,10 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> -#include <asm/arch/mx5x_pins.h> #include <asm/arch/sys_proto.h> #include <asm/arch/crm_regs.h> #include <asm/arch/clock.h> -#include <asm/arch/iomux.h> +#include <asm/arch/iomux-mx53.h> #include <asm/errno.h> #include <netdev.h> #include <mmc.h> @@ -61,9 +60,42 @@ void dram_init_banksize(void) #ifdef CONFIG_NAND_MXC static void setup_iomux_nand(void) { + static const iomux_v3_cfg_t nand_pads[] = { + NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0, + PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1, + PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0, + PAD_CTL_PUS_100K_UP), + NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE, + PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE, + PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B, + PAD_CTL_PUS_100K_UP), + NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B, + PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B, + PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0, + PAD_CTL_PKE | PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1, + PAD_CTL_PKE | PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2, + PAD_CTL_PKE | PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3, + PAD_CTL_PKE | PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4, + PAD_CTL_PKE | PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5, + PAD_CTL_PKE | PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6, + PAD_CTL_PKE | PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7, + PAD_CTL_PKE | PAD_CTL_DSE_HIGH), + }; + u32 i, reg; - #define M4IF_GENP_WEIM_MM_MASK 0x00000001 - #define WEIM_GCR2_MUX16_BYP_GRANT_MASK 0x00001000 reg = __raw_readl(M4IF_BASE_ADDR + 0xc); reg &= ~M4IF_GENP_WEIM_MM_MASK; @@ -74,48 +106,7 @@ static void setup_iomux_nand(void) __raw_writel(reg, WEIM_BASE_ADDR + i); } - mxc_request_iomux(MX53_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_NANDF_CS0, PAD_CTL_DRV_HIGH); - mxc_request_iomux(MX53_PIN_NANDF_CS1, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_NANDF_CS1, PAD_CTL_DRV_HIGH); - mxc_request_iomux(MX53_PIN_NANDF_RB0, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_NANDF_RB0, PAD_CTL_PKE_ENABLE | - PAD_CTL_PUE_PULL | PAD_CTL_100K_PU); - mxc_request_iomux(MX53_PIN_NANDF_CLE, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_NANDF_CLE, PAD_CTL_DRV_HIGH); - mxc_request_iomux(MX53_PIN_NANDF_ALE, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_NANDF_ALE, PAD_CTL_DRV_HIGH); - mxc_request_iomux(MX53_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_NANDF_WP_B, PAD_CTL_PKE_ENABLE | - PAD_CTL_PUE_PULL | PAD_CTL_100K_PU); - mxc_request_iomux(MX53_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_NANDF_RE_B, PAD_CTL_DRV_HIGH); - mxc_request_iomux(MX53_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_NANDF_WE_B, PAD_CTL_DRV_HIGH); - mxc_request_iomux(MX53_PIN_EIM_DA0, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_DA0, PAD_CTL_PKE_ENABLE | - PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH); - mxc_request_iomux(MX53_PIN_EIM_DA1, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_DA1, PAD_CTL_PKE_ENABLE | - PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH); - mxc_request_iomux(MX53_PIN_EIM_DA2, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_DA2, PAD_CTL_PKE_ENABLE | - PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH); - mxc_request_iomux(MX53_PIN_EIM_DA3, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_DA3, PAD_CTL_PKE_ENABLE | - PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH); - mxc_request_iomux(MX53_PIN_EIM_DA4, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_DA4, PAD_CTL_PKE_ENABLE | - PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH); - mxc_request_iomux(MX53_PIN_EIM_DA5, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_DA5, PAD_CTL_PKE_ENABLE | - PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH); - mxc_request_iomux(MX53_PIN_EIM_DA6, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_DA6, PAD_CTL_PKE_ENABLE | - PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH); - mxc_request_iomux(MX53_PIN_EIM_DA7, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_DA7, PAD_CTL_PKE_ENABLE | - PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH); + imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads)); } #else static void setup_iomux_nand(void) @@ -123,24 +114,17 @@ static void setup_iomux_nand(void) } #endif +#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) + static void setup_iomux_uart(void) { - /* UART1 RXD */ - mxc_request_iomux(MX53_PIN_ATA_DMACK, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX53_PIN_ATA_DMACK, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU | - PAD_CTL_ODE_OPENDRAIN_ENABLE); - mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3); - - /* UART1 TXD */ - mxc_request_iomux(MX53_PIN_ATA_DIOW, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX53_PIN_ATA_DIOW, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU | - PAD_CTL_ODE_OPENDRAIN_ENABLE); + static const iomux_v3_cfg_t uart_pads[] = { + NEW_PAD_CTRL(MX53_PAD_PATA_DMACK__UART1_RXD_MUX, UART_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DIOW__UART1_TXD_MUX, UART_PAD_CTRL), + }; + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); } #ifdef CONFIG_FSL_ESDHC @@ -154,9 +138,9 @@ int board_mmc_getcd(struct mmc *mmc) struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; int ret; - mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1); + imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1); gpio_direction_input(IMX_GPIO_NR(1, 1)); - mxc_request_iomux(MX53_PIN_GPIO_4, IOMUX_CONFIG_ALT1); + imx_iomux_v3_setup_pad(MX53_PAD_GPIO_4__GPIO1_4); gpio_direction_input(IMX_GPIO_NR(1, 4)); if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) @@ -167,8 +151,36 @@ int board_mmc_getcd(struct mmc *mmc) return ret; } +#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP) +#define SD_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH) +#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ + PAD_CTL_DSE_HIGH) + int board_mmc_init(bd_t *bis) { + static const iomux_v3_cfg_t sd1_pads[] = { + NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_CLK_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL), + }; + + static const iomux_v3_cfg_t sd2_pads[] = { + NEW_PAD_CTRL(MX53_PAD_SD2_CMD__ESDHC2_CMD, SD_CMD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD2_CLK__ESDHC2_CLK, SD_CLK_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD2_DATA0__ESDHC2_DAT0, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD2_DATA1__ESDHC2_DAT1, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD2_DATA2__ESDHC2_DAT2, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD2_DATA3__ESDHC2_DAT3, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA12__ESDHC2_DAT4, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA13__ESDHC2_DAT5, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA14__ESDHC2_DAT6, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA15__ESDHC2_DAT7, SD_PAD_CTRL), + }; + u32 index; s32 status = 0; @@ -178,56 +190,12 @@ int board_mmc_init(bd_t *bis) for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { switch (index) { case 0: - mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_SD1_DATA0, - IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_SD1_DATA1, - IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_SD1_DATA2, - IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_SD1_DATA3, - IOMUX_CONFIG_ALT0); - - mxc_iomux_set_pad(MX53_PIN_SD1_CMD, 0x1E4); - mxc_iomux_set_pad(MX53_PIN_SD1_CLK, 0xD4); - mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, 0x1D4); - mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, 0x1D4); - mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, 0x1D4); - mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, 0x1D4); + imx_iomux_v3_setup_multiple_pads(sd1_pads, + ARRAY_SIZE(sd1_pads)); break; case 1: - mxc_request_iomux(MX53_PIN_SD2_CMD, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_request_iomux(MX53_PIN_SD2_CLK, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_request_iomux(MX53_PIN_SD2_DATA0, - IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_SD2_DATA1, - IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_SD2_DATA2, - IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_SD2_DATA3, - IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_ATA_DATA12, - IOMUX_CONFIG_ALT2); - mxc_request_iomux(MX53_PIN_ATA_DATA13, - IOMUX_CONFIG_ALT2); - mxc_request_iomux(MX53_PIN_ATA_DATA14, - IOMUX_CONFIG_ALT2); - mxc_request_iomux(MX53_PIN_ATA_DATA15, - IOMUX_CONFIG_ALT2); - - mxc_iomux_set_pad(MX53_PIN_SD2_CMD, 0x1E4); - mxc_iomux_set_pad(MX53_PIN_SD2_CLK, 0xD4); - mxc_iomux_set_pad(MX53_PIN_SD2_DATA0, 0x1D4); - mxc_iomux_set_pad(MX53_PIN_SD2_DATA1, 0x1D4); - mxc_iomux_set_pad(MX53_PIN_SD2_DATA2, 0x1D4); - mxc_iomux_set_pad(MX53_PIN_SD2_DATA3, 0x1D4); - mxc_iomux_set_pad(MX53_PIN_ATA_DATA12, 0x1D4); - mxc_iomux_set_pad(MX53_PIN_ATA_DATA13, 0x1D4); - mxc_iomux_set_pad(MX53_PIN_ATA_DATA14, 0x1D4); - mxc_iomux_set_pad(MX53_PIN_ATA_DATA15, 0x1D4); + imx_iomux_v3_setup_multiple_pads(sd2_pads, + ARRAY_SIZE(sd2_pads)); break; default: printf("Warning: you configured more ESDHC controller" @@ -244,85 +212,70 @@ int board_mmc_init(bd_t *bis) static void weim_smc911x_iomux(void) { + static const iomux_v3_cfg_t weim_smc911x_pads[] = { + /* Data bus */ + NEW_PAD_CTRL(MX53_PAD_EIM_D16__EMI_WEIM_D_16, + PAD_CTL_PKE | PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_EIM_D17__EMI_WEIM_D_17, + PAD_CTL_PKE | PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_EIM_D18__EMI_WEIM_D_18, + PAD_CTL_PKE | PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_EIM_D19__EMI_WEIM_D_19, + PAD_CTL_PKE | PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_EIM_D20__EMI_WEIM_D_20, + PAD_CTL_PKE | PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_EIM_D21__EMI_WEIM_D_21, + PAD_CTL_PKE | PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_EIM_D22__EMI_WEIM_D_22, + PAD_CTL_PKE | PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_EIM_D23__EMI_WEIM_D_23, + PAD_CTL_PKE | PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_EIM_D24__EMI_WEIM_D_24, + PAD_CTL_PKE | PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_EIM_D25__EMI_WEIM_D_25, + PAD_CTL_PKE | PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_EIM_D26__EMI_WEIM_D_26, + PAD_CTL_PKE | PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_EIM_D27__EMI_WEIM_D_27, + PAD_CTL_PKE | PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_EIM_D28__EMI_WEIM_D_28, + PAD_CTL_PKE | PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_EIM_D29__EMI_WEIM_D_29, + PAD_CTL_PKE | PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_EIM_D30__EMI_WEIM_D_30, + PAD_CTL_PKE | PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_EIM_D31__EMI_WEIM_D_31, + PAD_CTL_PKE | PAD_CTL_DSE_HIGH), + + /* Address lines */ + NEW_PAD_CTRL(MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0, + PAD_CTL_PKE | PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1, + PAD_CTL_PKE | PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2, + PAD_CTL_PKE | PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3, + PAD_CTL_PKE | PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4, + PAD_CTL_PKE | PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5, + PAD_CTL_PKE | PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6, + PAD_CTL_PKE | PAD_CTL_DSE_HIGH), + + /* other EIM signals for ethernet */ + MX53_PAD_EIM_OE__EMI_WEIM_OE, + MX53_PAD_EIM_RW__EMI_WEIM_RW, + MX53_PAD_EIM_CS1__EMI_WEIM_CS_1, + }; + /* ETHERNET_INT as GPIO2_31 */ - mxc_request_iomux(MX53_PIN_EIM_EB3, IOMUX_CONFIG_ALT1); + imx_iomux_v3_setup_pad(MX53_PAD_EIM_EB3__GPIO2_31); gpio_direction_input(ETHERNET_INT); - /* Data bus */ - mxc_request_iomux(MX53_PIN_EIM_D16, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_D16, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_D17, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_D17, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_D18, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_D18, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_D19, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_D20, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_D20, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_D21, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_D21, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_D22, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_D22, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_D23, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_D23, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_D24, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_D24, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_D25, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_D25, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_D26, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_D26, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_D27, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_D27, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_D28, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_D28, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_D29, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_D29, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_D30, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_D30, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_D31, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_D31, 0xA4); - - /* Address lines */ - mxc_request_iomux(MX53_PIN_EIM_DA0, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_DA0, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_DA1, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_DA1, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_DA2, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_DA2, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_DA3, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_DA3, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_DA4, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_DA4, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_DA5, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_DA5, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_DA6, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_DA6, 0xA4); - - /* other EIM signals for ethernet */ - mxc_request_iomux(MX53_PIN_EIM_OE, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_EIM_RW, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_EIM_CS1, IOMUX_CONFIG_ALT0); + /* WEIM bus */ + imx_iomux_v3_setup_multiple_pads(weim_smc911x_pads, + ARRAY_SIZE(weim_smc911x_pads)); } static void weim_cs1_settings(void) diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c index 1273501476..727ad65c3e 100644 --- a/board/freescale/mx53evk/mx53evk.c +++ b/board/freescale/mx53evk/mx53evk.c @@ -23,11 +23,10 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> -#include <asm/arch/mx5x_pins.h> #include <asm/arch/sys_proto.h> #include <asm/arch/crm_regs.h> #include <asm/arch/clock.h> -#include <asm/arch/iomux.h> +#include <asm/arch/iomux-mx53.h> #include <asm/errno.h> #include <asm/imx-common/boot_mode.h> #include <netdev.h> @@ -49,69 +48,42 @@ int dram_init(void) return 0; } +#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) + static void setup_iomux_uart(void) { - /* UART1 RXD */ - mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2); - mxc_iomux_set_pad(MX53_PIN_CSI0_D11, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU | - PAD_CTL_ODE_OPENDRAIN_ENABLE); - mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1); - - /* UART1 TXD */ - mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2); - mxc_iomux_set_pad(MX53_PIN_CSI0_D10, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU | - PAD_CTL_ODE_OPENDRAIN_ENABLE); + static const iomux_v3_cfg_t uart_pads[] = { + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL), + }; + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); } +#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ + PAD_CTL_HYS | PAD_CTL_ODE) + static void setup_i2c(unsigned int port_number) { + static const iomux_v3_cfg_t i2c1_pads[] = { + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL), + }; + + static const iomux_v3_cfg_t i2c2_pads[] = { + NEW_PAD_CTRL(MX53_PAD_KEY_ROW3__I2C2_SDA, I2C_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_KEY_COL3__I2C2_SCL, I2C_PAD_CTRL), + }; + switch (port_number) { case 0: - /* i2c1 SDA */ - mxc_request_iomux(MX53_PIN_CSI0_D8, - IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); - mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT, - INPUT_CTL_PATH0); - mxc_iomux_set_pad(MX53_PIN_CSI0_D8, - PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | - PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE | - PAD_CTL_ODE_OPENDRAIN_ENABLE); - /* i2c1 SCL */ - mxc_request_iomux(MX53_PIN_CSI0_D9, - IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); - mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT, - INPUT_CTL_PATH0); - mxc_iomux_set_pad(MX53_PIN_CSI0_D9, - PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | - PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE | - PAD_CTL_ODE_OPENDRAIN_ENABLE); + imx_iomux_v3_setup_multiple_pads(i2c1_pads, + ARRAY_SIZE(i2c1_pads)); break; case 1: - /* i2c2 SDA */ - mxc_request_iomux(MX53_PIN_KEY_ROW3, - IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION); - mxc_iomux_set_input(MX53_I2C2_IPP_SDA_IN_SELECT_INPUT, - INPUT_CTL_PATH0); - mxc_iomux_set_pad(MX53_PIN_KEY_ROW3, - PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | - PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE | - PAD_CTL_ODE_OPENDRAIN_ENABLE); - - /* i2c2 SCL */ - mxc_request_iomux(MX53_PIN_KEY_COL3, - IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION); - mxc_iomux_set_input(MX53_I2C2_IPP_SCL_IN_SELECT_INPUT, - INPUT_CTL_PATH0); - mxc_iomux_set_pad(MX53_PIN_KEY_COL3, - PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | - PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE | - PAD_CTL_ODE_OPENDRAIN_ENABLE); + imx_iomux_v3_setup_multiple_pads(i2c2_pads, + ARRAY_SIZE(i2c2_pads)); break; default: printf("Warning: Wrong I2C port number\n"); @@ -160,54 +132,26 @@ void power_init(void) static void setup_iomux_fec(void) { - /*FEC_MDIO*/ - mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_MDIO, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE); - mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1); - - /*FEC_MDC*/ - mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH); - - /* FEC RXD1 */ - mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, - PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); - - /* FEC RXD0 */ - mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, - PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); - - /* FEC TXD1 */ - mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH); - - /* FEC TXD0 */ - mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH); - - /* FEC TX_EN */ - mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH); - - /* FEC TX_CLK */ - mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, - PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); - - /* FEC RX_ER */ - mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, - PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); - - /* FEC CRS */ - mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, - PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); + static const iomux_v3_cfg_t fec_pads[] = { + NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS | + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE), + NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV, + PAD_CTL_HYS | PAD_CTL_PKE), + }; + + imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); } #ifdef CONFIG_FSL_ESDHC @@ -221,9 +165,9 @@ int board_mmc_getcd(struct mmc *mmc) struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; int ret; - mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1); + imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11); gpio_direction_input(IMX_GPIO_NR(3, 11)); - mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1); + imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13); gpio_direction_input(IMX_GPIO_NR(3, 13)); if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) @@ -234,8 +178,38 @@ int board_mmc_getcd(struct mmc *mmc) return ret; } +#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP) +#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ + PAD_CTL_DSE_HIGH) + int board_mmc_init(bd_t *bis) { + static const iomux_v3_cfg_t sd1_pads[] = { + NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL), + MX53_PAD_EIM_DA13__GPIO3_13, + }; + + static const iomux_v3_cfg_t sd2_pads[] = { + NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD, + SD_CMD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL), + MX53_PAD_EIM_DA11__GPIO3_11, + }; + u32 index; s32 status = 0; @@ -245,109 +219,12 @@ int board_mmc_init(bd_t *bis) for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { switch (index) { case 0: - mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_SD1_DATA0, - IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_SD1_DATA1, - IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_SD1_DATA2, - IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_SD1_DATA3, - IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_EIM_DA13, - IOMUX_CONFIG_ALT1); - - mxc_iomux_set_pad(MX53_PIN_SD1_CMD, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX53_PIN_SD1_CLK, - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | - PAD_CTL_DRV_HIGH); - mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); - mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); - mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); - mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + imx_iomux_v3_setup_multiple_pads(sd1_pads, + ARRAY_SIZE(sd1_pads)); break; case 1: - mxc_request_iomux(MX53_PIN_ATA_RESET_B, - IOMUX_CONFIG_ALT2); - mxc_request_iomux(MX53_PIN_ATA_IORDY, - IOMUX_CONFIG_ALT2); - mxc_request_iomux(MX53_PIN_ATA_DATA8, - IOMUX_CONFIG_ALT4); - mxc_request_iomux(MX53_PIN_ATA_DATA9, - IOMUX_CONFIG_ALT4); - mxc_request_iomux(MX53_PIN_ATA_DATA10, - IOMUX_CONFIG_ALT4); - mxc_request_iomux(MX53_PIN_ATA_DATA11, - IOMUX_CONFIG_ALT4); - mxc_request_iomux(MX53_PIN_ATA_DATA0, - IOMUX_CONFIG_ALT4); - mxc_request_iomux(MX53_PIN_ATA_DATA1, - IOMUX_CONFIG_ALT4); - mxc_request_iomux(MX53_PIN_ATA_DATA2, - IOMUX_CONFIG_ALT4); - mxc_request_iomux(MX53_PIN_ATA_DATA3, - IOMUX_CONFIG_ALT4); - mxc_request_iomux(MX53_PIN_EIM_DA11, - IOMUX_CONFIG_ALT1); - - mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX53_PIN_ATA_IORDY, - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | - PAD_CTL_DRV_HIGH); - mxc_iomux_set_pad(MX53_PIN_ATA_DATA8, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); - mxc_iomux_set_pad(MX53_PIN_ATA_DATA9, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); - mxc_iomux_set_pad(MX53_PIN_ATA_DATA10, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); - mxc_iomux_set_pad(MX53_PIN_ATA_DATA11, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); - mxc_iomux_set_pad(MX53_PIN_ATA_DATA0, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); - mxc_iomux_set_pad(MX53_PIN_ATA_DATA1, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); - mxc_iomux_set_pad(MX53_PIN_ATA_DATA2, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); - mxc_iomux_set_pad(MX53_PIN_ATA_DATA3, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); - + imx_iomux_v3_setup_multiple_pads(sd2_pads, + ARRAY_SIZE(sd2_pads)); break; default: printf("Warning: you configured more ESDHC controller" diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index 8f39c383f1..10e9d36e51 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -24,11 +24,10 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> -#include <asm/arch/mx5x_pins.h> #include <asm/arch/sys_proto.h> #include <asm/arch/crm_regs.h> #include <asm/arch/clock.h> -#include <asm/arch/iomux.h> +#include <asm/arch/iomux-mx53.h> #include <asm/arch/clock.h> #include <asm/errno.h> #include <asm/imx-common/mx5_video.h> @@ -82,86 +81,51 @@ u32 get_board_rev(void) return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; } +#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) + static void setup_iomux_uart(void) { - /* UART1 RXD */ - mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2); - mxc_iomux_set_pad(MX53_PIN_CSI0_D11, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU | - PAD_CTL_ODE_OPENDRAIN_ENABLE); - mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1); - - /* UART1 TXD */ - mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2); - mxc_iomux_set_pad(MX53_PIN_CSI0_D10, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU | - PAD_CTL_ODE_OPENDRAIN_ENABLE); + static const iomux_v3_cfg_t uart_pads[] = { + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL), + }; + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); } #ifdef CONFIG_USB_EHCI_MX5 int board_ehci_hcd_init(int port) { /* request VBUS power enable pin, GPIO7_8 */ - mxc_request_iomux(MX53_PIN_ATA_DA_2, IOMUX_CONFIG_ALT1); - gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1); + imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8); + gpio_direction_output(IMX_GPIO_NR(7, 8), 1); return 0; } #endif static void setup_iomux_fec(void) { - /*FEC_MDIO*/ - mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_MDIO, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE); - mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1); - - /*FEC_MDC*/ - mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH); - - /* FEC RXD1 */ - mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, - PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); - - /* FEC RXD0 */ - mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, - PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); - - /* FEC TXD1 */ - mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH); - - /* FEC TXD0 */ - mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH); - - /* FEC TX_EN */ - mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH); - - /* FEC TX_CLK */ - mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, - PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); - - /* FEC RX_ER */ - mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, - PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); - - /* FEC CRS */ - mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, - PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); + static const iomux_v3_cfg_t fec_pads[] = { + NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS | + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE), + NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV, + PAD_CTL_HYS | PAD_CTL_PKE), + }; + + imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); } #ifdef CONFIG_FSL_ESDHC @@ -175,9 +139,9 @@ int board_mmc_getcd(struct mmc *mmc) struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; int ret; - mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1); + imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11); gpio_direction_input(IMX_GPIO_NR(3, 11)); - mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1); + imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13); gpio_direction_input(IMX_GPIO_NR(3, 13)); if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) @@ -188,8 +152,38 @@ int board_mmc_getcd(struct mmc *mmc) return ret; } +#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP) +#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ + PAD_CTL_DSE_HIGH) + int board_mmc_init(bd_t *bis) { + static const iomux_v3_cfg_t sd1_pads[] = { + NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL), + MX53_PAD_EIM_DA13__GPIO3_13, + }; + + static const iomux_v3_cfg_t sd2_pads[] = { + NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD, + SD_CMD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL), + MX53_PAD_EIM_DA11__GPIO3_11, + }; + u32 index; s32 status = 0; @@ -199,109 +193,12 @@ int board_mmc_init(bd_t *bis) for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { switch (index) { case 0: - mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_SD1_DATA0, - IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_SD1_DATA1, - IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_SD1_DATA2, - IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_SD1_DATA3, - IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_EIM_DA13, - IOMUX_CONFIG_ALT1); - - mxc_iomux_set_pad(MX53_PIN_SD1_CMD, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX53_PIN_SD1_CLK, - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | - PAD_CTL_DRV_HIGH); - mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); - mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); - mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); - mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + imx_iomux_v3_setup_multiple_pads(sd1_pads, + ARRAY_SIZE(sd1_pads)); break; case 1: - mxc_request_iomux(MX53_PIN_ATA_RESET_B, - IOMUX_CONFIG_ALT2); - mxc_request_iomux(MX53_PIN_ATA_IORDY, - IOMUX_CONFIG_ALT2); - mxc_request_iomux(MX53_PIN_ATA_DATA8, - IOMUX_CONFIG_ALT4); - mxc_request_iomux(MX53_PIN_ATA_DATA9, - IOMUX_CONFIG_ALT4); - mxc_request_iomux(MX53_PIN_ATA_DATA10, - IOMUX_CONFIG_ALT4); - mxc_request_iomux(MX53_PIN_ATA_DATA11, - IOMUX_CONFIG_ALT4); - mxc_request_iomux(MX53_PIN_ATA_DATA0, - IOMUX_CONFIG_ALT4); - mxc_request_iomux(MX53_PIN_ATA_DATA1, - IOMUX_CONFIG_ALT4); - mxc_request_iomux(MX53_PIN_ATA_DATA2, - IOMUX_CONFIG_ALT4); - mxc_request_iomux(MX53_PIN_ATA_DATA3, - IOMUX_CONFIG_ALT4); - mxc_request_iomux(MX53_PIN_EIM_DA11, - IOMUX_CONFIG_ALT1); - - mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX53_PIN_ATA_IORDY, - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | - PAD_CTL_DRV_HIGH); - mxc_iomux_set_pad(MX53_PIN_ATA_DATA8, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); - mxc_iomux_set_pad(MX53_PIN_ATA_DATA9, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); - mxc_iomux_set_pad(MX53_PIN_ATA_DATA10, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); - mxc_iomux_set_pad(MX53_PIN_ATA_DATA11, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); - mxc_iomux_set_pad(MX53_PIN_ATA_DATA0, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); - mxc_iomux_set_pad(MX53_PIN_ATA_DATA1, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); - mxc_iomux_set_pad(MX53_PIN_ATA_DATA2, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); - mxc_iomux_set_pad(MX53_PIN_ATA_DATA3, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); - + imx_iomux_v3_setup_multiple_pads(sd2_pads, + ARRAY_SIZE(sd2_pads)); break; default: printf("Warning: you configured more ESDHC controller" @@ -316,28 +213,17 @@ int board_mmc_init(bd_t *bis) } #endif +#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) + static void setup_iomux_i2c(void) { - /* I2C1 SDA */ - mxc_request_iomux(MX53_PIN_CSI0_D8, - IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); - mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT, - INPUT_CTL_PATH0); - mxc_iomux_set_pad(MX53_PIN_CSI0_D8, - PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | - PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE | - PAD_CTL_PUE_PULL | - PAD_CTL_ODE_OPENDRAIN_ENABLE); - /* I2C1 SCL */ - mxc_request_iomux(MX53_PIN_CSI0_D9, - IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); - mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT, - INPUT_CTL_PATH0); - mxc_iomux_set_pad(MX53_PIN_CSI0_D9, - PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | - PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE | - PAD_CTL_PUE_PULL | - PAD_CTL_ODE_OPENDRAIN_ENABLE); + static const iomux_v3_cfg_t i2c1_pads[] = { + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL), + }; + + imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads)); } static int power_init(void) diff --git a/board/freescale/mx53loco/mx53loco_video.c b/board/freescale/mx53loco/mx53loco_video.c index a4d5a6a365..c4654c9b96 100644 --- a/board/freescale/mx53loco/mx53loco_video.c +++ b/board/freescale/mx53loco/mx53loco_video.c @@ -24,7 +24,7 @@ #include <common.h> #include <linux/list.h> #include <asm/gpio.h> -#include <asm/arch/iomux.h> +#include <asm/arch/iomux-mx53.h> #include <linux/fb.h> #include <ipu_pixfmt.h> @@ -63,42 +63,46 @@ static struct fb_videomode const seiko_wvga = { void setup_iomux_lcd(void) { - mxc_request_iomux(MX53_PIN_DI0_DISP_CLK, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DI0_PIN15, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DI0_PIN2, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DI0_PIN3, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT0, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT1, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT2, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT3, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT4, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT5, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT6, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT7, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT8, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT9, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT10, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT11, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT12, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT13, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT14, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT15, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT16, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT17, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT18, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT19, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT20, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT21, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT22, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT23, IOMUX_CONFIG_ALT0); + static const iomux_v3_cfg_t lcd_pads[] = { + MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK, + MX53_PAD_DI0_PIN15__IPU_DI0_PIN15, + MX53_PAD_DI0_PIN2__IPU_DI0_PIN2, + MX53_PAD_DI0_PIN3__IPU_DI0_PIN3, + MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0, + MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1, + MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2, + MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3, + MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4, + MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5, + MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6, + MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7, + MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8, + MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9, + MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10, + MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11, + MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12, + MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13, + MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14, + MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15, + MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16, + MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17, + MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18, + MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19, + MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20, + MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21, + MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22, + MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23, + }; + + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); /* Turn on GPIO backlight */ - mxc_request_iomux(MX53_PIN_EIM_D24, IOMUX_CONFIG_ALT1); + imx_iomux_v3_setup_pad(MX53_PAD_EIM_D24__GPIO3_24); gpio_direction_output(MX53LOCO_LCD_POWER, 1); /* Turn on display contrast */ - mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1); - gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_1), 1); + imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1); + gpio_direction_output(IMX_GPIO_NR(1, 1), 1); } int board_video_skip(void) diff --git a/board/freescale/mx53smd/mx53smd.c b/board/freescale/mx53smd/mx53smd.c index 761f727d08..d04f44fb3e 100644 --- a/board/freescale/mx53smd/mx53smd.c +++ b/board/freescale/mx53smd/mx53smd.c @@ -23,11 +23,10 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> -#include <asm/arch/mx5x_pins.h> #include <asm/arch/sys_proto.h> #include <asm/arch/crm_regs.h> #include <asm/arch/clock.h> -#include <asm/arch/iomux.h> +#include <asm/arch/iomux-mx53.h> #include <asm/errno.h> #include <netdev.h> #include <mmc.h> @@ -56,76 +55,41 @@ void dram_init_banksize(void) gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; } +#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) + static void setup_iomux_uart(void) { - /* UART1 RXD */ - mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2); - mxc_iomux_set_pad(MX53_PIN_CSI0_D11, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU | - PAD_CTL_ODE_OPENDRAIN_ENABLE); - mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1); - - /* UART1 TXD */ - mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2); - mxc_iomux_set_pad(MX53_PIN_CSI0_D10, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU | - PAD_CTL_ODE_OPENDRAIN_ENABLE); + static const iomux_v3_cfg_t uart_pads[] = { + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL), + }; + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); } static void setup_iomux_fec(void) { - /*FEC_MDIO*/ - mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_MDIO, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE); - mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1); - - /*FEC_MDC*/ - mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH); - - /* FEC RXD1 */ - mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, - PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); - - /* FEC RXD0 */ - mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, - PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); - - /* FEC TXD1 */ - mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH); - - /* FEC TXD0 */ - mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH); - - /* FEC TX_EN */ - mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH); - - /* FEC TX_CLK */ - mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, - PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); - - /* FEC RX_ER */ - mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, - PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); - - /* FEC CRS */ - mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, - PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); + static const iomux_v3_cfg_t fec_pads[] = { + NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS | + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE), + NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV, + PAD_CTL_HYS | PAD_CTL_PKE), + }; + + imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); } #ifdef CONFIG_FSL_ESDHC @@ -135,13 +99,28 @@ struct fsl_esdhc_cfg esdhc_cfg[1] = { int board_mmc_getcd(struct mmc *mmc) { - mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1); + imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13); gpio_direction_input(IMX_GPIO_NR(3, 13)); return !gpio_get_value(IMX_GPIO_NR(3, 13)); } +#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP) +#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ + PAD_CTL_DSE_HIGH) + int board_mmc_init(bd_t *bis) { + static const iomux_v3_cfg_t sd1_pads[] = { + NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL), + MX53_PAD_EIM_DA13__GPIO3_13, + }; + u32 index; s32 status = 0; @@ -150,43 +129,8 @@ int board_mmc_init(bd_t *bis) for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { switch (index) { case 0: - mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_SD1_DATA0, - IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_SD1_DATA1, - IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_SD1_DATA2, - IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_SD1_DATA3, - IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_EIM_DA13, - IOMUX_CONFIG_ALT1); - - mxc_iomux_set_pad(MX53_PIN_SD1_CMD, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX53_PIN_SD1_CLK, - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | - PAD_CTL_DRV_HIGH); - mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); - mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); - mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); - mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + imx_iomux_v3_setup_multiple_pads(sd1_pads, + ARRAY_SIZE(sd1_pads)); break; default: diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c index ff7f5e83a0..e33674665f 100644 --- a/board/freescale/mx6qarm2/mx6qarm2.c +++ b/board/freescale/mx6qarm2/mx6qarm2.c @@ -35,17 +35,16 @@ DECLARE_GLOBAL_DATA_PTR; -#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) int dram_init(void) { diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index aec3286e25..bfe4868e8a 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -35,17 +35,16 @@ DECLARE_GLOBAL_DATA_PTR; -#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) int dram_init(void) { @@ -179,7 +178,10 @@ static int mx6sabre_rev(void) * i.MX6Q ARD RevB: 0x02 */ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; - int reg = readl(&ocotp->gp1); + struct fuse_bank *bank = &ocotp->bank[4]; + struct fuse_bank4_regs *fuse = + (struct fuse_bank4_regs *)bank->fuse_regs; + int reg = readl(&fuse->gp1); int ret; switch (reg >> 8 & 0x0F) { diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index 9f9cac82c4..8ce054e428 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -45,29 +45,25 @@ DECLARE_GLOBAL_DATA_PTR; -#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) -#define SPI_PAD_CTRL (PAD_CTL_HYS | \ - PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) -#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) -#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_ODE | PAD_CTL_SRE_FAST) int dram_init(void) diff --git a/board/freescale/mx6qsabresd/mx6qsabresd.c b/board/freescale/mx6qsabresd/mx6qsabresd.c index 0d7cb9efd0..2529826145 100644 --- a/board/freescale/mx6qsabresd/mx6qsabresd.c +++ b/board/freescale/mx6qsabresd/mx6qsabresd.c @@ -34,17 +34,16 @@ DECLARE_GLOBAL_DATA_PTR; -#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) int dram_init(void) { @@ -166,6 +165,7 @@ int board_mmc_getcd(struct mmc *mmc) int board_mmc_init(bd_t *bis) { + s32 status = 0; int i; /* @@ -196,15 +196,15 @@ int board_mmc_init(bd_t *bis) break; default: printf("Warning: you configured more USDHC controllers" - "(%d) than supported by the board\n", i + 1); - return 0; - } + "(%d) then supported by the board (%d)\n", + i + 1, CONFIG_SYS_FSL_USDHC_NUM); + return status; + } - if (fsl_esdhc_initialize(bis, &usdhc_cfg[i])) - printf("Warning: failed to initialize mmc dev %d\n", i); + status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]); } - return 0; + return status; } #endif diff --git a/board/freescale/mx6slevk/Makefile b/board/freescale/mx6slevk/Makefile new file mode 100644 index 0000000000..43af351ba9 --- /dev/null +++ b/board/freescale/mx6slevk/Makefile @@ -0,0 +1,28 @@ +# (C) Copyright 2013 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := mx6slevk.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mx6slevk/imximage.cfg b/board/freescale/mx6slevk/imximage.cfg new file mode 100644 index 0000000000..df39a16658 --- /dev/null +++ b/board/freescale/mx6slevk/imximage.cfg @@ -0,0 +1,118 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ + +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x020c4018 0x00260324 + +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +DATA 4 0x020e0344 0x00003030 +DATA 4 0x020e0348 0x00003030 +DATA 4 0x020e034c 0x00003030 +DATA 4 0x020e0350 0x00003030 +DATA 4 0x020e030c 0x00000030 +DATA 4 0x020e0310 0x00000030 +DATA 4 0x020e0314 0x00000030 +DATA 4 0x020e0318 0x00000030 +DATA 4 0x020e0300 0x00000030 +DATA 4 0x020e031c 0x00000030 +DATA 4 0x020e0338 0x00000028 +DATA 4 0x020e0320 0x00000030 +DATA 4 0x020e032c 0x00000000 +DATA 4 0x020e033c 0x00000008 +DATA 4 0x020e0340 0x00000008 +DATA 4 0x020e05c4 0x00000030 +DATA 4 0x020e05cc 0x00000030 +DATA 4 0x020e05d4 0x00000030 +DATA 4 0x020e05d8 0x00000030 +DATA 4 0x020e05ac 0x00000030 +DATA 4 0x020e05c8 0x00000030 +DATA 4 0x020e05b0 0x00020000 +DATA 4 0x020e05b4 0x00000000 +DATA 4 0x020e05c0 0x00020000 +DATA 4 0x020e05d0 0x00080000 + +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b085c 0x1b4700c7 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b0890 0x00300000 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b082c 0xf3333333 +DATA 4 0x021b0830 0xf3333333 +DATA 4 0x021b0834 0xf3333333 +DATA 4 0x021b0838 0xf3333333 +DATA 4 0x021b0848 0x4241444a +DATA 4 0x021b0850 0x3030312b +DATA 4 0x021b083c 0x20000000 +DATA 4 0x021b0840 0x00000000 +DATA 4 0x021b08c0 0x24911492 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b000c 0x33374133 +DATA 4 0x021b0004 0x00020024 +DATA 4 0x021b0010 0x00100A82 +DATA 4 0x021b0014 0x00000093 +DATA 4 0x021b0018 0x00001688 +DATA 4 0x021b002c 0x0f9f26d2 +DATA 4 0x021b0030 0x0000020e +DATA 4 0x021b0038 0x00190778 +DATA 4 0x021b0008 0x00000000 +DATA 4 0x021b0040 0x0000004f +DATA 4 0x021b0000 0xc3110000 +DATA 4 0x021b001c 0x003f8030 +DATA 4 0x021b001c 0xff0a8030 +DATA 4 0x021b001c 0x82018030 +DATA 4 0x021b001c 0x04028030 +DATA 4 0x021b001c 0x02038030 +DATA 4 0x021b001c 0xff0a8038 +DATA 4 0x021b001c 0x82018038 +DATA 4 0x021b001c 0x04028038 +DATA 4 0x021b001c 0x02038038 +DATA 4 0x021b0800 0xa1310003 +DATA 4 0x021b0020 0x00001800 +DATA 4 0x021b0818 0x00000000 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b0004 0x00025564 +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c new file mode 100644 index 0000000000..69fe8fc0e4 --- /dev/null +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -0,0 +1,102 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam <fabio.estevam@freescale.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <asm/arch/clock.h> +#include <asm/arch/iomux.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/io.h> +#include <asm/sizes.h> +#include <common.h> +#include <fsl_esdhc.h> +#include <mmc.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +static struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC2_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; /* Assume boot SD always present */ +} + +int board_mmc_init(bd_t *bis) +{ + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int checkboard(void) +{ + puts("Board: MX6SLEVK\n"); + + return 0; +} diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index 11e2e8ae48..0c30d76345 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -217,7 +217,7 @@ void fdt_del_flexcan(void *blob) int nodeoff = 0; while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, - "fsl,flexcan-v1.0")) >= 0) { + "fsl,p1010-flexcan")) >= 0) { fdt_del_node(blob, nodeoff); } } diff --git a/board/freescale/p1022ds/Makefile b/board/freescale/p1022ds/Makefile index c6d3418c16..0eeef05266 100644 --- a/board/freescale/p1022ds/Makefile +++ b/board/freescale/p1022ds/Makefile @@ -11,12 +11,26 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o +MINIMAL= + +ifdef CONFIG_SPL_BUILD +ifdef CONFIG_SPL_INIT_MINIMAL +MINIMAL=y +endif +endif + +ifdef MINIMAL + +COBJS-y += spl_minimal.o tlb.o law.o + +else COBJS-y += $(BOARD).o COBJS-y += ddr.o COBJS-y += law.o COBJS-y += tlb.o COBJS-$(CONFIG_FSL_DIU_FB) += diu.o +endif SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/freescale/p1022ds/law.c b/board/freescale/p1022ds/law.c index b23b8f9af5..c4398ddff9 100644 --- a/board/freescale/p1022ds/law.c +++ b/board/freescale/p1022ds/law.c @@ -16,6 +16,7 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p1022ds/spl_minimal.c b/board/freescale/p1022ds/spl_minimal.c new file mode 100644 index 0000000000..8d12fa6c7d --- /dev/null +++ b/board/freescale/p1022ds/spl_minimal.c @@ -0,0 +1,129 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <ns16550.h> +#include <asm/io.h> +#include <nand.h> +#include <asm/fsl_law.h> +#include <asm/fsl_ddr_sdram.h> + + +/* + * Fixed sdram init -- doesn't use serial presence detect. + */ +void sdram_init(void) +{ + volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; + + __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); + __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); +#if CONFIG_CHIP_SELECTS_PER_CTRL > 1 + __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds); + __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config); +#endif + __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3); + __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0); + __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1); + __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2); + + __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2); + __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode); + __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2); + + __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval); + __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); + __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl); + + __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); + __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); + __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); + __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl); + + /* Set, but do not enable the memory */ + __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, + &ddr->sdram_cfg); + + in_be32(&ddr->sdram_cfg); + udelay(500); + + /* Let the controller go */ + out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); + in_be32(&ddr->sdram_cfg); + + set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1); +} + +const static u32 sysclk_tbl[] = { + 66666000, 7499900, 83332500, 8999900, + 99999000, 11111000, 12499800, 13333200 +}; + +void board_init_f(ulong bootflag) +{ + int px_spd; + u32 plat_ratio, sys_clk, bus_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* for FPGA */ + set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); + set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); + + /* initialize selected port with appropriate baud rate */ + px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD)); + sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK]; + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + bus_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + bus_clk / 16 / CONFIG_BAUDRATE); + + puts("\nNAND boot... "); + + /* Initialize the DDR3 */ + sdram_init(); + + /* copy code to RAM and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + relocate_code(CONFIG_SPL_RELOC_STACK, 0, + CONFIG_SPL_RELOC_TEXT_BASE); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + nand_boot(); +} + +void putc(char c) +{ + if (c == '\n') + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); + + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); +} + +void puts(const char *str) +{ + while (*str) + putc(*str++); +} diff --git a/board/freescale/p1022ds/tlb.c b/board/freescale/p1022ds/tlb.c index 71e71f7070..3acc44912d 100644 --- a/board/freescale/p1022ds/tlb.c +++ b/board/freescale/p1022ds/tlb.c @@ -41,6 +41,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1M, 1), +#ifndef CONFIG_SPL_BUILD /* W**G* - Flash/promjet, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, @@ -67,24 +68,31 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_256K, 1), +#endif SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_4K, 1), -#ifdef CONFIG_SYS_RAMBOOT - /* *I*G - eSDHC/eSPI/NAND boot */ +#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) + /* **** - eSDHC/eSPI/NAND boot */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 8, BOOKE_PAGESZ_1G, 1), - - /* map the second 1G */ + /* **** - eSDHC/eSPI/NAND boot - second 1GB of memory */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 9, BOOKE_PAGESZ_1G, 1), #endif -# + +#ifdef CONFIG_SYS_NAND_BASE + /* *I*G - NAND */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_16K, 1), +#endif + }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 5b5b86c822..2e0e0c73aa 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -55,6 +55,13 @@ #define GPIO_SLIC_PIN 30 #define GPIO_SLIC_DATA (1 << (31 - GPIO_SLIC_PIN)) +#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT) +#define GPIO_DDR_RST_PORT 1 +#define GPIO_DDR_RST_PIN 8 +#define GPIO_DDR_RST_DATA (1 << (31 - GPIO_DDR_RST_PIN)) + +#define GPIO_2BIT_MASK (0x3 << (32 - (GPIO_DDR_RST_PIN + 1) * 2)) +#endif #if defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB) #define PCA_IOPORT_I2C_ADDR 0x23 @@ -67,7 +74,7 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { /* GPIO */ {1, 1, 2, 0, 0}, /* GPIO7/PB1 - LOAD_DEFAULT_N */ -#if 0 +#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT) {1, 8, 1, 1, 0}, /* GPIO10/PB8 - DDR_RST */ #endif {0, 15, 1, 0, 0}, /* GPIO11/A15 - WDI */ @@ -159,6 +166,16 @@ void board_gpio_init(void) ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); par_io_t *par_io = (par_io_t *) &(gur->qe_par_io); +#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT) + /* reset DDR3 */ + setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA); + udelay(1000); + clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA); + udelay(1000); + setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA); + /* disable CE_PB8 */ + clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdir1, GPIO_2BIT_MASK); +#endif /* Enable VSC7385 switch */ setbits_be32(&par_io[GPIO_GETH_SW_PORT].cpdat, GPIO_GETH_SW_DATA); @@ -421,6 +438,8 @@ void ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; + const char *soc_usb_compat = "fsl-usb2-dr"; + int err, usb1_off, usb2_off; ft_cpu_setup(blob, bd); @@ -442,5 +461,50 @@ void ft_board_setup(void *blob, bd_t *bd) #if defined(CONFIG_HAS_FSL_DR_USB) fdt_fixup_dr_usb(blob, bd); #endif + +#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) + /* Delete eLBC node as it is muxed with USB2 controller */ + if (hwconfig("usb2")) { + const char *soc_elbc_compat = "fsl,p1020-elbc"; + int off = fdt_node_offset_by_compatible(blob, -1, + soc_elbc_compat); + if (off < 0) { + printf("WARNING: could not find compatible node %s: %s.\n", + soc_elbc_compat, + fdt_strerror(off)); + return; + } + err = fdt_del_node(blob, off); + if (err < 0) { + printf("WARNING: could not remove %s: %s.\n", + soc_elbc_compat, fdt_strerror(err)); + } + return; + } +#endif + +/* Delete USB2 node as it is muxed with eLBC */ + usb1_off = fdt_node_offset_by_compatible(blob, -1, + soc_usb_compat); + if (usb1_off < 0) { + printf("WARNING: could not find compatible node %s: %s.\n", + soc_usb_compat, + fdt_strerror(usb1_off)); + return; + } + usb2_off = fdt_node_offset_by_compatible(blob, usb1_off, + soc_usb_compat); + if (usb2_off < 0) { + printf("WARNING: could not find compatible node %s: %s.\n", + soc_usb_compat, + fdt_strerror(usb2_off)); + return; + } + err = fdt_del_node(blob, usb2_off); + if (err < 0) { + printf("WARNING: could not remove %s: %s.\n", + soc_usb_compat, fdt_strerror(err)); + } + } #endif diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c index 09019e98af..e2bfb0d63d 100644 --- a/board/freescale/p1_p2_rdb_pc/spl_minimal.c +++ b/board/freescale/p1_p2_rdb_pc/spl_minimal.c @@ -81,6 +81,8 @@ void board_init_f(ulong bootflag) ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; #ifndef CONFIG_QE ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); +#elif defined(CONFIG_P1021RDB) + par_io_t *par_io = (par_io_t *)&(gur->qe_par_io); #endif /* initialize selected port with appropriate baud rate */ @@ -102,6 +104,19 @@ void board_init_f(ulong bootflag) __raw_writel(0x00200000, &pgpio->gpdat); udelay(1000); __raw_writel(0x00000000, &pgpio->gpdir); +#elif defined(CONFIG_P1021RDB) + /* init DDR3 reset signal CE_PB8 */ + out_be32(&par_io[1].cpdir1, 0x00004000); + out_be32(&par_io[1].cpodr, 0x00800000); + out_be32(&par_io[1].cppar1, 0x00000000); + /* reset DDR3 */ + out_be32(&par_io[1].cpdat, 0x00800000); + udelay(1000); + out_be32(&par_io[1].cpdat, 0x00000000); + udelay(1000); + out_be32(&par_io[1].cpdat, 0x00800000); + /* disable the CE_PB8 */ + out_be32(&par_io[1].cpdir1, 0x00000000); #endif #ifndef CONFIG_SYS_INIT_L2_ADDR diff --git a/board/freescale/titanium/Makefile b/board/freescale/titanium/Makefile new file mode 100644 index 0000000000..46827f8183 --- /dev/null +++ b/board/freescale/titanium/Makefile @@ -0,0 +1,36 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := titanium.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/titanium/imximage.cfg b/board/freescale/titanium/imximage.cfg new file mode 100644 index 0000000000..1934343416 --- /dev/null +++ b/board/freescale/titanium/imximage.cfg @@ -0,0 +1,178 @@ +/* + * Projectiondesign AS + * Derived from ./board/freescale/mx6qsabrelite/imximage.cfg + * + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Jason Liu <r64343@freescale.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * sd, nand + */ +BOOT_FROM nand + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +#define __ASSEMBLY__ +#include <config.h> +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 + +DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 + +DATA 4, MX6_IOM_DRAM_CAS, 0x00020030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 + +DATA 4, MX6_IOM_DRAM_RESET, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 + +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 + +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 + +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 + +/* (differential input) */ +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +/* disable ddr pullups */ +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +/* (differential input) */ +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 + +/* Read data DQ Byte0-3 delay */ +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 + +/* + * MDMISC mirroring interleaved (row/bank/col) + */ +DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 + +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 +DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7975 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF538E64 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x005B0E21 +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000017 +DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x0408803A +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803B +DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00428039 +DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x09408038 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x434B0350 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x034C0359 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x434B0350 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03650348 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4436383B +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x39393341 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x35373933 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x48254A36 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00440044 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00440044 +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */ +DATA 4, CCM_CCGR5, 0x0F0000C3 +DATA 4, CCM_CCGR6, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F diff --git a/board/freescale/titanium/titanium.c b/board/freescale/titanium/titanium.c new file mode 100644 index 0000000000..5250522d91 --- /dev/null +++ b/board/freescale/titanium/titanium.c @@ -0,0 +1,334 @@ +/* + * Copyright (C) 2013 Stefan Roese <sr@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6q_pins.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/mxc_i2c.h> +#include <asm/imx-common/boot_mode.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <micrel.h> +#include <miiphy.h> +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart2_pads[] = { + MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart4_pads[] = { + MX6_PAD_CSI0_DAT12__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT13__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) + +struct i2c_pads_info i2c_pad_info0 = { + .scl = { + .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO_5_27 | PC, + .gp = IMX_GPIO_NR(5, 27) + }, + .sda = { + .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO_5_26 | PC, + .gp = IMX_GPIO_NR(5, 26) + } +}; + +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC, + .gpio_mode = MX6_PAD_GPIO_3__GPIO_1_3 | PC, + .gp = IMX_GPIO_NR(1, 3) + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC, + .gp = IMX_GPIO_NR(7, 11) + } +}; + +iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +iomux_v3_cfg_t const enet_pads1[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* pin 35 - 1 (PHY_AD2) on reset */ + MX6_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 32 - 1 - (MODE0) all */ + MX6_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 31 - 1 - (MODE1) all */ + MX6_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 28 - 1 - (MODE2) all */ + MX6_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 27 - 1 - (MODE3) all */ + MX6_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ + MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 42 PHY nRST */ + MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +iomux_v3_cfg_t const enet_pads2[] = { + MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +iomux_v3_cfg_t nfc_pads[] = { + MX6_PAD_NANDF_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_WP_B__RAWNAND_RESETN | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_RB0__RAWNAND_READY0 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS0__RAWNAND_CE0N | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS1__RAWNAND_CE1N | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS2__RAWNAND_CE2N | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS3__RAWNAND_CE3N | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_CMD__RAWNAND_RDN | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_CLK__RAWNAND_WRN | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D0__RAWNAND_D0 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D1__RAWNAND_D1 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D2__RAWNAND_D2 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D3__RAWNAND_D3 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D4__RAWNAND_D4 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D5__RAWNAND_D5 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D6__RAWNAND_D6 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D7__RAWNAND_D7 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_DAT0__RAWNAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + imx_iomux_v3_setup_multiple_pads(nfc_pads, + ARRAY_SIZE(nfc_pads)); + + /* config gpmi and bch clock to 100 MHz */ + clrsetbits_le32(&mxc_ccm->cs2cdr, + MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, + MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); + + /* enable gpmi and bch clock gating */ + setbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} + +static void setup_iomux_enet(void) +{ + gpio_direction_output(IMX_GPIO_NR(3, 23), 0); + gpio_direction_output(IMX_GPIO_NR(6, 30), 1); + gpio_direction_output(IMX_GPIO_NR(6, 25), 1); + gpio_direction_output(IMX_GPIO_NR(6, 27), 1); + gpio_direction_output(IMX_GPIO_NR(6, 28), 1); + gpio_direction_output(IMX_GPIO_NR(6, 29), 1); + imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); + gpio_direction_output(IMX_GPIO_NR(6, 24), 1); + + /* Need delay 10ms according to KSZ9021 spec */ + udelay(1000 * 10); + gpio_set_value(IMX_GPIO_NR(3, 23), 1); + + imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); +} + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); + imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); +} + +#ifdef CONFIG_USB_EHCI_MX6 +int board_ehci_hcd_init(int port) +{ + return 0; +} + +#endif + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg usdhc_cfg[1] = { + { USDHC3_BASE_ADDR }, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + + if (cfg->esdhc_base == USDHC3_BASE_ADDR) { + gpio_direction_input(IMX_GPIO_NR(7, 0)); + return !gpio_get_value(IMX_GPIO_NR(7, 0)); + } + + return 0; +} + +int board_mmc_init(bd_t *bis) +{ + /* + * Only one USDHC controller on titianium + */ + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} +#endif + +int board_phy_config(struct phy_device *phydev) +{ + /* min rx data delay */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0); + /* min tx data delay */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0); + /* max rx/tx clock delay, min rx/tx control */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0); + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int ret; + + setup_iomux_enet(); + + ret = cpu_eth_init(bis); + if (ret) + printf("FEC MXC: %s:failed\n", __func__); + + return 0; +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); + + setup_gpmi_nand(); + + return 0; +} + +int checkboard(void) +{ + puts("Board: Titanium\n"); + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* NAND */ + { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) }, + /* 4 bit bus width */ + { "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) }, + { "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) }, + { NULL, 0 }, +}; +#endif + +int misc_init_r(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + + return 0; +} diff --git a/board/genesi/mx51_efikamx/efikamx-usb.c b/board/genesi/mx51_efikamx/efikamx-usb.c index cf020c35cb..cabad70af4 100644 --- a/board/genesi/mx51_efikamx/efikamx-usb.c +++ b/board/genesi/mx51_efikamx/efikamx-usb.c @@ -26,8 +26,7 @@ #include <usb.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> -#include <asm/arch/mx5x_pins.h> -#include <asm/arch/iomux.h> +#include <asm/arch/iomux-mx51.h> #include <asm/gpio.h> #include <usb/ehci-fsl.h> #include <usb/ulpi.h> @@ -35,40 +34,57 @@ #include "../../../drivers/usb/host/ehci.h" -/* USB pin configuration */ -#define USB_PAD_CONFIG (PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \ - PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | \ - PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_PULL) - /* * Configure the USB H1 and USB H2 IOMUX */ void setup_iomux_usb(void) { - setup_iomux_usb_h1(); - - if (machine_is_efikasb()) - setup_iomux_usb_h2(); - - /* USB PHY reset */ - mxc_request_iomux(MX51_PIN_EIM_D27, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_EIM_D27, PAD_CTL_PKE_ENABLE | - PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH); - - /* USB HUB reset */ - mxc_request_iomux(MX51_PIN_GPIO1_5, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_GPIO1_5, PAD_CTL_PKE_ENABLE | - PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH); - - /* WIFI EN (act low) */ - mxc_request_iomux(MX51_PIN_EIM_A22, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_EIM_A22, 0); - /* WIFI RESET */ - mxc_request_iomux(MX51_PIN_EIM_A16, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_EIM_A16, 0); - /* BT EN (act low) */ - mxc_request_iomux(MX51_PIN_EIM_A17, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_EIM_A17, 0); + static const iomux_v3_cfg_t usb_h1_pads[] = { + MX51_PAD_USBH1_CLK__USBH1_CLK, + MX51_PAD_USBH1_DIR__USBH1_DIR, + MX51_PAD_USBH1_STP__USBH1_STP, + MX51_PAD_USBH1_NXT__USBH1_NXT, + MX51_PAD_USBH1_DATA0__USBH1_DATA0, + MX51_PAD_USBH1_DATA1__USBH1_DATA1, + MX51_PAD_USBH1_DATA2__USBH1_DATA2, + MX51_PAD_USBH1_DATA3__USBH1_DATA3, + MX51_PAD_USBH1_DATA4__USBH1_DATA4, + MX51_PAD_USBH1_DATA5__USBH1_DATA5, + MX51_PAD_USBH1_DATA6__USBH1_DATA6, + MX51_PAD_USBH1_DATA7__USBH1_DATA7, + }; + + static const iomux_v3_cfg_t usb_pads[] = { + MX51_PAD_EIM_D27__GPIO2_9, /* USB PHY reset */ + MX51_PAD_GPIO1_5__GPIO1_5, /* USB HUB reset */ + NEW_PAD_CTRL(MX51_PAD_EIM_A22__GPIO2_16, 0), /* WIFI /EN */ + NEW_PAD_CTRL(MX51_PAD_EIM_A16__GPIO2_10, 0), /* WIFI RESET */ + NEW_PAD_CTRL(MX51_PAD_EIM_A17__GPIO2_11, 0), /* BT /EN */ + }; + + imx_iomux_v3_setup_multiple_pads(usb_h1_pads, ARRAY_SIZE(usb_h1_pads)); + + if (machine_is_efikasb()) { + static const iomux_v3_cfg_t usb_h2_pads[] = { + MX51_PAD_EIM_A24__USBH2_CLK, + MX51_PAD_EIM_A25__USBH2_DIR, + MX51_PAD_EIM_A26__USBH2_STP, + MX51_PAD_EIM_A27__USBH2_NXT, + MX51_PAD_EIM_D16__USBH2_DATA0, + MX51_PAD_EIM_D17__USBH2_DATA1, + MX51_PAD_EIM_D18__USBH2_DATA2, + MX51_PAD_EIM_D19__USBH2_DATA3, + MX51_PAD_EIM_D20__USBH2_DATA4, + MX51_PAD_EIM_D21__USBH2_DATA5, + MX51_PAD_EIM_D22__USBH2_DATA6, + MX51_PAD_EIM_D23__USBH2_DATA7, + }; + + imx_iomux_v3_setup_multiple_pads(usb_h2_pads, + ARRAY_SIZE(usb_h2_pads)); + } + + imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); } /* @@ -77,18 +93,18 @@ void setup_iomux_usb(void) static void efika_usb_enable_devices(void) { /* Enable Bluetooth */ - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 0); + gpio_direction_output(IMX_GPIO_NR(2, 11), 0); udelay(10000); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 1); + gpio_set_value(IMX_GPIO_NR(2, 11), 1); /* Enable WiFi */ - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A22), 1); + gpio_direction_output(IMX_GPIO_NR(2, 16), 1); udelay(10000); /* Reset the WiFi chip */ - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 0); + gpio_direction_output(IMX_GPIO_NR(2, 10), 0); udelay(10000); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 1); + gpio_set_value(IMX_GPIO_NR(2, 10), 1); } /* @@ -97,11 +113,11 @@ static void efika_usb_enable_devices(void) static void efika_usb_hub_reset(void) { /* HUB reset */ - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1); + gpio_direction_output(IMX_GPIO_NR(1, 5), 1); udelay(1000); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 0); + gpio_set_value(IMX_GPIO_NR(1, 5), 0); udelay(1000); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1); + gpio_set_value(IMX_GPIO_NR(1, 5), 1); } /* @@ -110,28 +126,26 @@ static void efika_usb_hub_reset(void) static void efika_usb_phy_reset(void) { /* SMSC 3317 PHY reset */ - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 0); + gpio_direction_output(IMX_GPIO_NR(2, 9), 0); udelay(1000); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 1); + gpio_set_value(IMX_GPIO_NR(2, 9), 1); } static void efika_ehci_init(struct usb_ehci *ehci, uint32_t stp_gpio, - uint32_t alt0, uint32_t alt1) + iomux_v3_cfg_t stp_pad_gpio, + iomux_v3_cfg_t stp_pad_usb) { int ret; struct ulpi_regs *ulpi = (struct ulpi_regs *)0; struct ulpi_viewport ulpi_vp; - mxc_request_iomux(stp_gpio, alt0); - mxc_iomux_set_pad(stp_gpio, PAD_CTL_DRV_HIGH | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - gpio_direction_output(IOMUX_TO_GPIO(stp_gpio), 0); + imx_iomux_v3_setup_pad(stp_pad_gpio); + gpio_direction_output(stp_gpio, 0); udelay(1000); - gpio_set_value(IOMUX_TO_GPIO(stp_gpio), 1); + gpio_set_value(stp_gpio, 1); udelay(1000); - mxc_request_iomux(stp_gpio, alt1); - mxc_iomux_set_pad(stp_gpio, USB_PAD_CONFIG); + imx_iomux_v3_setup_pad(stp_pad_usb); udelay(10000); ulpi_vp.viewport_addr = (u32)&ehci->ulpi_viewpoint; @@ -204,11 +218,13 @@ void board_ehci_hcd_postinit(struct usb_ehci *ehci, int port) tmp = (tmp & ~0x3) | 0x01; writel(tmp, OTG_BASE_ADDR + 0x80c); } else if (port == 1) { - efika_ehci_init(ehci, MX51_PIN_USBH1_STP, - IOMUX_CONFIG_ALT2, IOMUX_CONFIG_ALT0); + efika_ehci_init(ehci, IMX_GPIO_NR(1, 27), + MX51_PAD_USBH1_STP__GPIO1_27, + MX51_PAD_USBH1_STP__USBH1_STP); } else if ((port == 2) && machine_is_efikasb()) { - efika_ehci_init(ehci, MX51_PIN_EIM_A26, - IOMUX_CONFIG_ALT1, IOMUX_CONFIG_ALT2); + efika_ehci_init(ehci, IMX_GPIO_NR(2, 20), + MX51_PAD_EIM_A26__GPIO2_20, + MX51_PAD_EIM_A26__USBH2_STP); } if (port) diff --git a/board/genesi/mx51_efikamx/efikamx.c b/board/genesi/mx51_efikamx/efikamx.c index 69d41db530..13582a24e0 100644 --- a/board/genesi/mx51_efikamx/efikamx.c +++ b/board/genesi/mx51_efikamx/efikamx.c @@ -293,7 +293,7 @@ static iomux_v3_cfg_t const efikamx_sdhc1_pads[] = { static iomux_v3_cfg_t const efikamx_sdhc1_cd_pads[] = { MX51_PAD_GPIO1_0__SD1_CD, - MX51_PAD_EIM_CS2__SD1_CD, + NEW_PAD_CTRL(MX51_PAD_EIM_CS2__GPIO2_27, MX51_ESDHC_PAD_CTRL), }; #define EFIKAMX_SDHC1_CD IMX_GPIO_NR(1, 0) diff --git a/board/h2200/h2200.c b/board/h2200/h2200.c index 720b06e4ce..738e480a45 100644 --- a/board/h2200/h2200.c +++ b/board/h2200/h2200.c @@ -32,6 +32,15 @@ int board_eth_init(bd_t *bis) return 0; } +void reset_cpu(ulong ignore) +{ + /* Enable VLIO interface on Hamcop */ + writeb(0x1, 0x4000); + + /* Reset board (cold reset) */ + writeb(0xff, 0x4002); +} + int board_init(void) { /* We have RAM, disable cache */ diff --git a/board/karo/tx25/tx25.c b/board/karo/tx25/tx25.c index 85719a0204..2952eba8c8 100644 --- a/board/karo/tx25/tx25.c +++ b/board/karo/tx25/tx25.c @@ -27,9 +27,8 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> -#include <asm/arch/imx25-pinmux.h> +#include <asm/arch/iomux-mx25.h> #include <asm/gpio.h> -#include <asm/arch/sys_proto.h> DECLARE_GLOBAL_DATA_PTR; @@ -42,36 +41,44 @@ void board_init_f(ulong bootflag) #endif #ifdef CONFIG_FEC_MXC +/* + * FIXME: need to revisit this + * The original code enabled PUE and 100-k pull-down without PKE, so the right + * value here is likely: + * 0 for no pull + * or: + * PAD_CTL_PUS_100K_DOWN for 100-k pull-down + */ +#define FEC_OUT_PAD_CTRL 0 + #define GPIO_FEC_RESET_B IMX_GPIO_NR(4, 7) #define GPIO_FEC_ENABLE_B IMX_GPIO_NR(4, 9) void tx25_fec_init(void) { - struct iomuxc_mux_ctl *muxctl; - struct iomuxc_pad_ctl *padctl; - u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5); - u32 saved_rdata0_mode, saved_rdata1_mode, saved_rx_dv_mode; + static const iomux_v3_cfg_t fec_pads[] = { + MX25_PAD_FEC_TX_CLK__FEC_TX_CLK, + MX25_PAD_FEC_RX_DV__FEC_RX_DV, + MX25_PAD_FEC_RDATA0__FEC_RDATA0, + NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL), + NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL), + NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL), + MX25_PAD_FEC_MDIO__FEC_MDIO, + MX25_PAD_FEC_RDATA1__FEC_RDATA1, + NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL), + + NEW_PAD_CTRL(MX25_PAD_D13__GPIO_4_7, 0), /* FEC_RESET_B */ + NEW_PAD_CTRL(MX25_PAD_D11__GPIO_4_9, 0), /* FEC_ENABLE_B */ + }; + + static const iomux_v3_cfg_t fec_cfg_pads[] = { + MX25_PAD_FEC_RDATA0__GPIO_3_10, + MX25_PAD_FEC_RDATA1__GPIO_3_11, + MX25_PAD_FEC_RX_DV__GPIO_3_12, + }; debug("tx25_fec_init\n"); - /* - * fec pin init is generic - */ - mx25_fec_init_pins(); - - /* - * Set up the FEC_RESET_B and FEC_ENABLE GPIO pins. - * - * FEC_RESET_B: gpio4[7] is ALT 5 mode of pin D13 - * FEC_ENABLE_B: gpio4[9] is ALT 5 mode of pin D11 - */ - muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; - padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; - - writel(gpio_mux_mode, &muxctl->pad_d13); - writel(gpio_mux_mode, &muxctl->pad_d11); - - writel(0x0, &padctl->pad_d13); - writel(0x0, &padctl->pad_d11); + imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); /* drop PHY power and assert reset (low) */ gpio_direction_output(GPIO_FEC_RESET_B, 0); @@ -99,15 +106,10 @@ void tx25_fec_init(void) * RMII mode is selected by FEC_RX_DV which is GPIO 3_12 in mux mode */ /* - * save three current mux modes and set each to gpio mode + * set each mux mode to gpio mode */ - saved_rdata0_mode = readl(&muxctl->pad_fec_rdata0); - saved_rdata1_mode = readl(&muxctl->pad_fec_rdata1); - saved_rx_dv_mode = readl(&muxctl->pad_fec_rx_dv); - - writel(gpio_mux_mode, &muxctl->pad_fec_rdata0); - writel(gpio_mux_mode, &muxctl->pad_fec_rdata1); - writel(gpio_mux_mode, &muxctl->pad_fec_rx_dv); + imx_iomux_v3_setup_multiple_pads(fec_cfg_pads, + ARRAY_SIZE(fec_cfg_pads)); /* * set each to 1 and make each an output @@ -128,19 +130,46 @@ void tx25_fec_init(void) /* * set FEC pins back */ - writel(saved_rdata0_mode, &muxctl->pad_fec_rdata0); - writel(saved_rdata1_mode, &muxctl->pad_fec_rdata1); - writel(saved_rx_dv_mode, &muxctl->pad_fec_rx_dv); + imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); } #else #define tx25_fec_init() #endif -int board_init() -{ #ifdef CONFIG_MXC_UART - mx25_uart1_init_pins(); +/* + * Set up input pins with hysteresis and 100-k pull-ups + */ +#define UART1_IN_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP) +/* + * FIXME: need to revisit this + * The original code enabled PUE and 100-k pull-down without PKE, so the right + * value here is likely: + * 0 for no pull + * or: + * PAD_CTL_PUS_100K_DOWN for 100-k pull-down + */ +#define UART1_OUT_PAD_CTRL 0 + +static void tx25_uart1_init(void) +{ + static const iomux_v3_cfg_t uart1_pads[] = { + NEW_PAD_CTRL(MX25_PAD_UART1_RXD__UART1_RXD, UART1_IN_PAD_CTRL), + NEW_PAD_CTRL(MX25_PAD_UART1_TXD__UART1_TXD, UART1_OUT_PAD_CTRL), + NEW_PAD_CTRL(MX25_PAD_UART1_RTS__UART1_RTS, UART1_OUT_PAD_CTRL), + NEW_PAD_CTRL(MX25_PAD_UART1_CTS__UART1_CTS, UART1_IN_PAD_CTRL), + }; + + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} +#else +#define tx25_uart1_init() #endif + +int board_init() +{ + tx25_uart1_init(); + /* board id for linux */ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; return 0; diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index 29e24fb26f..9cf0fa167c 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007-2010 + * (C) Copyright 2007-2013 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * This program is free software; you can redistribute it and/or @@ -200,9 +200,11 @@ int misc_init_r(void) u32 pbcr; int size_val = 0; u32 reg; +#ifndef CONFIG_LCD4_LWMON5 unsigned long usb2d0cr = 0; unsigned long usb2phy0cr, usb2h0cr = 0; unsigned long sdr0_pfc1, sdr0_srst; +#endif /* * FLASH stuff... @@ -233,6 +235,7 @@ int misc_init_r(void) CONFIG_ENV_ADDR_REDUND + 2 * CONFIG_ENV_SECT_SIZE - 1, &flash_info[cfi_flash_num_flash_banks - 1]); +#ifndef CONFIG_LCD4_LWMON5 /* * USB suff... */ @@ -306,6 +309,7 @@ int misc_init_r(void) /* 7. Reassert internal PHY reset: */ mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY); udelay(1000); +#endif /* * Clear resets @@ -313,7 +317,9 @@ int misc_init_r(void) mtsdr(SDR0_SRST1, 0x00000000); mtsdr(SDR0_SRST0, 0x00000000); +#ifndef CONFIG_LCD4_LWMON5 printf("USB: Host(int phy) Device(ext phy)\n"); +#endif /* * Clear PLB4A0_ACR[WRP] @@ -323,10 +329,12 @@ int misc_init_r(void) reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK; mtdcr(PLB4A0_ACR, reg); +#ifndef CONFIG_LCD4_LWMON5 /* * Init matrix keyboard */ misc_init_r_kbd(); +#endif return 0; } @@ -336,7 +344,7 @@ int checkboard(void) char buf[64]; int i = getenv_f("serial#", buf, sizeof(buf)); - puts("Board: lwmon5"); + printf("Board: %s", __stringify(CONFIG_HOSTNAME)); if (i > 0) { puts(", serial# "); @@ -495,3 +503,66 @@ void board_reset(void) { gpio_write_bit(CONFIG_SYS_GPIO_BOARD_RESET, 1); } + +#ifdef CONFIG_SPL_OS_BOOT +/* + * lwmon5 specific implementation of spl_start_uboot() + * + * RETURN + * 0 if booting into OS is selected (default) + * 1 if booting into U-Boot is selected + */ +int spl_start_uboot(void) +{ + char s[8]; + + env_init(); + getenv_f("boot_os", s, sizeof(s)); + if ((s != NULL) && (strcmp(s, "yes") == 0)) + return 0; + + return 1; +} + +/* + * This function is called from the SPL U-Boot version for + * early init stuff, that needs to be done for OS (e.g. Linux) + * booting. Doing it later in the real U-Boot would not work + * in case that the SPL U-Boot boots Linux directly. + */ +void spl_board_init(void) +{ + const gdc_regs *regs = board_get_regs(); + + /* + * Setup PFC registers, mainly for ethernet support + * later on in Linux + */ + board_early_init_f(); + + /* + * Clear resets + */ + mtsdr(SDR0_SRST1, 0x00000000); + mtsdr(SDR0_SRST0, 0x00000000); + + /* + * Reset Lime controller + */ + gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1); + udelay(500); + gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1); + + out_be32((void *)CONFIG_SYS_LIME_SDRAM_CLOCK, CONFIG_SYS_MB862xx_CCF); + udelay(300); + out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_MB862xx_MMR); + + while (regs->index) { + out_be32((void *)(CONFIG_SYS_LIME_BASE_0 + GC_DISP_BASE) + + regs->index, regs->value); + regs++; + } + + board_backlight_brightness(DEFAULT_BRIGHTNESS); +} +#endif diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c index b64b35a94e..78b8fbc841 100644 --- a/board/lwmon5/sdram.c +++ b/board/lwmon5/sdram.c @@ -6,7 +6,7 @@ * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com * - * (C) Copyright 2007-2008 + * (C) Copyright 2007-2013 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * This program is free software; you can redistribute it and/or @@ -160,6 +160,7 @@ static void program_ecc(u32 start_address, ************************************************************************/ phys_size_t initdram (int board_type) { +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_LCD4_LWMON5) /* CL=4 */ mtsdram(DDR0_02, 0x00000000); @@ -253,6 +254,7 @@ phys_size_t initdram (int board_type) * exceptions are enabled. */ set_mcsr(get_mcsr()); +#endif /* CONFIG_SPL_BUILD */ return (CONFIG_SYS_MBYTES_SDRAM << 20); } diff --git a/board/olimex/mx23_olinuxino/spl_boot.c b/board/olimex/mx23_olinuxino/spl_boot.c index a96c293c0a..6ba8c86eaa 100644 --- a/board/olimex/mx23_olinuxino/spl_boot.c +++ b/board/olimex/mx23_olinuxino/spl_boot.c @@ -29,8 +29,8 @@ #include <asm/arch/imx-regs.h> #include <asm/arch/sys_proto.h> -#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_16MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_SSP (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_SSP (MXS_PAD_8MA | MXS_PAD_PULLUP) const iomux_cfg_t iomux_setup[] = { /* DUART */ diff --git a/board/sandbox/sandbox/sandbox.c b/board/sandbox/sandbox/sandbox.c index 98830139a5..8bdba9267b 100644 --- a/board/sandbox/sandbox/sandbox.c +++ b/board/sandbox/sandbox/sandbox.c @@ -56,6 +56,6 @@ int timer_init(void) int dram_init(void) { - gd->ram_size = CONFIG_DRAM_SIZE; + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; return 0; } diff --git a/board/syteco/zmx25/zmx25.c b/board/syteco/zmx25/zmx25.c index 4f37c59d80..087d856b03 100644 --- a/board/syteco/zmx25/zmx25.c +++ b/board/syteco/zmx25/zmx25.c @@ -32,91 +32,85 @@ #include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> -#include <asm/arch/imx25-pinmux.h> -#include <asm/arch/sys_proto.h> +#include <asm/arch/iomux-mx25.h> DECLARE_GLOBAL_DATA_PTR; int board_init() { - struct iomuxc_mux_ctl *muxctl; - struct iomuxc_pad_ctl *padctl; - struct iomuxc_pad_input_select *inputselect; - u32 gpio_mux_mode0_sion = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION; - u32 gpio_mux_mode1 = MX25_PIN_MUX_MODE(1); - u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5); - u32 gpio_mux_mode6 = MX25_PIN_MUX_MODE(6); - u32 input_select1 = MX25_PAD_INPUT_SELECT_DAISY(1); - u32 input_select2 = MX25_PAD_INPUT_SELECT_DAISY(2); + static const iomux_v3_cfg_t sdhc1_pads[] = { + NEW_PAD_CTRL(MX25_PAD_SD1_CMD__SD1_CMD, NO_PAD_CTRL), + NEW_PAD_CTRL(MX25_PAD_SD1_CLK__SD1_CLK, NO_PAD_CTRL), + NEW_PAD_CTRL(MX25_PAD_SD1_DATA0__SD1_DATA0, NO_PAD_CTRL), + NEW_PAD_CTRL(MX25_PAD_SD1_DATA1__SD1_DATA1, NO_PAD_CTRL), + NEW_PAD_CTRL(MX25_PAD_SD1_DATA2__SD1_DATA2, NO_PAD_CTRL), + NEW_PAD_CTRL(MX25_PAD_SD1_DATA3__SD1_DATA3, NO_PAD_CTRL), + }; + + static const iomux_v3_cfg_t dig_out_pads[] = { + MX25_PAD_CSI_D8__GPIO_1_7, /* Ouput 1 Ctrl */ + MX25_PAD_CSI_D7__GPIO_1_6, /* Ouput 2 Ctrl */ + NEW_PAD_CTRL(MX25_PAD_CSI_D6__GPIO_1_31, 0), /* Ouput 1 Stat */ + NEW_PAD_CTRL(MX25_PAD_CSI_D5__GPIO_1_30, 0), /* Ouput 2 Stat */ + }; + + static const iomux_v3_cfg_t led_pads[] = { + MX25_PAD_CSI_D9__GPIO_4_21, + MX25_PAD_CSI_D4__GPIO_1_29, + }; + + static const iomux_v3_cfg_t can_pads[] = { + NEW_PAD_CTRL(MX25_PAD_GPIO_A__CAN1_TX, NO_PAD_CTRL), + NEW_PAD_CTRL(MX25_PAD_GPIO_B__CAN1_RX, NO_PAD_CTRL), + NEW_PAD_CTRL(MX25_PAD_GPIO_C__CAN2_TX, NO_PAD_CTRL), + NEW_PAD_CTRL(MX25_PAD_GPIO_D__CAN2_RX, NO_PAD_CTRL), + }; + + static const iomux_v3_cfg_t i2c3_pads[] = { + MX25_PAD_CSPI1_SS1__I2C3_DAT, + MX25_PAD_GPIO_E__I2C3_CLK, + }; icache_enable(); - muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; - padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; - inputselect = (struct iomuxc_pad_input_select *)IMX_IOPADINPUTSEL_BASE; - - /* Setup of core volatage selection pin to run at 1.4V */ - writel(gpio_mux_mode5, &muxctl->pad_ext_armclk); /* VCORE GPIO3[15] */ + /* Setup of core voltage selection pin to run at 1.4V */ + imx_iomux_v3_setup_pad(MX25_PAD_EXT_ARMCLK__GPIO_3_15); /* VCORE */ gpio_direction_output(IMX_GPIO_NR(3, 15), 1); - /* Setup of input daisy chains for SD card pins*/ - writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_cmd); - writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_clk); - writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data0); - writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data1); - writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data2); - writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data3); + /* Setup of SD card pins*/ + imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads)); /* Setup of digital output for USB power and OC */ - writel(gpio_mux_mode5, &muxctl->pad_csi_d3); /* USB Power GPIO1[28] */ + imx_iomux_v3_setup_pad(MX25_PAD_CSI_D3__GPIO_1_28); /* USB Power */ gpio_direction_output(IMX_GPIO_NR(1, 28), 1); - writel(gpio_mux_mode5, &muxctl->pad_csi_d2); /* USB OC GPIO1[27] */ + imx_iomux_v3_setup_pad(MX25_PAD_CSI_D2__GPIO_1_27); /* USB OC */ gpio_direction_input(IMX_GPIO_NR(1, 18)); /* Setup of digital output control pins */ - writel(gpio_mux_mode5, &muxctl->pad_csi_d8); /* Ouput 1 Ctrl GPIO1[7] */ - writel(gpio_mux_mode5, &muxctl->pad_csi_d7); /* Ouput 2 Ctrl GPIO1[6] */ - writel(gpio_mux_mode5, &muxctl->pad_csi_d6); /* Ouput 1 Stat GPIO1[31]*/ - writel(gpio_mux_mode5, &muxctl->pad_csi_d5); /* Ouput 2 Stat GPIO1[30]*/ - - writel(0, &padctl->pad_csi_d6); /* Ouput 1 Stat pull up off */ - writel(0, &padctl->pad_csi_d5); /* Ouput 2 Stat pull up off */ + imx_iomux_v3_setup_multiple_pads(dig_out_pads, + ARRAY_SIZE(dig_out_pads)); /* Switch both output drivers off */ gpio_direction_output(IMX_GPIO_NR(1, 7), 0); gpio_direction_output(IMX_GPIO_NR(1, 6), 0); - /* Setup of key input pin GPIO2[29]*/ - writel(gpio_mux_mode5 | MX25_PIN_MUX_SION, &muxctl->pad_kpp_row0); - writel(0, &padctl->pad_kpp_row0); /* Key pull up off */ + /* Setup of key input pin */ + imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX25_PAD_KPP_ROW0__GPIO_2_29, 0)); gpio_direction_input(IMX_GPIO_NR(2, 29)); /* Setup of status LED outputs */ - writel(gpio_mux_mode5, &muxctl->pad_csi_d9); /* GPIO4[21] */ - writel(gpio_mux_mode5, &muxctl->pad_csi_d4); /* GPIO1[29] */ + imx_iomux_v3_setup_multiple_pads(led_pads, ARRAY_SIZE(led_pads)); /* Switch both LEDs off */ gpio_direction_output(IMX_GPIO_NR(4, 21), 0); gpio_direction_output(IMX_GPIO_NR(1, 29), 0); /* Setup of CAN1 and CAN2 signals */ - writel(gpio_mux_mode6, &muxctl->pad_gpio_a); /* CAN1 TX */ - writel(gpio_mux_mode6, &muxctl->pad_gpio_b); /* CAN1 RX */ - writel(gpio_mux_mode6, &muxctl->pad_gpio_c); /* CAN2 TX */ - writel(gpio_mux_mode6, &muxctl->pad_gpio_d); /* CAN2 RX */ - - /* Setup of input daisy chains for CAN signals*/ - writel(input_select1, &inputselect->can1_ipp_ind_canrx); /* CAN1 RX */ - writel(input_select1, &inputselect->can2_ipp_ind_canrx); /* CAN2 RX */ + imx_iomux_v3_setup_multiple_pads(can_pads, ARRAY_SIZE(can_pads)); /* Setup of I2C3 signals */ - writel(gpio_mux_mode1, &muxctl->pad_cspi1_ss1); /* I2C3 SDA */ - writel(gpio_mux_mode1, &muxctl->pad_gpio_e); /* I2C3 SCL */ - - /* Setup of input daisy chains for I2C3 signals*/ - writel(input_select1, &inputselect->i2c3_ipp_sda_in); /* I2C3 SDA */ - writel(input_select2, &inputselect->i2c3_ipp_scl_in); /* I2C3 SCL */ + imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads)); gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; @@ -128,25 +122,32 @@ int board_late_init(void) const char *e; #ifdef CONFIG_FEC_MXC - struct iomuxc_mux_ctl *muxctl; - u32 gpio_mux_mode2 = MX25_PIN_MUX_MODE(2); - u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5); - - /* - * fec pin init is generic - */ - mx25_fec_init_pins(); - - /* - * Set up LAN-RESET and FEC_RX_ERR - * - * LAN-RESET: GPIO3[16] is ALT 5 mode of pin U20 - * FEC_RX_ERR: FEC_RX_ERR is ALT 2 mode of pin R2 - */ - muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; - - writel(gpio_mux_mode5, &muxctl->pad_upll_bypclk); - writel(gpio_mux_mode2, &muxctl->pad_uart2_cts); +/* + * FIXME: need to revisit this + * The original code enabled PUE and 100-k pull-down without PKE, so the right + * value here is likely: + * 0 for no pull + * or: + * PAD_CTL_PUS_100K_DOWN for 100-k pull-down + */ +#define FEC_OUT_PAD_CTRL 0 + + static const iomux_v3_cfg_t fec_pads[] = { + MX25_PAD_FEC_TX_CLK__FEC_TX_CLK, + MX25_PAD_FEC_RX_DV__FEC_RX_DV, + MX25_PAD_FEC_RDATA0__FEC_RDATA0, + NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL), + NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL), + NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL), + MX25_PAD_FEC_MDIO__FEC_MDIO, + MX25_PAD_FEC_RDATA1__FEC_RDATA1, + NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL), + + MX25_PAD_UPLL_BYPCLK__GPIO_3_16, /* LAN-RESET */ + MX25_PAD_UART2_CTS__FEC_RX_ER, /* FEC_RX_ERR */ + }; + + imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); /* assert PHY reset (low) */ gpio_direction_output(IMX_GPIO_NR(3, 16), 0); diff --git a/board/ttcontrol/vision2/vision2.c b/board/ttcontrol/vision2/vision2.c index a471fec23d..9cc758a173 100644 --- a/board/ttcontrol/vision2/vision2.c +++ b/board/ttcontrol/vision2/vision2.c @@ -26,10 +26,9 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> -#include <asm/arch/mx5x_pins.h> #include <asm/arch/crm_regs.h> #include <asm/arch/clock.h> -#include <asm/arch/iomux.h> +#include <asm/arch/iomux-mx51.h> #include <asm/gpio.h> #include <asm/arch/sys_proto.h> #include <i2c.h> @@ -68,85 +67,67 @@ void hw_watchdog_reset(void) int val; /* toggle watchdog trigger pin */ - val = gpio_get_value(66); + val = gpio_get_value(IMX_GPIO_NR(3, 2)); val = val ? 0 : 1; - gpio_set_value(66, val); + gpio_set_value(IMX_GPIO_NR(3, 2), val); } #endif static void init_drive_strength(void) { - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS, - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS, - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM); - - /* Setting pad options */ - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + static const iomux_v3_cfg_t ddr_pads[] = { + NEW_PAD_CTRL(MX51_GRP_PKEDDR, 0), + NEW_PAD_CTRL(MX51_GRP_PKEADDR, PAD_CTL_PKE), + NEW_PAD_CTRL(MX51_GRP_DDRAPKS, 0), + NEW_PAD_CTRL(MX51_GRP_DDRAPUS, PAD_CTL_PUS_100K_UP), + NEW_PAD_CTRL(MX51_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_GRP_DDR_A0, PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX51_GRP_DDR_A1, PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX51_PAD_DRAM_RAS__DRAM_RAS, + PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_DRAM_CAS__DRAM_CAS, + PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_GRP_PKEDDR, PAD_CTL_PKE), + NEW_PAD_CTRL(MX51_GRP_DDRPKS, 0), + NEW_PAD_CTRL(MX51_GRP_HYSDDR0, 0), + NEW_PAD_CTRL(MX51_GRP_HYSDDR1, 0), + NEW_PAD_CTRL(MX51_GRP_HYSDDR2, 0), + NEW_PAD_CTRL(MX51_GRP_HYSDDR3, 0), + NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B0, PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B1, PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B2, PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B4, PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_GRP_DDRPUS, PAD_CTL_PUS_100K_UP), + NEW_PAD_CTRL(MX51_GRP_INMODE1, 0), + NEW_PAD_CTRL(MX51_GRP_DRAM_B0, PAD_CTL_DSE_MED), + NEW_PAD_CTRL(MX51_GRP_DRAM_B1, PAD_CTL_DSE_MED), + NEW_PAD_CTRL(MX51_GRP_DRAM_B2, PAD_CTL_DSE_MED), + NEW_PAD_CTRL(MX51_GRP_DRAM_B4, PAD_CTL_DSE_MED), + + NEW_PAD_CTRL(MX51_PAD_DRAM_SDWE__DRAM_SDWE, MX51_GPIO_PAD_CTRL), + NEW_PAD_CTRL(MX51_PAD_DRAM_SDCKE0__DRAM_SDCKE0, + MX51_GPIO_PAD_CTRL), + NEW_PAD_CTRL(MX51_PAD_DRAM_SDCKE1__DRAM_SDCKE1, + MX51_GPIO_PAD_CTRL), + NEW_PAD_CTRL(MX51_PAD_DRAM_SDCLK__DRAM_SDCLK, + MX51_GPIO_PAD_CTRL), + NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS0__DRAM_SDQS0, + MX51_GPIO_PAD_CTRL), + NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS1__DRAM_SDQS1, + MX51_GPIO_PAD_CTRL), + NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS2__DRAM_SDQS2, + MX51_GPIO_PAD_CTRL), + NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS3__DRAM_SDQS3, + MX51_GPIO_PAD_CTRL), + NEW_PAD_CTRL(MX51_PAD_DRAM_CS0__DRAM_CS0, MX51_GPIO_PAD_CTRL), + NEW_PAD_CTRL(MX51_PAD_DRAM_CS1__DRAM_CS1, MX51_GPIO_PAD_CTRL), + NEW_PAD_CTRL(MX51_PAD_DRAM_DQM0__DRAM_DQM0, MX51_GPIO_PAD_CTRL), + NEW_PAD_CTRL(MX51_PAD_DRAM_DQM1__DRAM_DQM1, MX51_GPIO_PAD_CTRL), + NEW_PAD_CTRL(MX51_PAD_DRAM_DQM2__DRAM_DQM2, MX51_GPIO_PAD_CTRL), + NEW_PAD_CTRL(MX51_PAD_DRAM_DQM3__DRAM_DQM3, MX51_GPIO_PAD_CTRL), + }; + + imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads)); } int dram_init(void) @@ -170,134 +151,102 @@ static void setup_weim(void) static void setup_uart(void) { - unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | - PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST; - /* console RX on Pin EIM_D25 */ - mxc_request_iomux(MX51_PIN_EIM_D25, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_EIM_D25, pad); - /* console TX on Pin EIM_D26 */ - mxc_request_iomux(MX51_PIN_EIM_D26, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_EIM_D26, pad); + static const iomux_v3_cfg_t uart_pads[] = { + MX51_PAD_EIM_D25__UART3_RXD, /* console RX */ + MX51_PAD_EIM_D26__UART3_TXD, /* console TX */ + }; + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); } #ifdef CONFIG_MXC_SPI void spi_io_init(void) { - /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */ - mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - - /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */ - mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - - /* 000: Select mux mode: ALT0 mux port: SS0 of instance: ecspi1. */ - mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, - PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - - /* - * SS1 will be used as GPIO because of uninterrupted - * long SPI transmissions (GPIO4_25) - */ - mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, - PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - - /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */ - mxc_request_iomux(MX51_PIN_DI1_PIN11, IOMUX_CONFIG_ALT7); - mxc_iomux_set_pad(MX51_PIN_DI1_PIN11, - PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - - /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */ - mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); + static const iomux_v3_cfg_t spi_pads[] = { + NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS | + PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS | + PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_CSPI1_SS0__ECSPI1_SS0, PAD_CTL_HYS | + PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1, PAD_CTL_HYS | + PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_DI1_PIN11__ECSPI1_SS2, PAD_CTL_HYS | + PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS | + PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), + }; + + imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads)); } static void reset_peripherals(int reset) { +#ifdef CONFIG_VISION2_HW_1_0 + static const iomux_v3_cfg_t fec_cfg_pads[] = { + /* RXD1 */ + NEW_PAD_CTRL(MX51_PAD_EIM_EB3__GPIO2_23, NO_PAD_CTRL), + /* RXD2 */ + NEW_PAD_CTRL(MX51_PAD_EIM_CS2__GPIO2_27, NO_PAD_CTRL), + /* RXD3 */ + NEW_PAD_CTRL(MX51_PAD_EIM_CS3__GPIO2_28, NO_PAD_CTRL), + /* RXER */ + NEW_PAD_CTRL(MX51_PAD_EIM_CS4__GPIO2_29, NO_PAD_CTRL), + /* COL */ + NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__GPIO3_10, NO_PAD_CTRL), + /* RCLK */ + NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__GPIO3_11, NO_PAD_CTRL), + /* RXD0 */ + NEW_PAD_CTRL(MX51_PAD_NANDF_D9__GPIO3_31, NO_PAD_CTRL), + }; + + static const iomux_v3_cfg_t fec_pads[] = { + NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2), + NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2), + NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2), + MX51_PAD_NANDF_D9__FEC_RDATA0, + NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4), + MX51_PAD_EIM_CS4__FEC_RX_ER, + NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4), + }; +#endif + if (reset) { /* reset_n is on NANDF_D15 */ - gpio_direction_output(89, 0); + gpio_direction_output(IMX_GPIO_NR(3, 25), 0); #ifdef CONFIG_VISION2_HW_1_0 /* * set FEC Configuration lines * set levels of FEC config lines */ - gpio_direction_output(75, 0); - gpio_direction_output(74, 1); - gpio_direction_output(95, 1); + gpio_direction_output(IMX_GPIO_NR(3, 11), 0); + gpio_direction_output(IMX_GPIO_NR(3, 10), 1); + gpio_direction_output(IMX_GPIO_NR(3, 31), 1); /* set direction of FEC config lines */ - gpio_direction_output(59, 0); - gpio_direction_output(60, 0); - gpio_direction_output(61, 0); - gpio_direction_output(55, 1); - - /* FEC_RXD1 - sel GPIO (2-23) for configuration -> 1 */ - mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT1); - /* FEC_RXD2 - sel GPIO (2-27) for configuration -> 0 */ - mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT1); - /* FEC_RXD3 - sel GPIO (2-28) for configuration -> 0 */ - mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT1); - /* FEC_RXER - sel GPIO (2-29) for configuration -> 0 */ - mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT1); - /* FEC_COL - sel GPIO (3-10) for configuration -> 1 */ - mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT3); - /* FEC_RCLK - sel GPIO (3-11) for configuration -> 0 */ - mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT3); - /* FEC_RXD0 - sel GPIO (3-31) for configuration -> 1 */ - mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT3); + gpio_direction_output(IMX_GPIO_NR(2, 27), 0); + gpio_direction_output(IMX_GPIO_NR(2, 28), 0); + gpio_direction_output(IMX_GPIO_NR(2, 29), 0); + gpio_direction_output(IMX_GPIO_NR(2, 23), 1); + + imx_iomux_v3_setup_multiple_pads(fec_cfg_pads, + ARRAY_SIZE(fec_cfg_pads)); #endif - /* - * activate reset_n pin - * Select mux mode: ALT3 mux port: NAND D15 - */ - mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_NANDF_D15, - PAD_CTL_DRV_VOT_HIGH | PAD_CTL_DRV_MAX); + /* activate reset_n pin */ + imx_iomux_v3_setup_pad( + NEW_PAD_CTRL(MX51_PAD_NANDF_D15__GPIO3_25, + PAD_CTL_DSE_MAX)); } else { /* set FEC Control lines */ - gpio_direction_input(89); + gpio_direction_input(IMX_GPIO_NR(3, 25)); udelay(500); #ifdef CONFIG_VISION2_HW_1_0 - /* FEC RDATA[3] */ - mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180); - - /* FEC RDATA[2] */ - mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180); - - /* FEC RDATA[1] */ - mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180); - - /* FEC RDATA[0] */ - mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2); - mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180); - - /* FEC RX_CLK */ - mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180); - - /* FEC RX_ER */ - mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180); - - /* FEC COL */ - mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180); + imx_iomux_v3_setup_multiple_pads(fec_pads, + ARRAY_SIZE(fec_pads)); #endif } } @@ -376,155 +325,94 @@ static void power_init_mx51(void) static void setup_gpios(void) { - unsigned int i; - - /* CAM_SUP_DISn, GPIO1_7 */ - mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_GPIO1_7, 0x82); + static const iomux_v3_cfg_t gpio_pads_1[] = { + NEW_PAD_CTRL(MX51_PAD_GPIO1_7__GPIO1_7, PAD_CTL_PKE | + PAD_CTL_DSE_MED), /* CAM_SUP_DISn */ + NEW_PAD_CTRL(MX51_PAD_DI1_PIN12__GPIO3_1, PAD_CTL_PKE | + PAD_CTL_DSE_MED), /* DAB Display EN */ + NEW_PAD_CTRL(MX51_PAD_DI1_PIN13__GPIO3_2, PAD_CTL_PKE | + PAD_CTL_DSE_MED), /* WDOG_TRIGGER */ + }; + + static const iomux_v3_cfg_t gpio_pads_2[] = { + NEW_PAD_CTRL(MX51_PAD_DI1_D0_CS__GPIO3_3, PAD_CTL_PKE | + PAD_CTL_DSE_MED), /* Display2 TxEN */ + NEW_PAD_CTRL(MX51_PAD_DI1_D1_CS__GPIO3_4, PAD_CTL_PKE | + PAD_CTL_DSE_MED), /* DAB Light EN */ + NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_DIN__GPIO3_5, PAD_CTL_PKE | + PAD_CTL_DSE_MED), /* AUDIO_MUTE */ + NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_DIO__GPIO3_6, PAD_CTL_PKE | + PAD_CTL_DSE_MED), /* SPARE_OUT */ + NEW_PAD_CTRL(MX51_PAD_NANDF_D14__GPIO3_26, PAD_CTL_PKE | + PAD_CTL_DSE_MED), /* BEEPER_EN */ + NEW_PAD_CTRL(MX51_PAD_NANDF_D13__GPIO3_27, PAD_CTL_PKE | + PAD_CTL_DSE_MED), /* POWER_OFF */ + NEW_PAD_CTRL(MX51_PAD_NANDF_D10__GPIO3_30, PAD_CTL_PKE | + PAD_CTL_DSE_MED), /* FRAM_WE */ + NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__GPIO4_26, PAD_CTL_PKE | + PAD_CTL_DSE_MED), /* EXPANSION_EN */ + MX51_PAD_GPIO1_2__PWM1_PWMO, + }; - /* DAB Display EN, GPIO3_1 */ - mxc_request_iomux(MX51_PIN_DI1_PIN12, IOMUX_CONFIG_ALT4); - mxc_iomux_set_pad(MX51_PIN_DI1_PIN12, 0x82); + unsigned int i; - /* WDOG_TRIGGER, GPIO3_2 */ - mxc_request_iomux(MX51_PIN_DI1_PIN13, IOMUX_CONFIG_ALT4); - mxc_iomux_set_pad(MX51_PIN_DI1_PIN13, 0x82); + imx_iomux_v3_setup_multiple_pads(gpio_pads_1, ARRAY_SIZE(gpio_pads_1)); /* Now we need to trigger the watchdog */ WATCHDOG_RESET(); - /* Display2 TxEN, GPIO3_3 */ - mxc_request_iomux(MX51_PIN_DI1_D0_CS, IOMUX_CONFIG_ALT4); - mxc_iomux_set_pad(MX51_PIN_DI1_D0_CS, 0x82); - - /* DAB Light EN, GPIO3_4 */ - mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4); - mxc_iomux_set_pad(MX51_PIN_DI1_D1_CS, 0x82); - - /* AUDIO_MUTE, GPIO3_5 */ - mxc_request_iomux(MX51_PIN_DISPB2_SER_DIN, IOMUX_CONFIG_ALT4); - mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIN, 0x82); - - /* SPARE_OUT, GPIO3_6 */ - mxc_request_iomux(MX51_PIN_DISPB2_SER_DIO, IOMUX_CONFIG_ALT4); - mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIO, 0x82); - - /* BEEPER_EN, GPIO3_26 */ - mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_NANDF_D14, 0x82); - - /* POWER_OFF, GPIO3_27 */ - mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_NANDF_D13, 0x82); - - /* FRAM_WE, GPIO3_30 */ - mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_NANDF_D10, 0x82); - - /* EXPANSION_EN, GPIO4_26 */ - mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x82); - - /* PWM Output GPIO1_2 */ - mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT1); + imx_iomux_v3_setup_multiple_pads(gpio_pads_2, ARRAY_SIZE(gpio_pads_2)); /* * Set GPIO1_4 to high and output; it is used to reset * the system on reboot */ - gpio_direction_output(4, 1); + gpio_direction_output(IMX_GPIO_NR(1, 4), 1); - gpio_direction_output(7, 0); - for (i = 65; i < 71; i++) + gpio_direction_output(IMX_GPIO_NR(1, 7), 0); + for (i = IMX_GPIO_NR(3, 1); i < IMX_GPIO_NR(3, 7); i++) gpio_direction_output(i, 0); - gpio_direction_output(94, 0); + gpio_direction_output(IMX_GPIO_NR(3, 30), 0); /* Set POWER_OFF high */ - gpio_direction_output(91, 1); + gpio_direction_output(IMX_GPIO_NR(3, 27), 1); - gpio_direction_output(90, 0); + gpio_direction_output(IMX_GPIO_NR(3, 26), 0); - gpio_direction_output(122, 0); + gpio_direction_output(IMX_GPIO_NR(4, 26), 0); - gpio_direction_output(121, 1); + gpio_direction_output(IMX_GPIO_NR(4, 25), 1); WATCHDOG_RESET(); } static void setup_fec(void) { - /*FEC_MDIO*/ - mxc_request_iomux(MX51_PIN_EIM_EB2, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_EIM_EB2, 0x1FD); - - /*FEC_MDC*/ - mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004); - - /* FEC RDATA[3] */ - mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180); - - /* FEC RDATA[2] */ - mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180); - - /* FEC RDATA[1] */ - mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180); - - /* FEC RDATA[0] */ - mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2); - mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180); - - /* FEC TDATA[3] */ - mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004); - - /* FEC TDATA[2] */ - mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004); - - /* FEC TDATA[1] */ - mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004); - - /* FEC TDATA[0] */ - mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2); - mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004); - - /* FEC TX_EN */ - mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004); - - /* FEC TX_ER */ - mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004); - - /* FEC TX_CLK */ - mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180); - - /* FEC TX_COL */ - mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180); - - /* FEC RX_CLK */ - mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180); - - /* FEC RX_CRS */ - mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180); - - /* FEC RX_ER */ - mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180); - - /* FEC RX_DV */ - mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2); - mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180); + static const iomux_v3_cfg_t fec_pads[] = { + NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, PAD_CTL_HYS | + PAD_CTL_PUS_22K_UP | PAD_CTL_ODE | + PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST), + MX51_PAD_NANDF_CS3__FEC_MDC, + NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2), + NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2), + NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2), + MX51_PAD_NANDF_D9__FEC_RDATA0, + MX51_PAD_NANDF_CS6__FEC_TDATA3, + MX51_PAD_NANDF_CS5__FEC_TDATA2, + MX51_PAD_NANDF_CS4__FEC_TDATA1, + MX51_PAD_NANDF_D8__FEC_TDATA0, + MX51_PAD_NANDF_CS7__FEC_TX_EN, + MX51_PAD_NANDF_CS2__FEC_TX_ER, + MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK, + NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4), + NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4), + MX51_PAD_EIM_CS5__FEC_CRS, + MX51_PAD_EIM_CS4__FEC_RX_ER, + NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, MX51_PAD_CTRL_4), + }; + + imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); } struct fsl_esdhc_cfg esdhc_cfg[1] = { @@ -536,7 +424,7 @@ int get_mmc_getcd(u8 *cd, struct mmc *mmc) struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) - *cd = gpio_get_value(0); + *cd = gpio_get_value(IMX_GPIO_NR(1, 0)); else *cd = 0; @@ -546,56 +434,24 @@ int get_mmc_getcd(u8 *cd, struct mmc *mmc) #ifdef CONFIG_FSL_ESDHC int board_mmc_init(bd_t *bis) { - mxc_request_iomux(MX51_PIN_SD1_CMD, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_request_iomux(MX51_PIN_SD1_CLK, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_request_iomux(MX51_PIN_SD1_DATA0, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_request_iomux(MX51_PIN_SD1_DATA1, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_request_iomux(MX51_PIN_SD1_DATA2, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_request_iomux(MX51_PIN_SD1_DATA3, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_SD1_CMD, - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | - PAD_CTL_PUE_PULL | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_SD1_CLK, - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | - PAD_CTL_HYS_NONE | PAD_CTL_47K_PU | - PAD_CTL_PUE_PULL | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | - PAD_CTL_PUE_PULL | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | - PAD_CTL_PUE_PULL | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | - PAD_CTL_PUE_PULL | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | - PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD | - PAD_CTL_PUE_PULL | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - mxc_request_iomux(MX51_PIN_GPIO1_0, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_GPIO1_0, - PAD_CTL_HYS_ENABLE); - mxc_request_iomux(MX51_PIN_GPIO1_1, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_GPIO1_1, - PAD_CTL_HYS_ENABLE); + static const iomux_v3_cfg_t sd1_pads[] = { + NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX | + PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX | + PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX | + PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX | + PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX | + PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX | + PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS), + NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS), + }; + + imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads)); esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); @@ -604,13 +460,18 @@ int board_mmc_init(bd_t *bis) void lcd_enable(void) { + static const iomux_v3_cfg_t lcd_pads[] = { + MX51_PAD_DI1_PIN2__DI1_PIN2, + MX51_PAD_DI1_PIN3__DI1_PIN3, + }; + int ret; - mxc_request_iomux(MX51_PIN_DI1_PIN2, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX51_PIN_DI1_PIN3, IOMUX_CONFIG_ALT0); + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); - gpio_set_value(2, 1); - mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT0); + gpio_set_value(IMX_GPIO_NR(1, 2), 1); + imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_2__GPIO1_2, + NO_PAD_CTRL)); ret = ipuv3_fb_init(&nec_nl6448bc26_09c, 0, IPU_PIX_FMT_RGB666); if (ret) @@ -624,9 +485,9 @@ int board_early_init_f(void) init_drive_strength(); /* Setup debug led */ - gpio_direction_output(6, 0); - mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_GPIO1_6, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); + gpio_direction_output(IMX_GPIO_NR(1, 6), 0); + imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6, + PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST)); /* wait a little while to give the pll time to settle */ sdelay(100000); @@ -644,12 +505,12 @@ int board_early_init_f(void) static void backlight(int on) { if (on) { - gpio_set_value(65, 1); + gpio_set_value(IMX_GPIO_NR(3, 1), 1); udelay(10000); - gpio_set_value(68, 1); + gpio_set_value(IMX_GPIO_NR(3, 4), 1); } else { - gpio_set_value(65, 0); - gpio_set_value(68, 0); + gpio_set_value(IMX_GPIO_NR(3, 1), 0); + gpio_set_value(IMX_GPIO_NR(3, 4), 0); } } diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index ac7b89aaec..bb983528b9 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -16,6 +16,7 @@ #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/boot_mode.h> #include <asm/io.h> #include <asm/sizes.h> #include <common.h> @@ -26,18 +27,19 @@ DECLARE_GLOBAL_DATA_PTR; -#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2) +#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9) #define ETH_PHY_RESET IMX_GPIO_NR(3, 29) int dram_init(void) @@ -52,6 +54,17 @@ static iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), }; +iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* Carrier MicroSD Card Detect */ + MX6_PAD_GPIO_2__GPIO_1_2 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + static iomux_v3_cfg_t const usdhc3_pads[] = { MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -59,6 +72,8 @@ static iomux_v3_cfg_t const usdhc3_pads[] = { MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* SOM MicroSD Card Detect */ + MX6_PAD_EIM_DA9__GPIO_3_9 | MUX_PAD_CTRL(NO_PAD_CTRL), }; static iomux_v3_cfg_t const enet_pads[] = { @@ -96,18 +111,66 @@ static void setup_iomux_enet(void) gpio_set_value(ETH_PHY_RESET, 1); } -static struct fsl_esdhc_cfg usdhc_cfg[1] = { +static struct fsl_esdhc_cfg usdhc_cfg[2] = { {USDHC3_BASE_ADDR}, + {USDHC1_BASE_ADDR}, }; -int board_mmc_init(bd_t *bis) +int board_mmc_getcd(struct mmc *mmc) { - imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - usdhc_cfg[0].max_bus_width = 4; + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + } + + return ret; +} - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +int board_mmc_init(bd_t *bis) +{ + s32 status = 0; + u32 index = 0; + + /* + * Following map is done: + * (U-boot device node) (Physical Port) + * mmc0 SOM MicroSD + * mmc1 Carrier board MicroSD + */ + for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { + switch (index) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[0].max_bus_width = 4; + gpio_direction_input(USDHC3_CD_GPIO); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + usdhc_cfg[1].max_bus_width = 4; + gpio_direction_input(USDHC1_CD_GPIO); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) then supported by the board (%d)\n", + index + 1, CONFIG_SYS_FSL_USDHC_NUM); + return status; + } + + status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + } + + return status; } static int mx6_rgmii_rework(struct phy_device *phydev) @@ -162,6 +225,24 @@ int board_early_init_f(void) return 0; } +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, + {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + + return 0; +} + int board_init(void) { /* address of boot parameters */ diff --git a/board/woodburn/woodburn.c b/board/woodburn/woodburn.c index 7c36af080e..3f2e6b52af 100644 --- a/board/woodburn/woodburn.c +++ b/board/woodburn/woodburn.c @@ -28,8 +28,7 @@ #include <asm/arch/imx-regs.h> #include <asm/arch/crm_regs.h> #include <asm/arch/clock.h> -#include <asm/arch/mx35_pins.h> -#include <asm/arch/iomux.h> +#include <asm/arch/iomux-mx35.h> #include <i2c.h> #include <power/pmic.h> #include <fsl_pmic.h> @@ -74,25 +73,29 @@ static void board_setup_sdram(void) static void setup_iomux_fec(void) { + static const iomux_v3_cfg_t fec_pads[] = { + MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, + MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, + MX35_PAD_FEC_RX_DV__FEC_RX_DV, + MX35_PAD_FEC_COL__FEC_COL, + MX35_PAD_FEC_RDATA0__FEC_RDATA_0, + MX35_PAD_FEC_TDATA0__FEC_TDATA_0, + MX35_PAD_FEC_TX_EN__FEC_TX_EN, + MX35_PAD_FEC_MDC__FEC_MDC, + MX35_PAD_FEC_MDIO__FEC_MDIO, + MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, + MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, + MX35_PAD_FEC_CRS__FEC_CRS, + MX35_PAD_FEC_RDATA1__FEC_RDATA_1, + MX35_PAD_FEC_TDATA1__FEC_TDATA_1, + MX35_PAD_FEC_RDATA2__FEC_RDATA_2, + MX35_PAD_FEC_TDATA2__FEC_TDATA_2, + MX35_PAD_FEC_RDATA3__FEC_RDATA_3, + MX35_PAD_FEC_TDATA3__FEC_TDATA_3, + }; + /* setup pins for FEC */ - mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC); + imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); } int woodburn_init(void) @@ -130,9 +133,9 @@ int woodburn_init(void) setup_iomux_fec(); /* setup GPIO1_4 FEC_ENABLE signal */ - mxc_request_iomux(MX35_PIN_SCKR, MUX_CONFIG_ALT5); + imx_iomux_v3_setup_pad(MX35_PAD_SCKR__GPIO1_4); gpio_direction_output(4, 1); - mxc_request_iomux(MX35_PIN_HCKT, MUX_CONFIG_ALT5); + imx_iomux_v3_setup_pad(MX35_PAD_HCKT__GPIO1_9); gpio_direction_output(9, 1); return 0; @@ -228,22 +231,24 @@ struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR}; int board_mmc_init(bd_t *bis) { + static const iomux_v3_cfg_t sdhc1_pads[] = { + MX35_PAD_SD1_CMD__ESDHC1_CMD, + MX35_PAD_SD1_CLK__ESDHC1_CLK, + MX35_PAD_SD1_DATA0__ESDHC1_DAT0, + MX35_PAD_SD1_DATA1__ESDHC1_DAT1, + MX35_PAD_SD1_DATA2__ESDHC1_DAT2, + MX35_PAD_SD1_DATA3__ESDHC1_DAT3, + }; + /* configure pins for SDHC1 only */ - mxc_request_iomux(MX35_PIN_SD1_CMD, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_SD1_CLK, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_SD1_DATA0, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_SD1_DATA1, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_SD1_DATA2, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_SD1_DATA3, MUX_CONFIG_FUNC); + imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads)); /* MMC Card Detect on GPIO1_7 */ - mxc_request_iomux(MX35_PIN_SCKT, MUX_CONFIG_ALT5); - mxc_iomux_set_input(MUX_IN_GPIO1_IN_7, 0x1); + imx_iomux_v3_setup_pad(MX35_PAD_SCKT__GPIO1_7); gpio_direction_input(GPIO_MMC_CD); /* MMC Write Protection on GPIO1_8 */ - mxc_request_iomux(MX35_PIN_FST, MUX_CONFIG_ALT5); - mxc_iomux_set_input(MUX_IN_GPIO1_IN_8, 0x1); + imx_iomux_v3_setup_pad(MX35_PAD_FST__GPIO1_8); gpio_direction_input(GPIO_MMC_WP); esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK); diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c index 70f94c1a59..befbb3a3e5 100644 --- a/board/xilinx/microblaze-generic/microblaze-generic.c +++ b/board/xilinx/microblaze-generic/microblaze-generic.c @@ -38,10 +38,15 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) *((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) = ++(*((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR))); #endif -#ifdef CONFIG_SYS_RESET_ADDRESS - puts ("Reseting board\n"); - asm ("bra r0"); + +#ifdef CONFIG_XILINX_TB_WATCHDOG + hw_watchdog_disable(); #endif + + puts ("Reseting board\n"); + __asm__ __volatile__ (" mts rmsr, r0;" \ + "bra r0"); + return 0; } diff --git a/board/xilinx/microblaze-generic/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h index 50a82d94a0..c846f97f5b 100644 --- a/board/xilinx/microblaze-generic/xparameters.h +++ b/board/xilinx/microblaze-generic/xparameters.h @@ -77,3 +77,7 @@ #define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR 0x42000180 #define XILINX_LLTEMAC_BASEADDR1 0x44200000 #define XILINX_LLTEMAC_FIFO_BASEADDR1 0x42100000 + +/* Watchdog IP is wxi_timebase_wdt_0 */ +#define XILINX_WATCHDOG_BASEADDR 0x50000000 +#define XILINX_WATCHDOG_IRQ 1 diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 1589d21073..b02c364dc9 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -22,15 +22,52 @@ #include <common.h> #include <netdev.h> +#include <zynqpl.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_FPGA +Xilinx_desc fpga; + +/* It can be done differently */ +Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); +Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); +Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); +Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); +#endif + int board_init(void) { +#ifdef CONFIG_FPGA + u32 idcode; + + idcode = zynq_slcr_get_idcode(); + + switch (idcode) { + case XILINX_ZYNQ_7010: + fpga = fpga010; + break; + case XILINX_ZYNQ_7020: + fpga = fpga020; + break; + case XILINX_ZYNQ_7030: + fpga = fpga030; + break; + case XILINX_ZYNQ_7045: + fpga = fpga045; + break; + } +#endif + icache_enable(); +#ifdef CONFIG_FPGA + fpga_init(); + fpga_add(fpga_xilinx, &fpga); +#endif + return 0; } |