diff options
Diffstat (limited to 'board')
96 files changed, 2759 insertions, 3496 deletions
diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index c7f6479a0c..c21d2f3ffa 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -379,7 +379,7 @@ int board_init(void) puts("Cannot find Armada 385 watchdog!\n"); } else { puts("Enabling Armada 385 watchdog.\n"); - wdt_start(watchdog_dev, (u32) 25000000 * 120, 0); + wdt_start(watchdog_dev, 120000, 0); } # endif diff --git a/board/Marvell/db-xc3-24g4xg/.gitignore b/board/Marvell/db-xc3-24g4xg/.gitignore new file mode 100644 index 0000000000..775b9346b8 --- /dev/null +++ b/board/Marvell/db-xc3-24g4xg/.gitignore @@ -0,0 +1 @@ +kwbimage.cfg diff --git a/board/Marvell/db-xc3-24g4xg/MAINTAINERS b/board/Marvell/db-xc3-24g4xg/MAINTAINERS new file mode 100644 index 0000000000..2b27e48181 --- /dev/null +++ b/board/Marvell/db-xc3-24g4xg/MAINTAINERS @@ -0,0 +1,7 @@ +DB-XC3-24G4XG BOARD +M: Chris Packham <chris.packham@alliedtelesis.co.nz> +S: Maintained +F: board/Marvell/db-xc3-24g4xg/ +F: include/configs/db-xc3-24g4xg.h +F: configs/db-xc3-24g4xg_defconfig +F: arch/arm/dts/armada-xp-db-xc3-24g4xg.dts diff --git a/board/Marvell/db-xc3-24g4xg/Makefile b/board/Marvell/db-xc3-24g4xg/Makefile new file mode 100644 index 0000000000..4dd57902d4 --- /dev/null +++ b/board/Marvell/db-xc3-24g4xg/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2015 Stefan Roese <sr@denx.de> + +obj-y := db-xc3-24g4xg.o +extra-y := kwbimage.cfg + +quiet_cmd_sed = SED $@ + cmd_sed = sed $(SEDFLAGS_$(@F)) $< >$(dir $<)$(@F) + +SEDFLAGS_kwbimage.cfg =-e "s|^BINARY.*|BINARY $(srctree)/$(@D)/binary.0 0000005b 00000068|" +$(src)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \ + include/config/auto.conf + $(call if_changed,sed) diff --git a/board/Marvell/db-xc3-24g4xg/README b/board/Marvell/db-xc3-24g4xg/README new file mode 100644 index 0000000000..5e479b433e --- /dev/null +++ b/board/Marvell/db-xc3-24g4xg/README @@ -0,0 +1,4 @@ +To generate binary.0 from Marvell's bin_hdr.elf use the following command + + arm-softfloat-linux-gnueabi-objcopy -S -O binary bin_hdr.elf \ + board/Marvell/db-xc3-24g4xg/binary.0 diff --git a/board/Marvell/db-xc3-24g4xg/binary.0 b/board/Marvell/db-xc3-24g4xg/binary.0 new file mode 100644 index 0000000000..8dd687286a --- /dev/null +++ b/board/Marvell/db-xc3-24g4xg/binary.0 @@ -0,0 +1,11 @@ +-------- +WARNING: +-------- +This file should contain the bin_hdr generated by the original Marvell +U-Boot implementation. As this is currently not included in this +U-Boot version, we have added this placeholder, so that the U-Boot +image can be generated without errors. + +If you have a known to be working bin_hdr for your board, then you +just need to replace this text file here with the binary header +and recompile U-Boot. diff --git a/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c b/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c new file mode 100644 index 0000000000..cae428ffd0 --- /dev/null +++ b/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Stefan Roese <sr@denx.de> + */ + +#include <common.h> +#include <i2c.h> +#include <asm/gpio.h> +#include <linux/mbus.h> +#include <linux/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * These values and defines are taken from the Marvell U-Boot version + * "u-boot-2013.01-2016_T1.0.eng_drop_v6" + */ +#define DB_DX_AC3_GPP_OUT_ENA_LOW (~(BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(6) | BIT(12) \ + | BIT(13) | BIT(16) | BIT(17) | BIT(20) | BIT(29) | BIT(30))) +#define DB_DX_AC3_GPP_OUT_ENA_MID (~(0)) +#define DB_DX_AC3_GPP_OUT_VAL_LOW (BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(6) | BIT(12) \ + | BIT(13) | BIT(16) | BIT(17) | BIT(20) | BIT(29) | BIT(30)) +#define DB_DX_AC3_GPP_OUT_VAL_MID 0x0 +#define DB_DX_AC3_GPP_POL_LOW 0x0 +#define DB_DX_AC3_GPP_POL_MID 0x0 + +int board_early_init_f(void) +{ + /* Configure MPP */ + writel(0x00142222, MVEBU_MPP_BASE + 0x00); + writel(0x11122000, MVEBU_MPP_BASE + 0x04); + writel(0x44444004, MVEBU_MPP_BASE + 0x08); + writel(0x14444444, MVEBU_MPP_BASE + 0x0c); + writel(0x00000001, MVEBU_MPP_BASE + 0x10); + + /* Set GPP Out value */ + writel(DB_DX_AC3_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); + writel(DB_DX_AC3_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); + + /* Set GPP Polarity */ + writel(DB_DX_AC3_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c); + writel(DB_DX_AC3_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); + + /* Set GPP Out Enable */ + writel(DB_DX_AC3_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); + writel(DB_DX_AC3_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + return 0; +} + +#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard(void) +{ + puts("Board: " CONFIG_SYS_BOARD "\n"); + + return 0; +} +#endif diff --git a/board/Marvell/db-xc3-24g4xg/kwbimage.cfg.in b/board/Marvell/db-xc3-24g4xg/kwbimage.cfg.in new file mode 100644 index 0000000000..b8bb7a6eb7 --- /dev/null +++ b/board/Marvell/db-xc3-24g4xg/kwbimage.cfg.in @@ -0,0 +1,12 @@ +# +# Copyright (C) 2014 Stefan Roese <sr@denx.de> +# + +# Armada XP uses version 1 image format +VERSION 1 + +# Boot Media configurations +BOOT_FROM spi + +# Binary Header (bin_hdr) with DDR3 training code +BINARY board/Marvell/db-xc3-24g4xg/binary.0 0000005b 00000068 diff --git a/board/Synology/ds414/ds414.c b/board/Synology/ds414/ds414.c index eb3694ea6e..d23e97c9b9 100644 --- a/board/Synology/ds414/ds414.c +++ b/board/Synology/ds414/ds414.c @@ -115,14 +115,14 @@ MV_DRAM_MODES *ddr3_get_static_ddr_mode(void) return &ds414_ddr_modes[0]; } -MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode) +MV_BIN_SERDES_CFG *board_serdes_cfg_get(void) { return &ds414_serdes_cfg[0]; } u8 board_sat_r_get(u8 dev_num, u8 reg) { - return (0x1 << 1 | 1); + return 0xf; /* All PEX ports support PCIe Gen2 */ } int board_early_init_f(void) diff --git a/board/alliedtelesis/x530/x530.c b/board/alliedtelesis/x530/x530.c index d7d1942fe6..6934fd8017 100644 --- a/board/alliedtelesis/x530/x530.c +++ b/board/alliedtelesis/x530/x530.c @@ -7,6 +7,7 @@ #include <command.h> #include <dm.h> #include <i2c.h> +#include <wdt.h> #include <asm/gpio.h> #include <linux/mbus.h> #include <linux/io.h> @@ -24,6 +25,10 @@ DECLARE_GLOBAL_DATA_PTR; #define CONFIG_NVS_LOCATION 0xf4800000 #define CONFIG_NVS_SIZE (512 << 10) +#ifdef CONFIG_WATCHDOG +static struct udevice *watchdog_dev; +#endif + static struct serdes_map board_serdes_map[] = { {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, @@ -75,6 +80,10 @@ struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) int board_early_init_f(void) { +#ifdef CONFIG_WATCHDOG + watchdog_dev = NULL; +#endif + /* Configure MPP */ writel(0x00001111, MVEBU_MPP_BASE + 0x00); writel(0x00000000, MVEBU_MPP_BASE + 0x04); @@ -88,6 +97,17 @@ int board_early_init_f(void) return 0; } +void spl_board_init(void) +{ +#ifdef CONFIG_WATCHDOG + int ret; + + ret = uclass_get_device(UCLASS_WDT, 0, &watchdog_dev); + if (!ret) + wdt_start(watchdog_dev, 120000, 0); +#endif +} + int board_init(void) { /* address of boot parameters */ @@ -100,9 +120,37 @@ int board_init(void) /* DEV_READYn is not needed for NVS, ignore it when accessing CS1 */ writel(0x00004001, MVEBU_DEV_BUS_BASE + 0xc8); + spl_board_init(); + return 0; } +void arch_preboot_os(void) +{ +#ifdef CONFIG_WATCHDOG + wdt_stop(watchdog_dev); +#endif +} + +#ifdef CONFIG_WATCHDOG +void watchdog_reset(void) +{ + static ulong next_reset = 0; + ulong now; + + if (!watchdog_dev) + return; + + now = timer_get_us(); + + /* Do not reset the watchdog too often */ + if (now > next_reset) { + wdt_reset(watchdog_dev); + next_reset = now + 1000; + } +} +#endif + static int led_7seg_init(unsigned int segments) { int node; diff --git a/board/aristainetos/aristainetos-v2.c b/board/aristainetos/aristainetos-v2.c index b33a75c82c..63b1057553 100644 --- a/board/aristainetos/aristainetos-v2.c +++ b/board/aristainetos/aristainetos-v2.c @@ -33,7 +33,7 @@ #include <micrel.h> #include <spi.h> #include <video.h> -#include <../drivers/video/ipu.h> +#include <../drivers/video/imx/ipu.h> #if defined(CONFIG_VIDEO_BMP_LOGO) #include <bmp_logo.h> #endif diff --git a/board/atmel/sama5d2_icp/Kconfig b/board/atmel/sama5d2_icp/Kconfig new file mode 100644 index 0000000000..3859845510 --- /dev/null +++ b/board/atmel/sama5d2_icp/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SAMA5D2_ICP + +config SYS_BOARD + default "sama5d2_icp" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "sama5d2_icp" + +endif diff --git a/board/atmel/sama5d2_icp/MAINTAINERS b/board/atmel/sama5d2_icp/MAINTAINERS new file mode 100644 index 0000000000..db984b6ae4 --- /dev/null +++ b/board/atmel/sama5d2_icp/MAINTAINERS @@ -0,0 +1,7 @@ +SAMA5D2 ICP BOARD +M: Eugen Hristev <eugen.hristev@microchip.com> +S: Maintained +F: board/atmel/sama5d2_icp/ +F: include/configs/sama5d2_icp.h +F: configs/sama5d2_icp_mmc_defconfig + diff --git a/board/atmel/sama5d2_icp/Makefile b/board/atmel/sama5d2_icp/Makefile new file mode 100644 index 0000000000..fd7e870599 --- /dev/null +++ b/board/atmel/sama5d2_icp/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018 Microchip Technology Inc. +# Eugen Hristev <eugen.hristev@microchip.com> +# + +obj-y += sama5d2_icp.o diff --git a/board/atmel/sama5d2_icp/sama5d2_icp.c b/board/atmel/sama5d2_icp/sama5d2_icp.c new file mode 100644 index 0000000000..807cfcdb19 --- /dev/null +++ b/board/atmel/sama5d2_icp/sama5d2_icp.c @@ -0,0 +1,191 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Microchip Technology, Inc. + * Eugen Hristev <eugen.hristev@microchip.com> + */ + +#include <common.h> +#include <debug_uart.h> +#include <asm/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/atmel_pio4.h> +#include <asm/arch/atmel_mpddrc.h> +#include <asm/arch/atmel_sdhci.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/arch/sama5d2.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_late_init(void) +{ + return 0; +} + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +static void board_uart0_hw_init(void) +{ + atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, ATMEL_PIO_PUEN_MASK); /* URXD0 */ + atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */ + + at91_periph_clk_enable(ATMEL_ID_UART0); +} + +void board_debug_uart_init(void) +{ + board_uart0_hw_init(); +} +#endif + +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +#define MAC24AA_MAC_OFFSET 0xfa + +int misc_init_r(void) +{ +#ifdef CONFIG_I2C_EEPROM + at91_set_ethaddr(MAC24AA_MAC_OFFSET); +#endif + return 0; +} + +/* SPL */ +#ifdef CONFIG_SPL_BUILD + +#ifdef CONFIG_SD_BOOT +void spl_mmc_init(void) +{ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 1, 0); /* CMD */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 2, 0); /* DAT0 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 3, 0); /* DAT1 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 4, 0); /* DAT2 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 5, 0); /* DAT3 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 0, 0); /* CK */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 13, 0); /* CD */ + + at91_periph_clk_enable(ATMEL_ID_SDMMC0); +} +#endif + +void spl_board_init(void) +{ +#ifdef CONFIG_SD_BOOT + spl_mmc_init(); +#endif +} + +void spl_display_print(void) +{ +} + +static void ddrc_conf(struct atmel_mpddrc_config *ddrc) +{ + ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM); + + ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | + ATMEL_MPDDRC_CR_NR_ROW_14 | + ATMEL_MPDDRC_CR_CAS_DDR_CAS5 | + ATMEL_MPDDRC_CR_DIC_DS | + ATMEL_MPDDRC_CR_NB_8BANKS | + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | + ATMEL_MPDDRC_CR_UNAL_SUPPORTED); + + ddrc->rtr = 0x298; + + ddrc->tpr0 = ((6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) | + (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) | + (3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) | + (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) | + (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) | + (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) | + (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) | + (4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET)); + + ddrc->tpr1 = ((27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) | + (29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) | + (0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) | + (10 << ATMEL_MPDDRC_TPR1_TXP_OFFSET)); + + ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) | + (0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) | + (0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) | + (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) | + (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET)); +} + +void mem_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; + struct atmel_mpddrc_config ddrc_config; + u32 reg; + + ddrc_conf(&ddrc_config); + + at91_periph_clk_enable(ATMEL_ID_MPDDRC); + writel(AT91_PMC_DDR, &pmc->scer); + + reg = readl(&mpddrc->io_calibr); + reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV; + reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55; + reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO; + reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100); + writel(reg, &mpddrc->io_calibr); + + writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE, + &mpddrc->rd_data_path); + + ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config); + + writel(0x5355, &mpddrc->cal_mr4); + writel(64, &mpddrc->tim_cal); +} + +void at91_pmc_init(void) +{ + u32 tmp; + + /* + * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz + * so we need to slow down and configure MCKR accordingly. + * This is why we have a special flavor of the switching function. + */ + tmp = AT91_PMC_MCKR_PLLADIV_2 | + AT91_PMC_MCKR_MDIV_3 | + AT91_PMC_MCKR_CSS_MAIN; + at91_mck_init_down(tmp); + + tmp = AT91_PMC_PLLAR_29 | + AT91_PMC_PLLXR_PLLCOUNT(0x3f) | + AT91_PMC_PLLXR_MUL(82) | + AT91_PMC_PLLXR_DIV(1); + at91_plla_init(tmp); + + tmp = AT91_PMC_MCKR_H32MXDIV | + AT91_PMC_MCKR_PLLADIV_2 | + AT91_PMC_MCKR_MDIV_3 | + AT91_PMC_MCKR_CSS_PLLA; + at91_mck_init(tmp); +} +#endif diff --git a/board/bosch/guardian/Kconfig b/board/bosch/guardian/Kconfig new file mode 100644 index 0000000000..1417da61f0 --- /dev/null +++ b/board/bosch/guardian/Kconfig @@ -0,0 +1,15 @@ +if TARGET_AM335X_GUARDIAN + +config SYS_BOARD + default "guardian" + +config SYS_VENDOR + default "bosch" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "am335x_guardian" + +endif diff --git a/board/bosch/guardian/MAINTAINERS b/board/bosch/guardian/MAINTAINERS new file mode 100644 index 0000000000..8d16ec0202 --- /dev/null +++ b/board/bosch/guardian/MAINTAINERS @@ -0,0 +1,6 @@ +Guardian BOARD +M: Sjoerd Simons <sjoerd.simons@collabora.co.uk> +S: Maintained +F: board/bosch/guardian/ +F: include/configs/am335x_guardian.h +F: configs/am335x_guardian_defconfig diff --git a/board/bosch/guardian/Makefile b/board/bosch/guardian/Makefile new file mode 100644 index 0000000000..11625c9dd6 --- /dev/null +++ b/board/bosch/guardian/Makefile @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Makefile +# +# Copyright (C) 2018 Robert Bosch Power Tools GmbH +# + +ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),) +obj-y := mux.o +endif + +obj-y += board.o diff --git a/board/bosch/guardian/board.c b/board/bosch/guardian/board.c new file mode 100644 index 0000000000..86ab180f5c --- /dev/null +++ b/board/bosch/guardian/board.c @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * board.c + * + * Board functions for Bosch Guardian + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Robert Bosch Power Tools GmbH + */ + +#include <common.h> +#include <cpsw.h> +#include <dm.h> +#include <environment.h> +#include <environment.h> +#include <errno.h> +#include <i2c.h> +#include <miiphy.h> +#include <panel.h> +#include <power/tps65217.h> +#include <power/tps65910.h> +#include <spl.h> +#include <watchdog.h> +#include <asm/arch/clock.h> +#include <asm/arch/cpu.h> +#include <asm/arch/ddr_defs.h> +#include <asm/arch/gpio.h> +#include <asm/arch/hardware.h> +#include <asm/arch/mem.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/omap.h> +#include <asm/arch/sys_proto.h> +#include <asm/emif.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include "board.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +static const struct ddr_data ddr3_data = { + .datardsratio0 = MT41K128M16JT125K_RD_DQS, + .datawdsratio0 = MT41K128M16JT125K_WR_DQS, + .datafwsratio0 = MT41K128M16JT125K_PHY_FIFO_WE, + .datawrsratio0 = MT41K128M16JT125K_PHY_WR_DATA, +}; + +static const struct cmd_control ddr3_cmd_ctrl_data = { + .cmd0csratio = MT41K128M16JT125K_RATIO, + .cmd0iclkout = MT41K128M16JT125K_INVERT_CLKOUT, + + .cmd1csratio = MT41K128M16JT125K_RATIO, + .cmd1iclkout = MT41K128M16JT125K_INVERT_CLKOUT, + + .cmd2csratio = MT41K128M16JT125K_RATIO, + .cmd2iclkout = MT41K128M16JT125K_INVERT_CLKOUT, +}; + +static struct emif_regs ddr3_emif_reg_data = { + .sdram_config = MT41K128M16JT125K_EMIF_SDCFG, + .ref_ctrl = MT41K128M16JT125K_EMIF_SDREF, + .sdram_tim1 = MT41K128M16JT125K_EMIF_TIM1, + .sdram_tim2 = MT41K128M16JT125K_EMIF_TIM2, + .sdram_tim3 = MT41K128M16JT125K_EMIF_TIM3, + .zq_config = MT41K128M16JT125K_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K128M16JT125K_EMIF_READ_LATENCY, +}; + +#define OSC (V_OSCK / 1000000) +const struct dpll_params dpll_ddr = { + 400, OSC - 1, 1, -1, -1, -1, -1}; + +void am33xx_spl_board_init(void) +{ + int mpu_vdd; + int usb_cur_lim; + + /* Get the frequency */ + dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); + + if (i2c_probe(TPS65217_CHIP_PM)) + return; + + /* + * Increase USB current limit to 1300mA or 1800mA and set + * the MPU voltage controller as needed. + */ + if (dpll_mpu_opp100.m == MPUPLL_M_1000) { + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; + } else { + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; + } + + if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, + TPS65217_POWER_PATH, + usb_cur_lim, + TPS65217_USB_INPUT_CUR_LIMIT_MASK)) + puts("tps65217_reg_write failure\n"); + + /* Set DCDC3 (CORE) voltage to 1.125V */ + if (tps65217_voltage_update(TPS65217_DEFDCDC3, + TPS65217_DCDC_VOLT_SEL_1125MV)) { + puts("tps65217_voltage_update failure\n"); + return; + } + + /* Set CORE Frequencies to OPP100 */ + do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); + + /* Set DCDC2 (MPU) voltage */ + if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { + puts("tps65217_voltage_update failure\n"); + return; + } + + /* + * Set LDO3 to 1.8V and LDO4 to 3.3V + */ + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, + TPS65217_DEFLS1, + TPS65217_LDO_VOLTAGE_OUT_1_8, + TPS65217_LDO_MASK)) + puts("tps65217_reg_write failure\n"); + + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, + TPS65217_DEFLS2, + TPS65217_LDO_VOLTAGE_OUT_3_3, + TPS65217_LDO_MASK)) + puts("tps65217_reg_write failure\n"); + + /* Set MPU Frequency to what we detected now that voltages are set */ + do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + enable_i2c0_pin_mux(); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + + return &dpll_ddr; +} + +void set_uart_mux_conf(void) +{ + enable_uart0_pin_mux(); +} + +void set_mux_conf_regs(void) +{ + enable_board_pin_mux(); +} + +const struct ctrl_ioregs ioregs = { + .cm0ioctl = MT41K128M16JT125K_IOCTRL_VALUE, + .cm1ioctl = MT41K128M16JT125K_IOCTRL_VALUE, + .cm2ioctl = MT41K128M16JT125K_IOCTRL_VALUE, + .dt0ioctl = MT41K128M16JT125K_IOCTRL_VALUE, + .dt1ioctl = MT41K128M16JT125K_IOCTRL_VALUE, +}; + +void sdram_init(void) +{ + config_ddr(400, &ioregs, + &ddr3_data, + &ddr3_cmd_ctrl_data, + &ddr3_emif_reg_data, 0); +} +#endif + +int board_init(void) +{ +#if defined(CONFIG_HW_WATCHDOG) + hw_watchdog_init(); +#endif + + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_NAND + gpmc_init(); +#endif + return 0; +} diff --git a/board/bosch/guardian/board.h b/board/bosch/guardian/board.h new file mode 100644 index 0000000000..b301caf47f --- /dev/null +++ b/board/bosch/guardian/board.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * board.h + * + * Board header for Bosch Guardian + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Robert Bosch Power Tools GmbH + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +void enable_uart0_pin_mux(void); +void enable_i2c0_pin_mux(void); +void enable_board_pin_mux(void); +#endif diff --git a/board/bosch/guardian/mux.c b/board/bosch/guardian/mux.c new file mode 100644 index 0000000000..708c3e7fdd --- /dev/null +++ b/board/bosch/guardian/mux.c @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * mux.c + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Robert Bosch Power Tools GmbH + */ + +#include <common.h> +#include <i2c.h> +#include <asm/arch/hardware.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/io.h> +#include "board.h" + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux adc_voltages_en[] = { + {OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux asp_power_en[] = { + {OFFSET(mcasp0_aclkx), (MODE(7) | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux switch_off_3v6_pin_mux[] = { + {OFFSET(mii1_txd0), (MODE(7) | PULLUP_EN)}, + /* + * The uart1 lines are made floating inputs, based on the Guardian + * A2 Sample Power Supply Schematics + */ + {OFFSET(uart1_rxd), (MODE(7) | PULLUDDIS)}, + {OFFSET(uart1_txd), (MODE(7) | PULLUDDIS)}, + {-1}, +}; + +#ifdef CONFIG_NAND +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, +#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT + {OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, +#endif + {OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)}, + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, + {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, + {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, + {-1}, +}; +#endif + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + +void enable_board_pin_mux(void) +{ +#ifdef CONFIG_NAND + configure_module_pin_mux(nand_pin_mux); +#endif + configure_module_pin_mux(adc_voltages_en); + configure_module_pin_mux(asp_power_en); + configure_module_pin_mux(switch_off_3v6_pin_mux); +} diff --git a/board/compulab/cl-som-am57x/Kconfig b/board/compulab/cl-som-am57x/Kconfig deleted file mode 100644 index 85fc9a1fdb..0000000000 --- a/board/compulab/cl-som-am57x/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_CL_SOM_AM57X - -config SYS_BOARD - default "cl-som-am57x" - -config SYS_VENDOR - default "compulab" - -config SYS_CONFIG_NAME - default "cl-som-am57x" - -endif diff --git a/board/compulab/cl-som-am57x/MAINTAINERS b/board/compulab/cl-som-am57x/MAINTAINERS deleted file mode 100644 index e0195f4610..0000000000 --- a/board/compulab/cl-som-am57x/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -CL-SOM-AM57x BOARD -M: Uri Mashiach <uri.mashiach@compulab.co.il> -S: Maintained -F: board/compulab/cl-som-am57x/ -F: include/configs/cl-som-am57x.h -F: configs/cl-som-am57x_defconfig diff --git a/board/compulab/cl-som-am57x/Makefile b/board/compulab/cl-som-am57x/Makefile deleted file mode 100644 index 566366bf6e..0000000000 --- a/board/compulab/cl-som-am57x/Makefile +++ /dev/null @@ -1,17 +0,0 @@ -# -# Makefile -# -# (C) Copyright 2016 CompuLab, Ltd. <www.compulab.co.il> -# -# Author: Dmitry Lifshitz <lifshitz@compulab.co.il> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifdef CONFIG_SPL_BUILD -obj-y += spl.o mux.o -else -obj-y += cl-som-am57x.o mux.o -endif - -obj-$(CONFIG_DRIVER_TI_CPSW) += eth.o diff --git a/board/compulab/cl-som-am57x/cl-som-am57x.c b/board/compulab/cl-som-am57x/cl-som-am57x.c deleted file mode 100644 index fcba2a0e2a..0000000000 --- a/board/compulab/cl-som-am57x/cl-som-am57x.c +++ /dev/null @@ -1,78 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Board functions for CompuLab cl_som_am57x board - * - * (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/ - * - * Author: Dmitry Lifshitz <lifshitz@compulab.co.il> - */ - -#include <common.h> -#include <palmas.h> -#include <usb.h> -#include <asm/gpio.h> -#include <asm/arch/mmc_host_def.h> -#include <asm/arch/sys_proto.h> -#include "../common/common.h" -#include "../common/eeprom.h" -#include <asm/omap_common.h> - -DECLARE_GLOBAL_DATA_PTR; - -const struct omap_sysinfo sysinfo = { - "Board: CL-SOM-AM57x\n" -}; - -int board_init(void) -{ - /* Disable PMIC Powerhold feature, DEV_CTRL.DEV_ON = 1 */ - palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1); - - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - return 0; -} - -#ifdef CONFIG_MMC -#define SB_SOM_CD_GPIO 187 -#define SB_SOM_WP_GPIO 188 - -int board_mmc_init(bd_t *bis) -{ - int ret0, ret1; - - ret0 = omap_mmc_init(0, 0, 0, SB_SOM_CD_GPIO, SB_SOM_WP_GPIO); - if (ret0) - printf("cl-som-am57x: failed to initialize mmc0\n"); - - ret1 = omap_mmc_init(1, 0, 0, -1, -1); - if (ret1) - printf("cl-som-am57x: failed to initialize mmc1\n"); - - return ret0 && ret1; -} -#endif /* CONFIG_MMC */ - -int misc_init_r(void) -{ - cl_print_pcb_info(); - - return 0; -} - -u32 get_board_rev(void) -{ - return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS); -} - -int board_usb_init(int index, enum usb_init_type init) -{ - enable_usb_clocks(index); - return 0; -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - disable_usb_clocks(index); - return 0; -} diff --git a/board/compulab/cl-som-am57x/eth.c b/board/compulab/cl-som-am57x/eth.c deleted file mode 100644 index 3c59457341..0000000000 --- a/board/compulab/cl-som-am57x/eth.c +++ /dev/null @@ -1,198 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Ethernet specific code for CompuLab CL-SOM-AM57x module - * - * (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/ - * - * Author: Uri Mashiach <uri.mashiach@compulab.co.il> - */ - -#include <common.h> -#include <cpsw.h> -#include <environment.h> -#include <miiphy.h> -#include <asm/gpio.h> -#include <asm/arch/sys_proto.h> -#include "../common/eeprom.h" - -static void cpsw_control(int enabled) -{ - /* VTP can be added here */ -} - -static struct cpsw_slave_data cl_som_am57x_cpsw_slaves[] = { - { - .slave_reg_ofs = 0x208, - .sliver_reg_ofs = 0xd80, - .phy_addr = 0, - .phy_if = PHY_INTERFACE_MODE_RMII, - }, - { - .slave_reg_ofs = 0x308, - .sliver_reg_ofs = 0xdc0, - .phy_addr = 1, - .phy_if = PHY_INTERFACE_MODE_RMII, - - }, -}; - -static struct cpsw_platform_data cl_som_am57_cpsw_data = { - .mdio_base = CPSW_MDIO_BASE, - .cpsw_base = CPSW_BASE, - .mdio_div = 0xff, - .channels = 8, - .cpdma_reg_ofs = 0x800, - .slaves = 2, - .slave_data = cl_som_am57x_cpsw_slaves, - .ale_reg_ofs = 0xd00, - .ale_entries = 1024, - .host_port_reg_ofs = 0x108, - .hw_stats_reg_ofs = 0x900, - .bd_ram_ofs = 0x2000, - .mac_control = (1 << 5), - .control = cpsw_control, - .host_port_num = 0, - .version = CPSW_CTRL_VERSION_2, -}; - -/* - * cl_som_am57x_efuse_read_mac_addr() - read Ethernet port MAC address. - * The information is retrieved from the SOC's registers. - * @buff: read buffer. - * @port_num: port number. - */ -static void cl_som_am57x_efuse_read_mac_addr(uchar *buff, uint port_num) -{ - uint32_t mac_hi, mac_lo; - - if (port_num) { - mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); - mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); - } else { - mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); - mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); - } - - buff[0] = (mac_hi & 0xFF0000) >> 16; - buff[1] = (mac_hi & 0xFF00) >> 8; - buff[2] = mac_hi & 0xFF; - buff[3] = (mac_lo & 0xFF0000) >> 16; - buff[4] = (mac_lo & 0xFF00) >> 8; - buff[5] = mac_lo & 0xFF; -} - -/* - * cl_som_am57x_handle_mac_address() - set MAC address in the U-Boot - * environment. - * The address is retrieved retrieved from an EEPROM field or from the - * SOC's registers. - * @env_name: U-Boot environment name. - * @field_name: EEPROM field name. - * @port_num: SOC's port number. - */ -static int cl_som_am57x_handle_mac_address(char *env_name, uint port_num) -{ - int ret; - uint8_t enetaddr[6]; - - ret = eth_env_get_enetaddr(env_name, enetaddr); - if (ret) - return 0; - - ret = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS); - - if (ret || !is_valid_ethaddr(enetaddr)) - cl_som_am57x_efuse_read_mac_addr(enetaddr, port_num); - - if (!is_valid_ethaddr(enetaddr)) - return -1; - - ret = eth_env_set_enetaddr(env_name, enetaddr); - if (ret) - printf("cl-som-am57x: Failed to set Eth port %d MAC address\n", - port_num); - - return ret; -} - -#define CL_SOM_AM57X_PHY_ADDR2 0x01 -#define AR8033_PHY_DEBUG_ADDR_REG 0x1d -#define AR8033_PHY_DEBUG_DATA_REG 0x1e -#define AR8033_DEBUG_RGMII_RX_CLK_DLY_REG 0x00 -#define AR8033_DEBUG_RGMII_TX_CLK_DLY_REG 0x05 -#define AR8033_DEBUG_RGMII_RX_CLK_DLY_MASK (1 << 15) -#define AR8033_DEBUG_RGMII_TX_CLK_DLY_MASK (1 << 8) - -/* - * cl_som_am57x_rgmii_clk_delay() - Set RGMII clock delay. - * Enable RX delay, disable TX delay. - */ -static void cl_som_am57x_rgmii_clk_delay(void) -{ - uint16_t mii_reg_val; - const char *devname; - - devname = miiphy_get_current_dev(); - /* PHY 2 */ - miiphy_write(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_ADDR_REG, - AR8033_DEBUG_RGMII_RX_CLK_DLY_REG); - miiphy_read(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_DATA_REG, - &mii_reg_val); - mii_reg_val |= AR8033_DEBUG_RGMII_RX_CLK_DLY_MASK; - miiphy_write(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_DATA_REG, - mii_reg_val); - - miiphy_write(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_ADDR_REG, - AR8033_DEBUG_RGMII_TX_CLK_DLY_REG); - miiphy_read(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_DATA_REG, - &mii_reg_val); - mii_reg_val &= ~AR8033_DEBUG_RGMII_TX_CLK_DLY_MASK; - miiphy_write(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_DATA_REG, - mii_reg_val); -} - -#define CL_SOM_AM57X_GPIO_PHY1_RST 92 /* GPIO3_28 */ -#define CL_SOM_AM57X_RGMII_PORT1 1 - -int board_eth_init(bd_t *bis) -{ - int ret; - uint32_t ctrl_val; - char *cpsw_phy_envval; - int cpsw_act_phy = 1; - - /* SB-SOM-AM57x primary Eth (P21) is routed to RGMII1 */ - ret = cl_som_am57x_handle_mac_address("ethaddr", - CL_SOM_AM57X_RGMII_PORT1); - - if (ret) - return -1; - - /* Select RGMII for GMII1_SEL */ - ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); - ctrl_val |= 0x22; - writel(ctrl_val, (*ctrl)->control_core_control_io1); - mdelay(10); - - gpio_request(CL_SOM_AM57X_GPIO_PHY1_RST, "phy1_rst"); - gpio_direction_output(CL_SOM_AM57X_GPIO_PHY1_RST, 0); - mdelay(20); - - gpio_set_value(CL_SOM_AM57X_GPIO_PHY1_RST, 1); - mdelay(20); - - cpsw_phy_envval = env_get("cpsw_phy"); - if (cpsw_phy_envval != NULL) - cpsw_act_phy = simple_strtoul(cpsw_phy_envval, NULL, 0); - - cl_som_am57_cpsw_data.active_slave = cpsw_act_phy; - - ret = cpsw_register(&cl_som_am57_cpsw_data); - if (ret < 0) - printf("Error %d registering CPSW switch\n", ret); - - /* Set RGMII clock delay */ - cl_som_am57x_rgmii_clk_delay(); - - return ret; -} diff --git a/board/compulab/cl-som-am57x/mux.c b/board/compulab/cl-som-am57x/mux.c deleted file mode 100644 index 050f2aa3ef..0000000000 --- a/board/compulab/cl-som-am57x/mux.c +++ /dev/null @@ -1,123 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Pinmux configuration for CompuLab CL-SOM-AM57x board - * - * (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/ - * - * Author: Dmitry Lifshitz <lifshitz@compulab.co.il> - */ -#include <asm/arch/sys_proto.h> -#include <asm/arch/mux_dra7xx.h> - -/* Serial console */ -static const struct pad_conf_entry cl_som_am57x_padconf_console[] = { - {UART3_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* UART3_RXD */ - {UART3_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* UART3_TXD */ -}; - -/* PMIC I2C */ -static const struct pad_conf_entry cl_som_am57x_padconf_pmic[] = { - {MCASP1_ACLKR, (M10 | PIN_INPUT)}, /* MCASP1_ACLKR.I2C4_SDA */ - {MCASP1_FSR, (M10 | PIN_INPUT)}, /* MCASP1_FSR.I2C4_SCL */ -}; - -/* Green GPIO led */ -static const struct pad_conf_entry cl_som_am57x_padconf_green_led[] = { - {GPMC_A15, (M14 | PIN_OUTPUT_PULLDOWN)}, /* GPMC_A15.GPIO2_5 */ -}; - -/* MMC/SD Card */ -static const struct pad_conf_entry cl_som_am57x_padconf_sd_card[] = { - {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_CLK */ - {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_CMD */ - {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_DAT0 */ - {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_DAT1 */ - {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_DAT2 */ - {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_DAT3 */ - {MMC1_SDCD, (M14 | PIN_INPUT) }, /* MMC1_SDCD */ - {MMC1_SDWP, (M14 | PIN_INPUT) }, /* MMC1_SDWP */ -}; - -/* WiFi - must be in the safe mode on boot */ -static const struct pad_conf_entry cl_som_am57x_padconf_wifi[] = { - {UART1_CTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* UART1_CTSN */ - {UART1_RTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* UART1_RTSN */ - {UART2_RXD, (M15 | PIN_INPUT_PULLDOWN)}, /* UART2_RXD */ - {UART2_TXD, (M15 | PIN_INPUT_PULLDOWN)}, /* UART2_TXD */ - {UART2_CTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* UART2_CTSN */ - {UART2_RTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* UART2_RTSN */ -}; - -/* QSPI */ -static const struct pad_conf_entry cl_som_am57x_padconf_qspi[] = { - {GPMC_A13, (M1 | PIN_INPUT) }, /* GPMC_A13.QSPI1_RTCLK */ - {GPMC_A18, (M1 | PIN_INPUT) }, /* GPMC_A18.QSPI1_SCLK */ - {GPMC_A16, (M1 | PIN_INPUT) }, /* GPMC_A16.QSPI1_D0 */ - {GPMC_A17, (M1 | PIN_INPUT) }, /* GPMC_A17.QSPI1_D1 */ - {GPMC_CS2, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_CS2.QSPI1_CS0 */ -}; - -/* GPIO Expander I2C */ -static const struct pad_conf_entry cl_som_am57x_padconf_i2c_gpio[] = { - {MCASP1_AXR0, (M10 | PIN_INPUT)}, /* MCASP1_AXR0.I2C5_SDA */ - {MCASP1_AXR1, (M10 | PIN_INPUT)}, /* MCASP1_AXR1.I2C5_SCL */ -}; - -/* eMMC internal storage */ -static const struct pad_conf_entry cl_som_am57x_padconf_emmc[] = { - {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A19.MMC2_DAT4 */ - {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A20.MMC2_DAT5 */ - {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A21.MMC2_DAT6 */ - {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A22.MMC2_DAT7 */ - {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A23.MMC2_CLK */ - {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A24.MMC2_DAT0 */ - {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A25.MMC2_DAT1 */ - {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A26.MMC2_DAT2 */ - {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A27.MMC2_DAT3 */ - {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_CS1.MMC2_CMD */ -}; - -/* usb1_drvvbus */ -static const struct pad_conf_entry cl_som_am57x_padconf_usb[] = { - /* USB1_DRVVBUS.USB1_DRVVBUS */ - {USB1_DRVVBUS, (M0 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL) }, -}; - -/* Ethernet */ -static const struct pad_conf_entry cl_som_am57x_padconf_ethernet[] = { - /* MDIO bus */ - {VIN2A_D10, (M3 | PIN_OUTPUT_PULLUP) }, /* VIN2A_D10.MDIO_MCLK */ - {VIN2A_D11, (M3 | PIN_INPUT_PULLUP) }, /* VIN2A_D11.MDIO_D */ - /* EMAC Slave 1 at addr 0x1 - Default interface */ - {VIN2A_D12, (M3 | PIN_OUTPUT) }, /* VIN2A_D12.RGMII1_TXC */ - {VIN2A_D13, (M3 | PIN_OUTPUT) }, /* VIN2A_D13.RGMII1_TXCTL */ - {VIN2A_D14, (M3 | PIN_OUTPUT) }, /* VIN2A_D14.RGMII1_TXD3 */ - {VIN2A_D15, (M3 | PIN_OUTPUT) }, /* VIN2A_D15.RGMII1_TXD2 */ - {VIN2A_D16, (M3 | PIN_OUTPUT) }, /* VIN2A_D16.RGMII1_TXD1 */ - {VIN2A_D17, (M3 | PIN_OUTPUT) }, /* VIN2A_D17.RGMII1_TXD0 */ - {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D18.RGMII1_RXC */ - {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D19.RGMII1_RXCTL */ - {VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D20.RGMII1_RXD3 */ - {VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D21.RGMII1_RXD2 */ - {VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D22.RGMII1_RXD1 */ - {VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D23.RGMII1_RXD0 */ - /* Eth PHY1 reset GPIOs*/ - {VIN2A_CLK0, (M14 | PIN_OUTPUT_PULLDOWN)}, /* VIN2A_CLK0.GPIO3_28 */ -}; - -#define SET_MUX(mux_array) do_set_mux32((*ctrl)->control_padconf_core_base, \ - mux_array, ARRAY_SIZE(mux_array)) - -void set_muxconf_regs(void) -{ - SET_MUX(cl_som_am57x_padconf_console); - SET_MUX(cl_som_am57x_padconf_pmic); - SET_MUX(cl_som_am57x_padconf_green_led); - SET_MUX(cl_som_am57x_padconf_sd_card); - SET_MUX(cl_som_am57x_padconf_wifi); - SET_MUX(cl_som_am57x_padconf_qspi); - SET_MUX(cl_som_am57x_padconf_i2c_gpio); - SET_MUX(cl_som_am57x_padconf_emmc); - SET_MUX(cl_som_am57x_padconf_usb); - SET_MUX(cl_som_am57x_padconf_ethernet); -} diff --git a/board/compulab/cl-som-am57x/spl.c b/board/compulab/cl-som-am57x/spl.c deleted file mode 100644 index 0fb3d84a02..0000000000 --- a/board/compulab/cl-som-am57x/spl.c +++ /dev/null @@ -1,238 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * SPL data and initialization for CompuLab CL-SOM-AM57x board - * - * (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/ - * - * Author: Uri Mashiach <uri.mashiach@compulab.co.il> - */ - -#include <asm/emif.h> -#include <asm/omap_common.h> -#include <asm/arch/sys_proto.h> - -static const struct dmm_lisa_map_regs cl_som_am57x_lisa_regs = { - .dmm_lisa_map_3 = 0x80740300, - .is_ma_present = 0x1 -}; - -void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) -{ - /* Disable SDRAM controller EMIF2 for single core SOC */ - *dmm_lisa_regs = &cl_som_am57x_lisa_regs; - if (omap_revision() == DRA722_ES1_0) { - ((struct dmm_lisa_map_regs *) *dmm_lisa_regs)->dmm_lisa_map_3 = - 0x80640100; - } -} - -static const struct emif_regs cl_som_am57x_emif1_ddr3_532mhz_emif_regs = { - .sdram_config_init = 0x61852332, - .sdram_config = 0x61852332, - .sdram_config2 = 0x00000000, - .ref_ctrl = 0x000040f1, - .ref_ctrl_final = 0x00001040, - .sdram_tim1 = 0xeeef36f3, - .sdram_tim2 = 0x348f7fda, - .sdram_tim3 = 0x027f88a8, - .read_idle_ctrl = 0x00050000, - .zq_config = 0x1007190b, - .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0034400b, - .emif_ddr_phy_ctlr_1 = 0x0e34400b, - .emif_ddr_ext_phy_ctrl_1 = 0x04040100, - .emif_ddr_ext_phy_ctrl_2 = 0x00740074, - .emif_ddr_ext_phy_ctrl_3 = 0x00780078, - .emif_ddr_ext_phy_ctrl_4 = 0x007c007c, - .emif_ddr_ext_phy_ctrl_5 = 0x007b007b, - .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x80000000, - .emif_rd_wr_lvl_ctl = 0x00000000, - .emif_rd_wr_exec_thresh = 0x00000305 -}; - -/* Ext phy ctrl regs 1-35 */ -static const u32 cl_som_am57x_emif1_ddr3_ext_phy_ctrl_regs[] = { - 0x10040100, - 0x00740074, - 0x00780078, - 0x007c007c, - 0x007b007b, - 0x00800080, - 0x00360036, - 0x00340034, - 0x00360036, - 0x00350035, - 0x00350035, - - 0x01ff01ff, - 0x01ff01ff, - 0x01ff01ff, - 0x01ff01ff, - 0x01ff01ff, - - 0x00430043, - 0x003e003e, - 0x004a004a, - 0x00470047, - 0x00400040, - - 0x00000000, - 0x00600020, - 0x40011080, - 0x08102040, - - 0x00400040, - 0x00400040, - 0x00400040, - 0x00400040, - 0x00400040, - 0x0, - 0x0, - 0x0, - 0x0, - 0x0 -}; - -static const struct emif_regs cl_som_am57x_emif2_ddr3_532mhz_emif_regs = { - .sdram_config_init = 0x61852332, - .sdram_config = 0x61852332, - .sdram_config2 = 0x00000000, - .ref_ctrl = 0x000040f1, - .ref_ctrl_final = 0x00001040, - .sdram_tim1 = 0xeeef36f3, - .sdram_tim2 = 0x348f7fda, - .sdram_tim3 = 0x027f88a8, - .read_idle_ctrl = 0x00050000, - .zq_config = 0x1007190b, - .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0034400b, - .emif_ddr_phy_ctlr_1 = 0x0e34400b, - .emif_ddr_ext_phy_ctrl_1 = 0x04040100, - .emif_ddr_ext_phy_ctrl_2 = 0x00740074, - .emif_ddr_ext_phy_ctrl_3 = 0x00780078, - .emif_ddr_ext_phy_ctrl_4 = 0x007c007c, - .emif_ddr_ext_phy_ctrl_5 = 0x007b007b, - .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x80000000, - .emif_rd_wr_lvl_ctl = 0x00000000, - .emif_rd_wr_exec_thresh = 0x00000305 -}; - -static const u32 cl_som_am57x_emif2_ddr3_ext_phy_ctrl_regs[] = { - 0x10040100, - 0x00820082, - 0x008b008b, - 0x00800080, - 0x007e007e, - 0x00800080, - 0x00370037, - 0x00390039, - 0x00360036, - 0x00370037, - 0x00350035, - 0x01ff01ff, - 0x01ff01ff, - 0x01ff01ff, - 0x01ff01ff, - 0x01ff01ff, - 0x00540054, - 0x00540054, - 0x004e004e, - 0x004c004c, - 0x00400040, - - 0x00000000, - 0x00600020, - 0x40011080, - 0x08102040, - - 0x00400040, - 0x00400040, - 0x00400040, - 0x00400040, - 0x00400040, - 0x0, - 0x0, - 0x0, - 0x0, - 0x0 -}; - -static struct vcores_data cl_som_am57x_volts = { - .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM, - .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM, - .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .mpu.addr = TPS659038_REG_ADDR_SMPS12, - .mpu.pmic = &tps659038, - - .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM, - .eve.value[OPP_OD] = VDD_EVE_DRA7_OD, - .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH, - .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM, - .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD, - .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH, - .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .eve.addr = TPS659038_REG_ADDR_SMPS45, - .eve.pmic = &tps659038, - - .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, - .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, - .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, - .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, - .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, - .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, - .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .gpu.addr = TPS659038_REG_ADDR_SMPS6, - .gpu.pmic = &tps659038, - - .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM, - .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM, - .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .core.addr = TPS659038_REG_ADDR_SMPS7, - .core.pmic = &tps659038, - - .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM, - .iva.value[OPP_OD] = VDD_IVA_DRA7_OD, - .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH, - .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM, - .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD, - .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH, - .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .iva.addr = TPS659038_REG_ADDR_SMPS8, - .iva.pmic = &tps659038, -}; - -void hw_data_init(void) -{ - *prcm = &dra7xx_prcm; - *dplls_data = &dra7xx_dplls; - *omap_vcores = &cl_som_am57x_volts; - *ctrl = &dra7xx_ctrl; -} - -void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) -{ - switch (emif_nr) { - case 1: - *regs = &cl_som_am57x_emif1_ddr3_532mhz_emif_regs; - break; - case 2: - *regs = &cl_som_am57x_emif2_ddr3_532mhz_emif_regs; - break; - } -} - -void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size) -{ - switch (emif_nr) { - case 1: - *regs = cl_som_am57x_emif1_ddr3_ext_phy_ctrl_regs; - *size = ARRAY_SIZE(cl_som_am57x_emif1_ddr3_ext_phy_ctrl_regs); - break; - case 2: - *regs = cl_som_am57x_emif2_ddr3_ext_phy_ctrl_regs; - *size = ARRAY_SIZE(cl_som_am57x_emif2_ddr3_ext_phy_ctrl_regs); - break; - } -} diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index b0b29b3887..1bc26828bf 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -49,33 +49,6 @@ DECLARE_GLOBAL_DATA_PTR; #define CFG_MAC_ADDR_OFFSET (flash->size - SZ_64K) -#ifdef CONFIG_SPL_BUILD -#include <ns16550.h> -#include <dm/platform_data/spi_davinci.h> - -static const struct ns16550_platdata da850evm_serial = { - .base = DAVINCI_UART2_BASE, - .reg_shift = 2, - .clock = 150000000, - .fcr = UART_FCR_DEFVAL, -}; - -U_BOOT_DEVICE(da850evm_uart) = { - .name = "ns16550_serial", - .platdata = &da850evm_serial, -}; - -static const struct davinci_spi_platdata davinci_spi_data = { - .regs = (struct davinci_spi_regs *)0x01f0e000, - .num_cs = 4, -}; - -U_BOOT_DEVICE(davinci_spi) = { - .name = "davinci_spi", - .platdata = &davinci_spi_data, -}; -#endif - #ifdef CONFIG_MAC_ADDR_IN_SPIFLASH static int get_mac_addr(u8 *addr) { @@ -231,25 +204,6 @@ int misc_init_r(void) return 0; } -#ifndef CONFIG_DM_MMC -#ifdef CONFIG_MMC_DAVINCI -static struct davinci_mmc mmc_sd0 = { - .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE, - .host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */ - .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, - .version = MMC_CTLR_VERSION_2, -}; - -int board_mmc_init(bd_t *bis) -{ - mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID); - - /* Add slot-0 to mmc subsystem */ - return davinci_mmc_init(bis, &mmc_sd0); -} -#endif -#endif - static const struct pinmux_config gpio_pins[] = { #ifdef CONFIG_USE_NOR /* GP0[11] is required for NOR to work on Rev 3 EVMs */ diff --git a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds index 7b5fab7756..8f04911306 100644 --- a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds +++ b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds @@ -10,6 +10,9 @@ MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\ LENGTH = CONFIG_SPL_MAX_FOOTPRINT } +MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) ENTRY(_start) @@ -42,6 +45,15 @@ SECTIONS __rel_dyn_end = .; } >.sram + __image_copy_end = .; + + .end : + { + *(.__end) + } + + _image_binary_end = .; + .bss : { . = ALIGN(4); @@ -49,12 +61,5 @@ SECTIONS *(.bss*) . = ALIGN(4); __bss_end = .; - } >.sram - - __image_copy_end = .; - - .end : - { - *(.__end) - } + } >.sdram } diff --git a/board/freescale/imx8qxp_mek/imx8qxp_mek.c b/board/freescale/imx8qxp_mek/imx8qxp_mek.c index a4c587a390..63cd605b6a 100644 --- a/board/freescale/imx8qxp_mek/imx8qxp_mek.c +++ b/board/freescale/imx8qxp_mek/imx8qxp_mek.c @@ -112,7 +112,7 @@ void build_info(void) sc_misc_build_info(-1, &sc_build, &sc_commit); if (!sc_build) { printf("SCFW does not support build info\n"); - sc_commit = 0; /* Display 0 when the build info is not supported*/ + sc_commit = 0; /* Display 0 when the build info is not supported */ } printf("Build: SCFW %x\n", sc_commit); } diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index 079d302fbe..f42d2ceb79 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -10,6 +10,7 @@ #include <asm/arch/iomux.h> #include <asm/arch/mx6-pins.h> #include <linux/errno.h> +#include <linux/libfdt.h> #include <asm/gpio.h> #include <asm/mach-imx/mxc_i2c.h> #include <asm/mach-imx/iomux-v3.h> @@ -27,6 +28,7 @@ #include <i2c.h> #include <input.h> #include <pwm.h> +#include <version.h> #include <stdlib.h> #include "../common/ge_common.h" #include "../common/vpd_reader.h" @@ -44,10 +46,6 @@ static struct vpd_cache vpd; PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) @@ -57,9 +55,6 @@ static struct vpd_cache vpd; #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) -#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_ODE | PAD_CTL_SRE_FAST) @@ -110,58 +105,13 @@ static void setup_iomux_enet(void) imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); /* Reset AR8033 PHY */ + gpio_request(IMX_GPIO_NR(1, 28), "fec_rst"); gpio_direction_output(IMX_GPIO_NR(1, 28), 0); mdelay(10); gpio_set_value(IMX_GPIO_NR(1, 28), 1); mdelay(1); } -static iomux_v3_cfg_t const usdhc2_pads[] = { - MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - -static iomux_v3_cfg_t const usdhc4_pads[] = { - MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static iomux_v3_cfg_t const ecspi1_pads[] = { - MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - static struct i2c_pads_info i2c_pad_info1 = { .scl = { .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD, @@ -201,18 +151,6 @@ static struct i2c_pads_info i2c_pad_info3 = { } }; -#ifdef CONFIG_MXC_SPI -int board_spi_cs_gpio(unsigned bus, unsigned cs) -{ - return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1; -} - -static void setup_spi(void) -{ - imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); -} -#endif - static iomux_v3_cfg_t const pcie_pads[] = { MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), @@ -229,76 +167,6 @@ static void setup_iomux_uart(void) imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); } -#ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg usdhc_cfg[3] = { - {USDHC2_BASE_ADDR}, - {USDHC3_BASE_ADDR}, - {USDHC4_BASE_ADDR}, -}; - -#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) -#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 11) - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC2_BASE_ADDR: - ret = !gpio_get_value(USDHC2_CD_GPIO); - break; - case USDHC3_BASE_ADDR: - ret = 1; /* eMMC is always present */ - break; - case USDHC4_BASE_ADDR: - ret = !gpio_get_value(USDHC4_CD_GPIO); - break; - } - - return ret; -} - -int board_mmc_init(bd_t *bis) -{ - int ret; - int i; - - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - imx_iomux_v3_setup_multiple_pads( - usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); - gpio_direction_input(USDHC2_CD_GPIO); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - break; - case 1: - imx_iomux_v3_setup_multiple_pads( - usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - break; - case 2: - imx_iomux_v3_setup_multiple_pads( - usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); - gpio_direction_input(USDHC4_CD_GPIO); - usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - break; - default: - printf("Warning: you configured more USDHC controllers\n" - "(%d) then supported by the board (%d)\n", - i + 1, CONFIG_SYS_FSL_USDHC_NUM); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) - return ret; - } - - return 0; -} -#endif - static int mx6_rgmii_rework(struct phy_device *phydev) { /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */ @@ -533,8 +401,8 @@ static void setup_display_bx50v3(void) /* backlights off until needed */ imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads)); + gpio_request(LVDS_POWER_GP, "lvds_power"); gpio_direction_input(LVDS_POWER_GP); - gpio_direction_input(LVDS_BACKLIGHT_GP); } #endif /* CONFIG_VIDEO_IPUV3 */ @@ -687,20 +555,25 @@ int board_init(void) set_confidx(&vpd); } + gpio_request(SUS_S3_OUT, "sus_s3_out"); gpio_direction_output(SUS_S3_OUT, 1); + + gpio_request(WIFI_EN, "wifi_en"); gpio_direction_output(WIFI_EN, 1); + #if defined(CONFIG_VIDEO_IPUV3) if (is_b850v3()) setup_display_b850v3(); else setup_display_bx50v3(); + + gpio_request(LVDS_BACKLIGHT_GP, "lvds_backlight"); + gpio_direction_input(LVDS_BACKLIGHT_GP); #endif + /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; -#ifdef CONFIG_MXC_SPI - setup_spi(); -#endif return 0; } @@ -818,6 +691,15 @@ int checkboard(void) return 0; } +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + fdt_setprop(blob, 0, "ge,boot-ver", version_string, + strlen(version_string) + 1); + return 0; +} +#endif + static int do_backlight_enable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { #ifdef CONFIG_VIDEO_IPUV3 diff --git a/board/ge/mx53ppd/mx53ppd.c b/board/ge/mx53ppd/mx53ppd.c index 23bfe55541..5411e422ac 100644 --- a/board/ge/mx53ppd/mx53ppd.c +++ b/board/ge/mx53ppd/mx53ppd.c @@ -17,6 +17,7 @@ #include <asm/arch/iomux-mx53.h> #include <asm/arch/clock.h> #include <linux/errno.h> +#include <linux/libfdt.h> #include <asm/mach-imx/mxc_i2c.h> #include <asm/mach-imx/mx5_video.h> #include <environment.h> @@ -30,6 +31,7 @@ #include <fsl_pmic.h> #include <linux/fb.h> #include <ipu_pixfmt.h> +#include <version.h> #include <watchdog.h> #include "ppd_gpio.h" #include <stdlib.h> @@ -122,79 +124,6 @@ static void setup_iomux_fec(void) imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); } -#ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg esdhc_cfg[2] = { - {MMC_SDHC3_BASE_ADDR}, - {MMC_SDHC1_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - return 1; -} - -#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUS_100K_UP) -#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ - PAD_CTL_DSE_HIGH) - -int board_mmc_init(bd_t *bis) -{ - static const iomux_v3_cfg_t sd1_pads[] = { - NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD, - SD_CMD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL), - MX53_PAD_EIM_DA11__GPIO3_11, - }; - - static const iomux_v3_cfg_t sd2_pads[] = { - NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL), - MX53_PAD_EIM_DA13__GPIO3_13, - }; - - u32 index; - int ret; - - esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - - for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { - switch (index) { - case 0: - imx_iomux_v3_setup_multiple_pads(sd1_pads, - ARRAY_SIZE(sd1_pads)); - break; - case 1: - imx_iomux_v3_setup_multiple_pads(sd2_pads, - ARRAY_SIZE(sd2_pads)); - break; - default: - printf("Warning: you configured more ESDHC controller (%d) as supported by the board(2)\n", - CONFIG_SYS_FSL_ESDHC_NUM); - return -EINVAL; - } - ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]); - if (ret) - return ret; - } - - return 0; -} -#endif - #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) @@ -380,3 +309,12 @@ int checkboard(void) return 0; } + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + fdt_setprop(blob, 0, "ge,boot-ver", version_string, + strlen(version_string) + 1); + return 0; +} +#endif diff --git a/board/ge/mx53ppd/ppd_gpio.h b/board/ge/mx53ppd/ppd_gpio.h index e3b84c7a71..ba2d1baf37 100644 --- a/board/ge/mx53ppd/ppd_gpio.h +++ b/board/ge/mx53ppd/ppd_gpio.h @@ -36,6 +36,8 @@ static const iomux_v3_cfg_t ppd_pads[] = { MX53_PAD_KEY_COL2__GPIO4_10, MX53_PAD_KEY_ROW2__GPIO4_11, MX53_PAD_KEY_COL3__GPIO4_12, + + MX53_PAD_PATA_DATA7__GPIO2_7, /* BUFFERED_HOST_CONTROLLED_RESET_TO_DOCKING_CONNECTOR_N */ }; struct gpio_cfg { @@ -61,6 +63,7 @@ struct gpio_cfg { #define ECSPI1_CS1 IMX_GPIO_NR(4, 10) #define ECSPI1_CS2 IMX_GPIO_NR(4, 11) #define ECSPI1_CS3 IMX_GPIO_NR(4, 12) +#define BUFFERED_HOST_CONTROLLED_RESET_TO_DOCKING_CONNECTOR_N IMX_GPIO_NR(2, 7) static const struct gpio_cfg ppd_gpios[] = { /* FEC */ @@ -90,6 +93,7 @@ static const struct gpio_cfg ppd_gpios[] = { { ECSPI1_CS1, 1 }, { ECSPI1_CS2, 1 }, { ECSPI1_CS3, 1 }, + { BUFFERED_HOST_CONTROLLED_RESET_TO_DOCKING_CONNECTOR_N, 1 }, }; #endif /* __PPD_GPIO_H_ */ diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c index 6f728398c3..10031a4801 100644 --- a/board/logicpd/am3517evm/am3517evm.c +++ b/board/logicpd/am3517evm/am3517evm.c @@ -37,6 +37,15 @@ DECLARE_GLOBAL_DATA_PTR; #define CPGMACSS_SW_RST (1 << 1) #define PHY_GPIO 30 +#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SPL_OS_BOOT) +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + return serial_tstc() && serial_getc() == 'c'; +} +#endif +#endif /* * Routine: board_init diff --git a/board/maxbcm/maxbcm.c b/board/maxbcm/maxbcm.c index e8f8f7ba5b..395904f8c8 100644 --- a/board/maxbcm/maxbcm.c +++ b/board/maxbcm/maxbcm.c @@ -95,7 +95,7 @@ MV_DRAM_MODES *ddr3_get_static_ddr_mode(void) return &maxbcm_ddr_modes[0]; } -MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode) +MV_BIN_SERDES_CFG *board_serdes_cfg_get(void) { return &maxbcm_serdes_cfg[0]; } diff --git a/board/mscc/jr2/jr2.c b/board/mscc/jr2/jr2.c index 58a4a04162..6e5ef4c97f 100644 --- a/board/mscc/jr2/jr2.c +++ b/board/mscc/jr2/jr2.c @@ -6,6 +6,7 @@ #include <common.h> #include <asm/io.h> #include <led.h> +#include <miiphy.h> enum { BOARD_TYPE_PCB110 = 0xAABBCE00, @@ -64,6 +65,28 @@ static void vcoreiii_gpio_set_alternate(int gpio, int mode) } } +int board_phy_config(struct phy_device *phydev) +{ + if (gd->board_type == BOARD_TYPE_PCB110 || + gd->board_type == BOARD_TYPE_PCB112) { + phy_write(phydev, 0, 31, 0x10); + phy_write(phydev, 0, 18, 0x80F0); + while (phy_read(phydev, 0, 18) & 0x8000) + ; + phy_write(phydev, 0, 31, 0); + } + if (gd->board_type == BOARD_TYPE_PCB111) { + phy_write(phydev, 0, 31, 0x10); + phy_write(phydev, 0, 18, 0x80A0); + while (phy_read(phydev, 0, 18) & 0x8000) + ; + phy_write(phydev, 0, 14, 0x800); + phy_write(phydev, 0, 31, 0); + } + + return 0; +} + void board_debug_uart_init(void) { /* too early for the pinctrl driver, so configure the UART pins here */ diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c index f988af2abc..c30df5df9d 100644 --- a/board/phytec/pcm052/pcm052.c +++ b/board/phytec/pcm052/pcm052.c @@ -1,5 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* + * (C) Copyright 2018 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de. + * * Copyright 2013 Freescale Semiconductor, Inc. */ @@ -10,79 +13,12 @@ #include <asm/arch/ddrmc-vf610.h> #include <asm/arch/crm_regs.h> #include <asm/arch/clock.h> -#include <mmc.h> -#include <fsl_esdhc.h> +#include <led.h> +#include <environment.h> #include <miiphy.h> -#include <netdev.h> -#include <i2c.h> DECLARE_GLOBAL_DATA_PTR; -/* - * Default DDR pad settings in arch/arm/include/asm/arch-vf610/iomux-vf610.h - * do not match our settings. Let us (re)define our own settings here. - */ - -#define PCM052_VF610_DDR_PAD_CTRL PAD_CTL_DSE_20ohm -#define PCM052_VF610_DDR_PAD_CTRL_1 (PAD_CTL_DSE_20ohm | \ - PAD_CTL_INPUT_DIFFERENTIAL) -#define PCM052_VF610_DDR_RESET_PAD_CTL (PAD_CTL_DSE_150ohm | \ - PAD_CTL_PUS_100K_UP | \ - PAD_CTL_INPUT_DIFFERENTIAL) - -enum { - PCM052_VF610_PAD_DDR_RESETB = IOMUX_PAD(0x021c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_RESET_PAD_CTL), - PCM052_VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A12__DDR_A_12 = IOMUX_PAD(0x022c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A11__DDR_A_11 = IOMUX_PAD(0x0230, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A10__DDR_A_10 = IOMUX_PAD(0x0234, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A9__DDR_A_9 = IOMUX_PAD(0x0238, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A8__DDR_A_8 = IOMUX_PAD(0x023c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A7__DDR_A_7 = IOMUX_PAD(0x0240, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A6__DDR_A_6 = IOMUX_PAD(0x0244, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A5__DDR_A_5 = IOMUX_PAD(0x0248, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A4__DDR_A_4 = IOMUX_PAD(0x024c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A3__DDR_A_3 = IOMUX_PAD(0x0250, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A2__DDR_A_2 = IOMUX_PAD(0x0254, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A1__DDR_A_1 = IOMUX_PAD(0x0258, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A0__DDR_A_0 = IOMUX_PAD(0x025c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_BA2__DDR_BA_2 = IOMUX_PAD(0x0260, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_BA1__DDR_BA_1 = IOMUX_PAD(0x0264, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_BA0__DDR_BA_0 = IOMUX_PAD(0x0268, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_CAS__DDR_CAS_B = IOMUX_PAD(0x026c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_CKE__DDR_CKE_0 = IOMUX_PAD(0x0270, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_CLK__DDR_CLK_0 = IOMUX_PAD(0x0274, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1), - PCM052_VF610_PAD_DDR_CS__DDR_CS_B_0 = IOMUX_PAD(0x0278, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D15__DDR_D_15 = IOMUX_PAD(0x027c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D14__DDR_D_14 = IOMUX_PAD(0x0280, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D13__DDR_D_13 = IOMUX_PAD(0x0284, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D12__DDR_D_12 = IOMUX_PAD(0x0288, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D11__DDR_D_11 = IOMUX_PAD(0x028c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D10__DDR_D_10 = IOMUX_PAD(0x0290, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D9__DDR_D_9 = IOMUX_PAD(0x0294, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D8__DDR_D_8 = IOMUX_PAD(0x0298, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D7__DDR_D_7 = IOMUX_PAD(0x029c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D6__DDR_D_6 = IOMUX_PAD(0x02a0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D5__DDR_D_5 = IOMUX_PAD(0x02a4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D4__DDR_D_4 = IOMUX_PAD(0x02a8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D3__DDR_D_3 = IOMUX_PAD(0x02ac, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D2__DDR_D_2 = IOMUX_PAD(0x02b0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D1__DDR_D_1 = IOMUX_PAD(0x02b4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D0__DDR_D_0 = IOMUX_PAD(0x02b8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_DQM1__DDR_DQM_1 = IOMUX_PAD(0x02bc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_DQM0__DDR_DQM_0 = IOMUX_PAD(0x02c0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_DQS1__DDR_DQS_1 = IOMUX_PAD(0x02c4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1), - PCM052_VF610_PAD_DDR_DQS0__DDR_DQS_0 = IOMUX_PAD(0x02c8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1), - PCM052_VF610_PAD_DDR_RAS__DDR_RAS_B = IOMUX_PAD(0x02cc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_WE__DDR_WE_B = IOMUX_PAD(0x02d0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_ODT1__DDR_ODT_0 = IOMUX_PAD(0x02d4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_ODT0__DDR_ODT_1 = IOMUX_PAD(0x02d8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 = IOMUX_PAD(0x02dc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0 = IOMUX_PAD(0x02e0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), -}; - static struct ddrmc_cr_setting pcm052_cr_settings[] = { /* not in the datasheets, but in the original code */ { 0x00002000, 105 }, @@ -151,59 +87,6 @@ static struct ddrmc_phy_setting pcm052_phy_settings[] = { int dram_init(void) { - static const iomux_v3_cfg_t pcm052_pads[] = { - PCM052_VF610_PAD_DDR_A15__DDR_A_15, - PCM052_VF610_PAD_DDR_A14__DDR_A_14, - PCM052_VF610_PAD_DDR_A13__DDR_A_13, - PCM052_VF610_PAD_DDR_A12__DDR_A_12, - PCM052_VF610_PAD_DDR_A11__DDR_A_11, - PCM052_VF610_PAD_DDR_A10__DDR_A_10, - PCM052_VF610_PAD_DDR_A9__DDR_A_9, - PCM052_VF610_PAD_DDR_A8__DDR_A_8, - PCM052_VF610_PAD_DDR_A7__DDR_A_7, - PCM052_VF610_PAD_DDR_A6__DDR_A_6, - PCM052_VF610_PAD_DDR_A5__DDR_A_5, - PCM052_VF610_PAD_DDR_A4__DDR_A_4, - PCM052_VF610_PAD_DDR_A3__DDR_A_3, - PCM052_VF610_PAD_DDR_A2__DDR_A_2, - PCM052_VF610_PAD_DDR_A1__DDR_A_1, - PCM052_VF610_PAD_DDR_A0__DDR_A_0, - PCM052_VF610_PAD_DDR_BA2__DDR_BA_2, - PCM052_VF610_PAD_DDR_BA1__DDR_BA_1, - PCM052_VF610_PAD_DDR_BA0__DDR_BA_0, - PCM052_VF610_PAD_DDR_CAS__DDR_CAS_B, - PCM052_VF610_PAD_DDR_CKE__DDR_CKE_0, - PCM052_VF610_PAD_DDR_CLK__DDR_CLK_0, - PCM052_VF610_PAD_DDR_CS__DDR_CS_B_0, - PCM052_VF610_PAD_DDR_D15__DDR_D_15, - PCM052_VF610_PAD_DDR_D14__DDR_D_14, - PCM052_VF610_PAD_DDR_D13__DDR_D_13, - PCM052_VF610_PAD_DDR_D12__DDR_D_12, - PCM052_VF610_PAD_DDR_D11__DDR_D_11, - PCM052_VF610_PAD_DDR_D10__DDR_D_10, - PCM052_VF610_PAD_DDR_D9__DDR_D_9, - PCM052_VF610_PAD_DDR_D8__DDR_D_8, - PCM052_VF610_PAD_DDR_D7__DDR_D_7, - PCM052_VF610_PAD_DDR_D6__DDR_D_6, - PCM052_VF610_PAD_DDR_D5__DDR_D_5, - PCM052_VF610_PAD_DDR_D4__DDR_D_4, - PCM052_VF610_PAD_DDR_D3__DDR_D_3, - PCM052_VF610_PAD_DDR_D2__DDR_D_2, - PCM052_VF610_PAD_DDR_D1__DDR_D_1, - PCM052_VF610_PAD_DDR_D0__DDR_D_0, - PCM052_VF610_PAD_DDR_DQM1__DDR_DQM_1, - PCM052_VF610_PAD_DDR_DQM0__DDR_DQM_0, - PCM052_VF610_PAD_DDR_DQS1__DDR_DQS_1, - PCM052_VF610_PAD_DDR_DQS0__DDR_DQS_0, - PCM052_VF610_PAD_DDR_RAS__DDR_RAS_B, - PCM052_VF610_PAD_DDR_WE__DDR_WE_B, - PCM052_VF610_PAD_DDR_ODT1__DDR_ODT_0, - PCM052_VF610_PAD_DDR_ODT0__DDR_ODT_1, - PCM052_VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1, - PCM052_VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0, - PCM052_VF610_PAD_DDR_RESETB, - }; - #if defined(CONFIG_TARGET_PCM052) static const struct ddr3_jedec_timings pcm052_ddr_timings = { @@ -320,8 +203,6 @@ int dram_init(void) #endif - imx_iomux_v3_setup_multiple_pads(pcm052_pads, ARRAY_SIZE(pcm052_pads)); - ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings, pcm052_phy_settings, 1, row_diff); @@ -330,135 +211,6 @@ int dram_init(void) return 0; } -static void setup_iomux_uart(void) -{ - static const iomux_v3_cfg_t uart1_pads[] = { - NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, VF610_UART_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, VF610_UART_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); -} - -#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ - PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE) - -static void setup_iomux_enet(void) -{ - static const iomux_v3_cfg_t enet0_pads[] = { - NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads)); -} - -/* - * I2C2 is the only I2C used, on pads PTA22/PTA23. - */ - -static void setup_iomux_i2c(void) -{ - static const iomux_v3_cfg_t i2c_pads[] = { - VF610_PAD_PTA22__I2C2_SCL, - VF610_PAD_PTA23__I2C2_SDA, - }; - - imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads)); -} - -#ifdef CONFIG_NAND_VF610_NFC -static void setup_iomux_nfc(void) -{ - static const iomux_v3_cfg_t nfc_pads[] = { - VF610_PAD_PTD31__NF_IO15, - VF610_PAD_PTD30__NF_IO14, - VF610_PAD_PTD29__NF_IO13, - VF610_PAD_PTD28__NF_IO12, - VF610_PAD_PTD27__NF_IO11, - VF610_PAD_PTD26__NF_IO10, - VF610_PAD_PTD25__NF_IO9, - VF610_PAD_PTD24__NF_IO8, - VF610_PAD_PTD23__NF_IO7, - VF610_PAD_PTD22__NF_IO6, - VF610_PAD_PTD21__NF_IO5, - VF610_PAD_PTD20__NF_IO4, - VF610_PAD_PTD19__NF_IO3, - VF610_PAD_PTD18__NF_IO2, - VF610_PAD_PTD17__NF_IO1, - VF610_PAD_PTD16__NF_IO0, - VF610_PAD_PTB24__NF_WE_B, - VF610_PAD_PTB25__NF_CE0_B, - VF610_PAD_PTB27__NF_RE_B, - VF610_PAD_PTC26__NF_RB_B, - VF610_PAD_PTC27__NF_ALE, - VF610_PAD_PTC28__NF_CLE - }; - - imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); -} -#endif - -static void setup_iomux_qspi(void) -{ - static const iomux_v3_cfg_t qspi0_pads[] = { - VF610_PAD_PTD0__QSPI0_A_QSCK, - VF610_PAD_PTD1__QSPI0_A_CS0, - VF610_PAD_PTD2__QSPI0_A_DATA3, - VF610_PAD_PTD3__QSPI0_A_DATA2, - VF610_PAD_PTD4__QSPI0_A_DATA1, - VF610_PAD_PTD5__QSPI0_A_DATA0, - VF610_PAD_PTD7__QSPI0_B_QSCK, - VF610_PAD_PTD8__QSPI0_B_CS0, - VF610_PAD_PTD9__QSPI0_B_DATA3, - VF610_PAD_PTD10__QSPI0_B_DATA2, - VF610_PAD_PTD11__QSPI0_B_DATA1, - VF610_PAD_PTD12__QSPI0_B_DATA0, - }; - - imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads)); -} - -#define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \ - PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE) - -struct fsl_esdhc_cfg esdhc_cfg[1] = { - {ESDHC1_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - /* eSDHC1 is always present */ - return 1; -} - -int board_mmc_init(bd_t *bis) -{ - static const iomux_v3_cfg_t esdhc1_pads[] = { - NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL), - }; - - esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - - imx_iomux_v3_setup_multiple_pads( - esdhc1_pads, ARRAY_SIZE(esdhc1_pads)); - - return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); -} - static void clock_init(void) { struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; @@ -485,7 +237,7 @@ static void clock_init(void) clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK); clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, - CCM_CCGR10_NFC_CTRL_MASK | CCM_CCGR10_I2C2_CTRL_MASK); + CCM_CCGR10_NFC_CTRL_MASK); clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN, ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT); @@ -531,23 +283,10 @@ static void mscm_init(void) writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]); } -int board_phy_config(struct phy_device *phydev) -{ - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - int board_early_init_f(void) { clock_init(); mscm_init(); - setup_iomux_uart(); - setup_iomux_enet(); - setup_iomux_i2c(); - setup_iomux_qspi(); - setup_iomux_nfc(); return 0; } @@ -571,47 +310,102 @@ int board_init(void) return 0; } -int checkboard(void) +#ifdef CONFIG_TARGET_BK4R1 +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) { - puts("Board: PCM-052\n"); + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[4]; + struct fuse_bank4_regs *fuse = + (struct fuse_bank4_regs *)bank->fuse_regs; + u32 value; - return 0; + /* + * BK4 has different layout of stored MAC address + * than one used in imx_get_mac_from_fuse() @ generic.c + */ + + switch (dev_id) { + case 0: + value = readl(&fuse->mac_addr1); + + mac[0] = value >> 8; + mac[1] = value; + + value = readl(&fuse->mac_addr0); + mac[2] = value >> 24; + mac[3] = value >> 16; + mac[4] = value >> 8; + mac[5] = value; + break; + case 1: + value = readl(&fuse->mac_addr2); + + mac[0] = value >> 24; + mac[1] = value >> 16; + mac[2] = value >> 8; + mac[3] = value; + + value = readl(&fuse->mac_addr1); + mac[4] = value >> 24; + mac[5] = value >> 16; + break; + } } -static int do_m4go(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) +int board_late_init(void) { - ulong addr; + struct src *psrc = (struct src *)SRC_BASE_ADDR; + u32 reg; - /* Consume 'm4go' */ - argc--; argv++; + if (IS_ENABLED(CONFIG_LED)) + led_default_state(); /* - * Parse provided address - default to load_addr in case not provided. + * BK4r1 handle emergency/service SD card boot + * Checking the SBMR1 register BOOTCFG1 byte: + * NAND: + * bit [2] - NAND data width - 16 + * bit [5] - NAND fast boot + * bit [7] = 1 - NAND as a source of booting + * SD card (0x64): + * bit [4] = 0 - SD card source + * bit [6] = 1 - SD/MMC source */ - if (argc) - addr = simple_strtoul(argv[0], NULL, 16); - else - addr = load_addr; + reg = readl(&psrc->sbmr1); + if ((reg & SRC_SBMR1_BOOTCFG1_SDMMC) && + !(reg & SRC_SBMR1_BOOTCFG1_MMC)) { + printf("------ SD card boot -------\n"); + set_default_env("!LVFBootloader", 0); + env_set("bootcmd", + "run prepare_install_bk4r1_envs; run install_bk4r1rs"); + } - /* - * Write boot address in PERSISTENT_ENTRY1[31:0] aka SRC_GPR2[31:0] - */ - writel(addr + 0x401, 0x4006E028); + return 0; +} - /* - * Start secondary processor by enabling its clock - */ - writel(0x15a5a, 0x4006B08C); +/** + * KSZ8081 + */ +#define MII_KSZ8081_REFERENCE_CLOCK_SELECT 0x1f +#define RMII_50MHz_CLOCK 0x8180 - return 1; +int board_phy_config(struct phy_device *phydev) +{ + /* Set 50 MHz reference clock */ + phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8081_REFERENCE_CLOCK_SELECT, + RMII_50MHz_CLOCK); + + return genphy_config(phydev); } +#endif /* CONFIG_TARGET_BK4R1 */ -U_BOOT_CMD( - m4go, 2 /* one arg max */, 1 /* repeatable */, do_m4go, - "start the secondary Cortex-M4 from scatter file image", - "[<addr>]\n" - " - start secondary Cortex-M4 core using a scatter file image\n" - "The argument needs to be a scatter file\n" -); +int checkboard(void) +{ +#ifdef CONFIG_TARGET_BK4R1 + puts("Board: BK4r1 (L333)\n"); +#else + puts("Board: PCM-052\n"); +#endif + return 0; +} diff --git a/board/qca/ap152/Kconfig b/board/qca/ap152/Kconfig new file mode 100644 index 0000000000..f6ad498e85 --- /dev/null +++ b/board/qca/ap152/Kconfig @@ -0,0 +1,15 @@ +if TARGET_AP152 + +config SYS_VENDOR + default "qca" + +config SYS_BOARD + default "ap152" + +config SYS_CONFIG_NAME + default "ap152" + +config SYS_TEXT_BASE + default 0x9f000000 + +endif diff --git a/board/qca/ap152/MAINTAINERS b/board/qca/ap152/MAINTAINERS new file mode 100644 index 0000000000..785ec2766d --- /dev/null +++ b/board/qca/ap152/MAINTAINERS @@ -0,0 +1,6 @@ +AP152 BOARD +M: Rosy Song <rosysong@rosinson.com> +S: Maintained +F: board/qca/ap152/ +F: include/configs/ap152.h +F: configs/ap152_defconfig diff --git a/board/qca/ap152/Makefile b/board/qca/ap152/Makefile new file mode 100644 index 0000000000..4270afa129 --- /dev/null +++ b/board/qca/ap152/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y = ap152.o diff --git a/board/qca/ap152/ap152.c b/board/qca/ap152/ap152.c new file mode 100644 index 0000000000..30cd56563b --- /dev/null +++ b/board/qca/ap152/ap152.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Rosy Song <rosysong@rosinson.com> + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <mach/ar71xx_regs.h> +#include <mach/ddr.h> +#include <mach/ath79.h> +#include <debug_uart.h> + +#define RST_RESET_RTC_RESET_LSB 27 +#define RST_RESET_RTC_RESET_MASK 0x08000000 +#define RST_RESET_RTC_RESET_SET(x) \ + (((x) << RST_RESET_RTC_RESET_LSB) & RST_RESET_RTC_RESET_MASK) + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ + void __iomem *regs; + u32 val; + + regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE, + MAP_NOCACHE); + + /* UART : RX18, TX22 done + * GPIO18 as input, GPIO22 as output + */ + val = readl(regs + AR71XX_GPIO_REG_OE); + val |= QCA956X_GPIO(18); + val &= ~QCA956X_GPIO(22); + writel(val, regs + AR71XX_GPIO_REG_OE); + + /* + * Enable GPIO22 as UART0_SOUT + */ + val = readl(regs + QCA956X_GPIO_REG_OUT_FUNC5); + val &= ~QCA956X_GPIO_MUX_MASK(16); + val |= QCA956X_GPIO_OUT_MUX_UART0_SOUT << 16; + writel(val, regs + QCA956X_GPIO_REG_OUT_FUNC5); + + /* + * Enable GPIO18 as UART0_SIN + */ + val = readl(regs + QCA956X_GPIO_REG_IN_ENABLE0); + val &= ~QCA956X_GPIO_MUX_MASK(8); + val |= QCA956X_GPIO_IN_MUX_UART0_SIN << 8; + writel(val, regs + QCA956X_GPIO_REG_IN_ENABLE0); + + /* + * Enable GPIO22 output + */ + val = readl(regs + AR71XX_GPIO_REG_OUT); + val |= QCA956X_GPIO(22); + writel(val, regs + AR71XX_GPIO_REG_OUT); +} +#endif + +int board_early_init_f(void) +{ + u32 reg; + void __iomem *rst_regs = map_physmem(AR71XX_RESET_BASE, + AR71XX_RESET_SIZE, MAP_NOCACHE); + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + /* CPU:775, DDR:650, AHB:258 */ + qca956x_pll_init(); + qca956x_ddr_init(); +#endif + + /* Take WMAC out of reset */ + reg = readl(rst_regs + QCA956X_RESET_REG_RESET_MODULE); + reg &= (~RST_RESET_RTC_RESET_SET(1)); + writel(reg, rst_regs + QCA956X_RESET_REG_RESET_MODULE); + + ath79_eth_reset(); + return 0; +} diff --git a/board/renesas/rcar-common/common.c b/board/renesas/rcar-common/common.c index 1129f4bf0c..1ce6e2eac1 100644 --- a/board/renesas/rcar-common/common.c +++ b/board/renesas/rcar-common/common.c @@ -8,57 +8,4 @@ */ #include <common.h> -#include <asm/io.h> -#include <asm/arch/sys_proto.h> #include <asm/arch/rmobile.h> -#include <asm/arch/rcar-mstp.h> - -#define TSTR0 0x04 -#define TSTR0_STR0 0x01 - -static struct mstp_ctl mstptbl[] = { - { SMSTPCR0, MSTP0_BITS, CONFIG_SMSTP0_ENA, - RMSTPCR0, MSTP0_BITS, CONFIG_RMSTP0_ENA }, - { SMSTPCR1, MSTP1_BITS, CONFIG_SMSTP1_ENA, - RMSTPCR1, MSTP1_BITS, CONFIG_RMSTP1_ENA }, - { SMSTPCR2, MSTP2_BITS, CONFIG_SMSTP2_ENA, - RMSTPCR2, MSTP2_BITS, CONFIG_RMSTP2_ENA }, - { SMSTPCR3, MSTP3_BITS, CONFIG_SMSTP3_ENA, - RMSTPCR3, MSTP3_BITS, CONFIG_RMSTP3_ENA }, - { SMSTPCR4, MSTP4_BITS, CONFIG_SMSTP4_ENA, - RMSTPCR4, MSTP4_BITS, CONFIG_RMSTP4_ENA }, - { SMSTPCR5, MSTP5_BITS, CONFIG_SMSTP5_ENA, - RMSTPCR5, MSTP5_BITS, CONFIG_RMSTP5_ENA }, -#ifdef CONFIG_RCAR_GEN3 - { SMSTPCR6, MSTP6_BITS, CONFIG_SMSTP6_ENA, - RMSTPCR6, MSTP6_BITS, CONFIG_RMSTP6_ENA }, -#endif - { SMSTPCR7, MSTP7_BITS, CONFIG_SMSTP7_ENA, - RMSTPCR7, MSTP7_BITS, CONFIG_RMSTP7_ENA }, - { SMSTPCR8, MSTP8_BITS, CONFIG_SMSTP8_ENA, - RMSTPCR8, MSTP8_BITS, CONFIG_RMSTP8_ENA }, - { SMSTPCR9, MSTP9_BITS, CONFIG_SMSTP9_ENA, - RMSTPCR9, MSTP9_BITS, CONFIG_RMSTP9_ENA }, - { SMSTPCR10, MSTP10_BITS, CONFIG_SMSTP10_ENA, - RMSTPCR10, MSTP10_BITS, CONFIG_RMSTP10_ENA }, - { SMSTPCR11, MSTP11_BITS, CONFIG_SMSTP1_ENA, - RMSTPCR11, MSTP11_BITS, CONFIG_RMSTP11_ENA }, -}; - -void arch_preboot_os(void) -{ - int i; - - /* stop TMU0 */ - mstp_clrbits_le32(TMU_BASE + TSTR0, TMU_BASE + TSTR0, TSTR0_STR0); - - /* Stop module clock */ - for (i = 0; i < ARRAY_SIZE(mstptbl); i++) { - mstp_setclrbits_le32((uintptr_t)mstptbl[i].s_addr, - mstptbl[i].s_dis, - mstptbl[i].s_ena); - mstp_setclrbits_le32((uintptr_t)mstptbl[i].r_addr, - mstptbl[i].r_dis, - mstptbl[i].r_ena); - } -} diff --git a/board/renesas/ulcb/MAINTAINERS b/board/renesas/ulcb/MAINTAINERS index e7cdc5217f..8549f543f4 100644 --- a/board/renesas/ulcb/MAINTAINERS +++ b/board/renesas/ulcb/MAINTAINERS @@ -5,3 +5,4 @@ F: board/renesas/ulcb/ F: include/configs/ulcb.h F: configs/r8a7795_ulcb_defconfig F: configs/r8a7796_ulcb_defconfig +F: configs/r8a77965_ulcb_defconfig diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c index 81d6f8f6f2..9785107e56 100644 --- a/board/renesas/ulcb/ulcb.c +++ b/board/renesas/ulcb/ulcb.c @@ -97,6 +97,10 @@ int board_fit_config_name_match(const char *name) !strcmp(name, "r8a7796-m3ulcb-u-boot")) return 0; + if ((cpu_type == RMOBILE_CPU_TYPE_R8A77965) && + !strcmp(name, "r8a77965-m3nulcb-u-boot")) + return 0; + return -1; } #endif diff --git a/board/solidrun/clearfog/README b/board/solidrun/clearfog/README index a7bc0d4e23..0b0e98de90 100644 --- a/board/solidrun/clearfog/README +++ b/board/solidrun/clearfog/README @@ -17,6 +17,29 @@ $ sudo dd if=u-boot-spl.kwb of=/dev/sdX bs=512 seek=1 Please use the correct device node for your setup instead of "/dev/sdX" here! +Install U-Boot on eMMC: +----------------------- + +The ROM loads the bootloader from eMMC first boot partition at offset 0. This +is unlike load from SD card that is at offset 512. As a result, the offset of +the main U-Boot image on the eMMC boot partition changes. Set +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR to 0x140 for SPL to load U-Boot from +the correct location. + +To make SPL load the main U-Boot image from the eMMC boot partition enable +eMMC boot acknowledgement and boot partition with the following U-Boot +command: + + mmc partconf 0 1 1 0 + +Install U-Boot on eMMC boot partition from Linux running on Clearfog: + + echo 0 > /sys/block/mmcblk0boot0/force_ro + dd if=u-boot-spl.kwb of=/dev/mmcblk0boot0 + +Note that the SD card is not accessible when the Clearfog SOM has eMMC. +Consider initial boot from UART (see below). + Boot selection: --------------- diff --git a/board/st/stm32mp1/MAINTAINERS b/board/st/stm32mp1/MAINTAINERS index 48d8fd2c3f..0a2eddbe03 100644 --- a/board/st/stm32mp1/MAINTAINERS +++ b/board/st/stm32mp1/MAINTAINERS @@ -2,7 +2,8 @@ STM32MP1 BOARD M: Patrick Delaunay <patrick.delaunay@st.com> L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers) S: Maintained +F: arch/arm/dts/stm32mp157* F: board/st/stm32mp1 -F: include/configs/stm32mp1.h F: configs/stm32mp15_basic_defconfig -F: arch/arm/dts/stm32mp157* +F: configs/stm32mp15_trusted_defconfig +F: include/configs/stm32mp1.h diff --git a/board/st/stm32mp1/README b/board/st/stm32mp1/README index 174e6db148..1cd3534ae4 100644 --- a/board/st/stm32mp1/README +++ b/board/st/stm32mp1/README @@ -28,14 +28,15 @@ Everything is supported in Linux but U-Boot is limited to: And the necessary drivers 1. I2C -2. STPMU1 -2. STPMU1 (PMIC and regulator) +2. STPMIC1 (PMIC and regulator) 3. Clock, Reset, Sysreset 4. Fuse Currently the following boards are supported: + stm32mp157c-ev1 + stm32mp157c-ed1 ++ stm32mp157a-dk1 ++ stm32mp157c-dk2 3. Boot Sequences ================= @@ -45,15 +46,22 @@ BootRom => FSBL in SYSRAM => SSBL in DDR => OS (Linux Kernel) with FSBL = First Stage Bootloader SSBL = Second Stage Bootloader -One boot configuration is supported: +2 boot configurations are supported: - The "Basic" boot chain (defconfig_file : stm32mp15_basic_defconfig) +1) The "Trusted" boot chain (defconfig_file : stm32mp15_trusted_defconfig) + BootRom => FSBL = Trusted Firmware-A (TF-A) => SSBL = U-Boot + TF-A performs a full initialization of Secure peripherals and installs a + secure monitor. + U-Boot is running in normal world and uses TF-A monitor + to access to secure resources + +2) The "Basic" boot chain (defconfig_file : stm32mp15_basic_defconfig) BootRom => FSBL = U-Boot SPL => SSBL = U-Boot SPL has limited security initialisation U-Boot is running in secure mode and provide a secure monitor to the kernel with only PSCI support (Power State Coordination Interface defined by ARM) -All the STM32MP1 board supported by U-Boot use the same generic board +All the STM32MP1 boards supported by U-Boot use the same generic board stm32mp1 which support all the bootable devices. Each board is configurated only with the associated device tree. @@ -64,12 +72,18 @@ Each board is configurated only with the associated device tree. You need to select the appropriate device tree for your board, the supported device trees for stm32mp157 are: -+ ev1: eval board with pmic stpmu1 (ev1 = mother board + daughter ed1) ++ ev1: eval board with pmic stpmic1 (ev1 = mother board + daughter ed1) dts: stm32mp157c-ev1 -+ ed1: daughter board with pmic stpmu1 ++ ed1: daughter board with pmic stpmic1 dts: stm32mp157c-ed1 ++ dk1: Discovery board + dts: stm32mp157a-dk1 + ++ dk2: Discovery board = dk1 with a BT/WiFI combo and a DSI panel + dts: stm32mp157c-dk2 + 5. Build Procedure ================== @@ -90,12 +104,14 @@ the supported device trees for stm32mp157 are: # export KBUILD_OUTPUT=/path/to/output for example: use one output directory for each configuration + # export KBUILD_OUTPUT=stm32mp15_trusted # export KBUILD_OUTPUT=stm32mp15_basic -4. Configure the U-Boot: +4. Configure U-Boot: # make <defconfig_file> + - For trusted boot mode : "stm32mp15_trusted_defconfig" - For basic boot mode: "stm32mp15_basic_defconfig" 5. Configure the device-tree and build the U-Boot image: @@ -104,16 +120,26 @@ the supported device trees for stm32mp157 are: example: - basic boot on ev1 + a) trusted boot on ev1 + # export KBUILD_OUTPUT=stm32mp15_trusted + # make stm32mp15_trusted_defconfig + # make DEVICE_TREE=stm32mp157c-ev1 all + + b) basic boot on ev1 # export KBUILD_OUTPUT=stm32mp15_basic # make stm32mp15_basic_defconfig # make DEVICE_TREE=stm32mp157c-ev1 all - basic boot on ed1 + c) basic boot on ed1 # export KBUILD_OUTPUT=stm32mp15_basic # make stm32mp15_basic_defconfig # make DEVICE_TREE=stm32mp157c-ed1 all + d) basic boot on dk2 + # export KBUILD_OUTPUT=stm32mp15_basic + # make stm32mp15_basic_defconfig + # make DEVICE_TREE=stm32mp157c-dk2 all + 6. Output files BootRom and TF-A expect binaries with STM32 image header @@ -122,6 +148,11 @@ the supported device trees for stm32mp157 are: So in the output directory (selected by KBUILD_OUTPUT), you can found the needed files: + a) For Trusted boot + + FSBL = tf-a.stm32 (provided by TF-A compilation) + + SSBL = u-boot.stm32 + + b) For Basic boot + FSBL = spl/u-boot-spl.stm32 + SSBL = u-boot.img @@ -135,13 +166,22 @@ You can select the boot mode, on the board ed1 with the switch SW1 ----------------------------------- Reserved 0 0 0 NOR 0 0 1 - SD-Card 1 1 1 SD-Card 1 0 1 eMMC 0 1 0 NAND 0 1 1 Recovery 1 1 0 Recovery 0 0 0 +- on board DK1/DK2 with the switch SW1 : BOOT0, BOOT2 + (BOOT1 forced to 0, NOR not supported) + + -------------------------- + Boot Mode BOOT2 BOOT0 + -------------------------- + Reserved 1 0 + SD-Card 1 1 + Recovery 0 0 + Recovery is a boot from serial link (UART/USB) and it is used with STM32CubeProgrammer tool to load executable in RAM and to update the flash devices available on the board (NOR/NAND/eMMC/SDCARD). @@ -158,14 +198,14 @@ The minimal requirements for STMP32MP1 boot up to U-Boot are: - one ssbl partition for U-Boot Then the minimal GPT partition is: - ----- ------- --------- ------------- - | Num | Name | Size | Content | - ----- ------- -------- -------------- + ----- ------- --------- -------------- + | Num | Name | Size | Content | + ----- ------- -------- --------------- | 1 | fsbl1 | 256 KiB | TF-A or SPL | | 2 | fsbl2 | 256 KiB | TF-A or SPL | - | 3 | ssbl | enought | U-Boot | - | * | - | - | Boot/Rootfs| - ----- ------- --------- ------------- + | 3 | ssbl | enought | U-Boot | + | * | - | - | Boot/Rootfs | + ----- ------- --------- -------------- (*) add bootable partition for extlinux.conf following Generic Distribution @@ -189,7 +229,7 @@ for example: with gpt table with 128 entries you can add other partitions for kernel one partition rootfs for example: - -n 3:5154: -c 4:rootfs + -n 4:5154: -c 4:rootfs \ c) copy the FSBL (2 times) and SSBL file on the correct partition. in this example in partition 1 to 3 @@ -199,6 +239,11 @@ for example: with gpt table with 128 entries # dd if=u-boot-spl.stm32 of=/dev/mmcblk0p2 # dd if=u-boot.img of=/dev/mmcblk0p3 + for trusted boot mode : + # dd if=tf-a.stm32 of=/dev/mmcblk0p1 + # dd if=tf-a.stm32 of=/dev/mmcblk0p2 + # dd if=u-boot.stm32 of=/dev/mmcblk0p3 + To boot from SDCard, select BootPinMode = 1 1 1 and reset. 8. Prepare eMMC @@ -208,7 +253,7 @@ You can use U-Boot to copy binary in eMMC. In the next example, you need to boot from SDCARD and the images (u-boot-spl.stm32, u-boot.img) are presents on SDCARD (mmc 0) in ext4 partition 4 (bootfs). -To boot from SDCard, select BootPinMode = 1 1 1 and reset. +To boot from SDCard, select BootPinMode = 1 0 1 and reset. Then you update the eMMC with the next U-Boot command : @@ -227,7 +272,7 @@ b) copy SPL on eMMC on firts boot partition # mmc write ${fileaddr} 0 200 # mmc partconf 1 1 1 0 -b) copy U-Boot in first GPT partition of eMMC +c) copy U-Boot in first GPT partition of eMMC # ext4load mmc 0:4 0xC0000000 u-boot.img # mmc dev 1 diff --git a/board/st/stm32mp1/board.c b/board/st/stm32mp1/board.c index 5f31ea99f5..5c1acca20d 100644 --- a/board/st/stm32mp1/board.c +++ b/board/st/stm32mp1/board.c @@ -8,7 +8,7 @@ #include <asm/io.h> #include <asm/arch/ddr.h> #include <power/pmic.h> -#include <power/stpmu1.h> +#include <power/stpmic1.h> #ifdef CONFIG_DEBUG_UART_BOARD_INIT void board_debug_uart_init(void) @@ -37,64 +37,65 @@ void board_debug_uart_init(void) } #endif -#ifdef CONFIG_PMIC_STPMU1 +#ifdef CONFIG_PMIC_STPMIC1 int board_ddr_power_init(void) { struct udevice *dev; int ret; ret = uclass_get_device_by_driver(UCLASS_PMIC, - DM_GET_DRIVER(pmic_stpmu1), &dev); + DM_GET_DRIVER(pmic_stpmic1), &dev); if (ret) /* No PMIC on board */ return 0; - /* Set LDO3 to sync mode */ - ret = pmic_reg_read(dev, STPMU1_LDOX_CTRL_REG(STPMU1_LDO3)); + /* VTT = Set LDO3 to sync mode */ + ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3)); if (ret < 0) return ret; - ret &= ~STPMU1_LDO3_MODE; - ret &= ~STPMU1_LDO12356_OUTPUT_MASK; - ret |= STPMU1_LDO3_DDR_SEL << STPMU1_LDO12356_OUTPUT_SHIFT; + ret &= ~STPMIC1_LDO3_MODE; + ret &= ~STPMIC1_LDO12356_VOUT_MASK; + ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL); - ret = pmic_reg_write(dev, STPMU1_LDOX_CTRL_REG(STPMU1_LDO3), + ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3), ret); if (ret < 0) return ret; - /* Set BUCK2 to 1.35V */ + /* VDD_DDR = Set BUCK2 to 1.35V */ ret = pmic_clrsetbits(dev, - STPMU1_BUCKX_CTRL_REG(STPMU1_BUCK2), - STPMU1_BUCK_OUTPUT_MASK, - STPMU1_BUCK2_1350000V); + STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2), + STPMIC1_BUCK_VOUT_MASK, + STPMIC1_BUCK2_1350000V); if (ret < 0) return ret; - /* Enable BUCK2 and VREF */ + /* Enable VDD_DDR = BUCK2 */ ret = pmic_clrsetbits(dev, - STPMU1_BUCKX_CTRL_REG(STPMU1_BUCK2), - STPMU1_BUCK_EN, STPMU1_BUCK_EN); + STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2), + STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA); if (ret < 0) return ret; - mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS); + mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS); - ret = pmic_clrsetbits(dev, STPMU1_VREF_CTRL_REG, - STPMU1_VREF_EN, STPMU1_VREF_EN); + /* Enable VREF */ + ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR, + STPMIC1_VREF_ENA, STPMIC1_VREF_ENA); if (ret < 0) return ret; - mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS); + mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS); /* Enable LDO3 */ ret = pmic_clrsetbits(dev, - STPMU1_LDOX_CTRL_REG(STPMU1_LDO3), - STPMU1_LDO_EN, STPMU1_LDO_EN); + STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3), + STPMIC1_LDO_ENA, STPMIC1_LDO_ENA); if (ret < 0) return ret; - mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS); + mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS); return 0; } diff --git a/board/st/stm32mp1/spl.c b/board/st/stm32mp1/spl.c index f3db0d6385..a7844f244b 100644 --- a/board/st/stm32mp1/spl.c +++ b/board/st/stm32mp1/spl.c @@ -11,22 +11,22 @@ #include <asm/io.h> #include <post.h> #include <power/pmic.h> -#include <power/stpmu1.h> +#include <power/stpmic1.h> #include <asm/arch/ddr.h> void spl_board_init(void) { /* Keep vdd on during the reset cycle */ -#if defined(CONFIG_PMIC_STPMU1) && defined(CONFIG_SPL_POWER_SUPPORT) +#if defined(CONFIG_PMIC_STPMIC1) && defined(CONFIG_SPL_POWER_SUPPORT) struct udevice *dev; int ret; ret = uclass_get_device_by_driver(UCLASS_PMIC, - DM_GET_DRIVER(pmic_stpmu1), &dev); + DM_GET_DRIVER(pmic_stpmic1), &dev); if (!ret) pmic_clrsetbits(dev, - STPMU1_MASK_RESET_BUCK, - STPMU1_MASK_RESET_BUCK3, - STPMU1_MASK_RESET_BUCK3); + STPMIC1_BUCKS_MRST_CR, + STPMIC1_MRST_BUCK(STPMIC1_BUCK3), + STPMIC1_MRST_BUCK(STPMIC1_BUCK3)); #endif } diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 54feca0ecf..76917b022e 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -2,197 +2,505 @@ /* * Copyright (C) 2018, STMicroelectronics - All Rights Reserved */ -#include <config.h> #include <common.h> -#include <led.h> +#include <adc.h> +#include <config.h> #include <clk.h> #include <dm.h> +#include <g_dnl.h> #include <generic-phy.h> +#include <i2c.h> +#include <led.h> +#include <misc.h> #include <phy.h> #include <reset.h> +#include <syscon.h> #include <usb.h> -#include <asm/arch/stm32.h> #include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/stm32.h> #include <power/regulator.h> #include <usb/dwc2_udc.h> +/* SYSCFG registers */ +#define SYSCFG_BOOTR 0x00 +#define SYSCFG_PMCSETR 0x04 +#define SYSCFG_IOCTRLSETR 0x18 +#define SYSCFG_ICNR 0x1C +#define SYSCFG_CMPCR 0x20 +#define SYSCFG_CMPENSETR 0x24 +#define SYSCFG_PMCCLRR 0x44 + +#define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0) +#define SYSCFG_BOOTR_BOOTPD_SHIFT 4 + +#define SYSCFG_IOCTRLSETR_HSLVEN_TRACE BIT(0) +#define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI BIT(1) +#define SYSCFG_IOCTRLSETR_HSLVEN_ETH BIT(2) +#define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC BIT(3) +#define SYSCFG_IOCTRLSETR_HSLVEN_SPI BIT(4) + +#define SYSCFG_CMPCR_SW_CTRL BIT(1) +#define SYSCFG_CMPCR_READY BIT(8) + +#define SYSCFG_CMPENSETR_MPU_EN BIT(0) + +#define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16) +#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17) + +#define SYSCFG_PMCSETR_ETH_SELMII BIT(20) + +#define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21) +#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII (0 << 21) +#define SYSCFG_PMCSETR_ETH_SEL_RGMII (1 << 21) +#define SYSCFG_PMCSETR_ETH_SEL_RMII (4 << 21) + /* * Get a global data pointer */ DECLARE_GLOBAL_DATA_PTR; -#define STM32MP_GUSBCFG 0x40002407 +#define USB_WARNING_LOW_THRESHOLD_UV 660000 +#define USB_START_LOW_THRESHOLD_UV 1230000 +#define USB_START_HIGH_THRESHOLD_UV 2100000 + +int checkboard(void) +{ + int ret; + char *mode; + u32 otp; + struct udevice *dev; + const char *fdt_compat; + int fdt_compat_len; + + if (IS_ENABLED(CONFIG_STM32MP1_TRUSTED)) + mode = "trusted"; + else + mode = "basic"; + + printf("Board: stm32mp1 in %s mode", mode); + fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible", + &fdt_compat_len); + if (fdt_compat && fdt_compat_len) + printf(" (%s)", fdt_compat); + puts("\n"); + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(stm32mp_bsec), + &dev); + + if (!ret) + ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_BOARD), + &otp, sizeof(otp)); + if (!ret && otp) { + printf("Board: MB%04x Var%d Rev.%c-%02d\n", + otp >> 16, + (otp >> 12) & 0xF, + ((otp >> 8) & 0xF) - 1 + 'A', + otp & 0xF); + } + + return 0; +} + +static void board_key_check(void) +{ +#if defined(CONFIG_FASTBOOT) || defined(CONFIG_CMD_STM32PROG) + ofnode node; + struct gpio_desc gpio; + enum forced_boot_mode boot_mode = BOOT_NORMAL; + + node = ofnode_path("/config"); + if (!ofnode_valid(node)) { + debug("%s: no /config node?\n", __func__); + return; + } +#ifdef CONFIG_FASTBOOT + if (gpio_request_by_name_nodev(node, "st,fastboot-gpios", 0, + &gpio, GPIOD_IS_IN)) { + debug("%s: could not find a /config/st,fastboot-gpios\n", + __func__); + } else { + if (dm_gpio_get_value(&gpio)) { + puts("Fastboot key pressed, "); + boot_mode = BOOT_FASTBOOT; + } + + dm_gpio_free(NULL, &gpio); + } +#endif +#ifdef CONFIG_CMD_STM32PROG + if (gpio_request_by_name_nodev(node, "st,stm32prog-gpios", 0, + &gpio, GPIOD_IS_IN)) { + debug("%s: could not find a /config/st,stm32prog-gpios\n", + __func__); + } else { + if (dm_gpio_get_value(&gpio)) { + puts("STM32Programmer key pressed, "); + boot_mode = BOOT_STM32PROG; + } + dm_gpio_free(NULL, &gpio); + } +#endif + + if (boot_mode != BOOT_NORMAL) { + puts("entering download mode...\n"); + clrsetbits_le32(TAMP_BOOT_CONTEXT, + TAMP_BOOT_FORCED_MASK, + boot_mode); + } +#endif +} -#define STM32MP_GGPIO 0x38 -#define STM32MP_GGPIO_VBUS_SENSING BIT(21) +#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) -static struct dwc2_plat_otg_data stm32mp_otg_data = { - .usb_gusbcfg = STM32MP_GUSBCFG, -}; +/* STMicroelectronics STUSB1600 Type-C controller */ +#define STUSB1600_CC_CONNECTION_STATUS 0x0E -static struct reset_ctl usbotg_reset; +/* STUSB1600_CC_CONNECTION_STATUS bitfields */ +#define STUSB1600_CC_ATTACH BIT(0) -int board_usb_init(int index, enum usb_init_type init) +static int stusb1600_init(struct udevice **dev_stusb1600) { - struct fdtdec_phandle_args args; - struct udevice *dev; - const void *blob = gd->fdt_blob; - struct clk clk; - struct phy phy; - int node; - int phy_provider; + ofnode node; + struct udevice *dev, *bus; int ret; + u32 chip_addr; - /* find the usb otg node */ - node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2"); - if (node < 0) { - debug("Not found usb_otg device\n"); - return -ENODEV; - } + *dev_stusb1600 = NULL; - if (!fdtdec_get_is_enabled(blob, node)) { - debug("stm32 usbotg is disabled in the device tree\n"); + /* if node stusb1600 is present, means DK1 or DK2 board */ + node = ofnode_by_compatible(ofnode_null(), "st,stusb1600"); + if (!ofnode_valid(node)) return -ENODEV; - } - /* Enable clock */ - ret = fdtdec_parse_phandle_with_args(blob, node, "clocks", - "#clock-cells", 0, 0, &args); + ret = ofnode_read_u32(node, "reg", &chip_addr); + if (ret) + return -EINVAL; + + ret = uclass_get_device_by_ofnode(UCLASS_I2C, ofnode_get_parent(node), + &bus); if (ret) { - debug("usbotg has no clocks defined in the device tree\n"); - return ret; + printf("bus for stusb1600 not found\n"); + return -ENODEV; } - ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, &dev); - if (ret) - return ret; + ret = dm_i2c_probe(bus, chip_addr, 0, &dev); + if (!ret) + *dev_stusb1600 = dev; - if (args.args_count != 1) { - debug("Can't find clock ID in the device tree\n"); - return -ENODATA; - } + return ret; +} + +static int stusb1600_cable_connected(struct udevice *dev) +{ + u8 status; + + if (dm_i2c_read(dev, STUSB1600_CC_CONNECTION_STATUS, &status, 1)) + return 0; - clk.dev = dev; - clk.id = args.args[0]; + return status & STUSB1600_CC_ATTACH; +} + +#include <usb/dwc2_udc.h> +int g_dnl_board_usb_cable_connected(void) +{ + struct udevice *stusb1600; + struct udevice *dwc2_udc_otg; + int ret; + + if (!stusb1600_init(&stusb1600)) + return stusb1600_cable_connected(stusb1600); + + ret = uclass_get_device_by_driver(UCLASS_USB_GADGET_GENERIC, + DM_GET_DRIVER(dwc2_udc_otg), + &dwc2_udc_otg); + if (!ret) + debug("dwc2_udc_otg init failed\n"); + + return dwc2_udc_B_session_valid(dwc2_udc_otg); +} +#endif /* CONFIG_USB_GADGET */ + +static int get_led(struct udevice **dev, char *led_string) +{ + char *led_name; + int ret; - ret = clk_enable(&clk); + led_name = fdtdec_get_config_string(gd->fdt_blob, led_string); + if (!led_name) { + pr_debug("%s: could not find %s config string\n", + __func__, led_string); + return -ENOENT; + } + ret = led_get_by_label(led_name, dev); if (ret) { - debug("Failed to enable usbotg clock\n"); + debug("%s: get=%d\n", __func__, ret); return ret; } - /* Reset */ - ret = fdtdec_parse_phandle_with_args(blob, node, "resets", - "#reset-cells", 0, 0, &args); - if (ret) { - debug("usbotg has no resets defined in the device tree\n"); - goto clk_err; + return 0; +} + +static int setup_led(enum led_state_t cmd) +{ + struct udevice *dev; + int ret; + + ret = get_led(&dev, "u-boot,boot-led"); + if (ret) + return ret; + + ret = led_set_state(dev, cmd); + return ret; +} + +static int board_check_usb_power(void) +{ + struct ofnode_phandle_args adc_args; + struct udevice *adc; + struct udevice *led; + ofnode node; + unsigned int raw; + int max_uV = 0; + int ret, uV, adc_count; + u8 i, nb_blink; + + node = ofnode_path("/config"); + if (!ofnode_valid(node)) { + debug("%s: no /config node?\n", __func__); + return -ENOENT; } - ret = uclass_get_device_by_of_offset(UCLASS_RESET, args.node, &dev); - if (ret || args.args_count != 1) - goto clk_err; + /* + * Retrieve the ADC channels devices and get measurement + * for each of them + */ + adc_count = ofnode_count_phandle_with_args(node, "st,adc_usb_pd", + "#io-channel-cells"); + if (adc_count < 0) { + if (adc_count == -ENOENT) + return 0; - usbotg_reset.dev = dev; - usbotg_reset.id = args.args[0]; + pr_err("%s: can't find adc channel (%d)\n", __func__, + adc_count); - reset_assert(&usbotg_reset); - udelay(2); - reset_deassert(&usbotg_reset); + return adc_count; + } - /* Get USB PHY */ - ret = fdtdec_parse_phandle_with_args(blob, node, "phys", - "#phy-cells", 0, 0, &args); - if (!ret) { - phy_provider = fdt_parent_offset(blob, args.node); - ret = uclass_get_device_by_of_offset(UCLASS_PHY, - phy_provider, &dev); - if (ret) - goto clk_err; + for (i = 0; i < adc_count; i++) { + if (ofnode_parse_phandle_with_args(node, "st,adc_usb_pd", + "#io-channel-cells", 0, i, + &adc_args)) { + pr_debug("%s: can't find /config/st,adc_usb_pd\n", + __func__); + return 0; + } - phy.dev = dev; - phy.id = fdtdec_get_uint(blob, args.node, "reg", -1); + ret = uclass_get_device_by_ofnode(UCLASS_ADC, adc_args.node, + &adc); - ret = generic_phy_power_on(&phy); if (ret) { - debug("unable to power on the phy\n"); - goto clk_err; + pr_err("%s: Can't get adc device(%d)\n", __func__, + ret); + return ret; } - ret = generic_phy_init(&phy); + ret = adc_channel_single_shot(adc->name, adc_args.args[0], + &raw); if (ret) { - debug("failed to init usb phy\n"); - goto phy_power_err; + pr_err("%s: single shot failed for %s[%d]!\n", + __func__, adc->name, adc_args.args[0]); + return ret; } - } - - /* Parse and store data needed for gadget */ - stm32mp_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); - if (stm32mp_otg_data.regs_otg == FDT_ADDR_T_NONE) { - debug("usbotg: can't get base address\n"); - ret = -ENODATA; - goto phy_init_err; - } - - stm32mp_otg_data.rx_fifo_sz = fdtdec_get_int(blob, node, - "g-rx-fifo-size", 0); - stm32mp_otg_data.np_tx_fifo_sz = fdtdec_get_int(blob, node, - "g-np-tx-fifo-size", 0); - stm32mp_otg_data.tx_fifo_sz = fdtdec_get_int(blob, node, - "g-tx-fifo-size", 0); - /* Enable voltage level detector */ - if (!(fdtdec_parse_phandle_with_args(blob, node, "usb33d-supply", - NULL, 0, 0, &args))) { - if (!uclass_get_device_by_of_offset(UCLASS_REGULATOR, - args.node, &dev)) { - ret = regulator_set_enable(dev, true); - if (ret) { - debug("Failed to enable usb33d\n"); - goto phy_init_err; - } + /* Convert to uV */ + if (!adc_raw_to_uV(adc, raw, &uV)) { + if (uV > max_uV) + max_uV = uV; + pr_debug("%s: %s[%02d] = %u, %d uV\n", __func__, + adc->name, adc_args.args[0], raw, uV); + } else { + pr_err("%s: Can't get uV value for %s[%d]\n", + __func__, adc->name, adc_args.args[0]); } } - /* Enable vbus sensing */ - setbits_le32(stm32mp_otg_data.regs_otg + STM32MP_GGPIO, - STM32MP_GGPIO_VBUS_SENSING); - return dwc2_udc_probe(&stm32mp_otg_data); + /* + * If highest value is inside 1.23 Volts and 2.10 Volts, that means + * board is plugged on an USB-C 3A power supply and boot process can + * continue. + */ + if (max_uV > USB_START_LOW_THRESHOLD_UV && + max_uV < USB_START_HIGH_THRESHOLD_UV) + return 0; + + /* Display warning message and make u-boot,error-led blinking */ + pr_err("\n*******************************************\n"); + + if (max_uV < USB_WARNING_LOW_THRESHOLD_UV) { + pr_err("* WARNING 500mA power supply detected *\n"); + nb_blink = 2; + } else { + pr_err("* WARNING 1.5A power supply detected *\n"); + nb_blink = 3; + } -phy_init_err: - generic_phy_exit(&phy); + pr_err("* Current too low, use a 3A power supply! *\n"); + pr_err("*******************************************\n\n"); -phy_power_err: - generic_phy_power_off(&phy); + ret = get_led(&led, "u-boot,error-led"); + if (ret) + return ret; -clk_err: - clk_disable(&clk); + for (i = 0; i < nb_blink * 2; i++) { + led_set_state(led, LEDST_TOGGLE); + mdelay(125); + } + led_set_state(led, LEDST_ON); - return ret; + return 0; } -int board_usb_cleanup(int index, enum usb_init_type init) +static void sysconf_init(void) { - /* Reset usbotg */ - reset_assert(&usbotg_reset); - udelay(2); - reset_deassert(&usbotg_reset); +#ifndef CONFIG_STM32MP1_TRUSTED + u8 *syscfg; +#ifdef CONFIG_DM_REGULATOR + struct udevice *pwr_dev; + struct udevice *pwr_reg; + struct udevice *dev; + int ret; + u32 otp = 0; +#endif + u32 bootr; + + syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG); + + /* interconnect update : select master using the port 1 */ + /* LTDC = AXI_M9 */ + /* GPU = AXI_M8 */ + /* today information is hardcoded in U-Boot */ + writel(BIT(9), syscfg + SYSCFG_ICNR); + + /* disable Pull-Down for boot pin connected to VDD */ + bootr = readl(syscfg + SYSCFG_BOOTR); + bootr &= ~(SYSCFG_BOOTR_BOOT_MASK << SYSCFG_BOOTR_BOOTPD_SHIFT); + bootr |= (bootr & SYSCFG_BOOTR_BOOT_MASK) << SYSCFG_BOOTR_BOOTPD_SHIFT; + writel(bootr, syscfg + SYSCFG_BOOTR); + +#ifdef CONFIG_DM_REGULATOR + /* High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI + * and TRACE. Needed above ~50MHz and conditioned by AFMUX selection. + * The customer will have to disable this for low frequencies + * or if AFMUX is selected but the function not used, typically for + * TRACE. Otherwise, impact on power consumption. + * + * WARNING: + * enabling High Speed mode while VDD>2.7V + * with the OTP product_below_2v5 (OTP 18, BIT 13) + * erroneously set to 1 can damage the IC! + * => U-Boot set the register only if VDD < 2.7V (in DT) + * but this value need to be consistent with board design + */ + ret = syscon_get_by_driver_data(STM32MP_SYSCON_PWR, &pwr_dev); + if (!ret) { + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(stm32mp_bsec), + &dev); + if (ret) { + pr_err("Can't find stm32mp_bsec driver\n"); + return; + } - return 0; -} + ret = misc_read(dev, STM32_BSEC_SHADOW(18), &otp, 4); + if (!ret) + otp = otp & BIT(13); + + /* get VDD = pwr-supply */ + ret = device_get_supply_regulator(pwr_dev, "pwr-supply", + &pwr_reg); + + /* check if VDD is Low Voltage */ + if (!ret) { + if (regulator_get_value(pwr_reg) < 2700000) { + writel(SYSCFG_IOCTRLSETR_HSLVEN_TRACE | + SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI | + SYSCFG_IOCTRLSETR_HSLVEN_ETH | + SYSCFG_IOCTRLSETR_HSLVEN_SDMMC | + SYSCFG_IOCTRLSETR_HSLVEN_SPI, + syscfg + SYSCFG_IOCTRLSETR); + + if (!otp) + pr_err("product_below_2v5=0: HSLVEN protected by HW\n"); + } else { + if (otp) + pr_err("product_below_2v5=1: HSLVEN update is destructive, no update as VDD>2.7V\n"); + } + } else { + debug("VDD unknown"); + } + } +#endif -int board_late_init(void) -{ - return 0; + /* activate automatic I/O compensation + * warning: need to ensure CSI enabled and ready in clock driver + */ + writel(SYSCFG_CMPENSETR_MPU_EN, syscfg + SYSCFG_CMPENSETR); + + while (!(readl(syscfg + SYSCFG_CMPCR) & SYSCFG_CMPCR_READY)) + ; + clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL); +#endif } /* board dependent setup after realloc */ int board_init(void) { + struct udevice *dev; + /* address of boot parameters */ gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100; + /* probe all PINCTRL for hog */ + for (uclass_first_device(UCLASS_PINCTRL, &dev); + dev; + uclass_next_device(&dev)) { + pr_debug("probe pincontrol = %s\n", dev->name); + } + + board_key_check(); + + sysconf_init(); + if (IS_ENABLED(CONFIG_LED)) led_default_state(); return 0; } + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + const void *fdt_compat; + int fdt_compat_len; + + fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible", + &fdt_compat_len); + if (fdt_compat && fdt_compat_len) { + if (strncmp(fdt_compat, "st,", 3) != 0) + env_set("board_name", fdt_compat); + else + env_set("board_name", fdt_compat + 3); + } +#endif + + /* for DK1/DK2 boards */ + board_check_usb_power(); + + return 0; +} + +void board_quiesce_devices(void) +{ + setup_led(LEDST_OFF); +} diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 8e2f90fc68..338f374e56 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -341,6 +341,11 @@ M: FUKAUMI Naoki <naobsd@gmail.com> S: Maintained F: configs/Nintendo_NES_Classic_Edition_defconfig +OCEANIC 5205 5INMFD BOARD +M: Jagan Teki <jagan@amarulasolutions.com> +S: Maintained +F: configs/oceanic_5205_5inmfd_defconfig + OLIMEX A20-SOM204 BOARD M: Stefan Mavrodiev <stefan@olimex.com> S: Maintained @@ -348,7 +353,7 @@ F: configs/A20-Olimex-SOM204-EVB_defconfig F: configs/A20-Olimex-SOM204-EVB-eMMC_defconfig ORANGEPI LITE2 BOARD -M: Jagan Teki <jagan@openedev.com> +M: Jagan Teki <jagan@amarulasolutions.com> S: Maintained F: configs/orangepi_lite2_defconfig diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile index 4d6258d932..c4e13f8c38 100644 --- a/board/sunxi/Makefile +++ b/board/sunxi/Makefile @@ -8,9 +8,6 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. obj-y += board.o obj-$(CONFIG_SUN7I_GMAC) += gmac.o -ifndef CONFIG_SPL_BUILD -obj-$(CONFIG_SUNXI_AHCI) += ahci.o -endif obj-$(CONFIG_MACH_SUN4I) += dram_sun4i_auto.o obj-$(CONFIG_MACH_SUN5I) += dram_sun5i_auto.o obj-$(CONFIG_MACH_SUN7I) += dram_sun5i_auto.o diff --git a/board/sunxi/ahci.c b/board/sunxi/ahci.c deleted file mode 100644 index a79b80ca1e..0000000000 --- a/board/sunxi/ahci.c +++ /dev/null @@ -1,134 +0,0 @@ -#include <common.h> -#include <ahci.h> -#include <dm.h> -#include <scsi.h> -#include <errno.h> -#include <asm/io.h> -#include <asm/gpio.h> - -#define AHCI_PHYCS0R 0x00c0 -#define AHCI_PHYCS1R 0x00c4 -#define AHCI_PHYCS2R 0x00c8 -#define AHCI_RWCR 0x00fc - -/* This magic PHY initialisation was taken from the Allwinner releases - * and Linux driver, but is completely undocumented. - */ -static int sunxi_ahci_phy_init(u8 *reg_base) -{ - u32 reg_val; - int timeout; - - writel(0, reg_base + AHCI_RWCR); - mdelay(5); - - setbits_le32(reg_base + AHCI_PHYCS1R, 0x1 << 19); - clrsetbits_le32(reg_base + AHCI_PHYCS0R, - (0x7 << 24), - (0x5 << 24) | (0x1 << 23) | (0x1 << 18)); - clrsetbits_le32(reg_base + AHCI_PHYCS1R, - (0x3 << 16) | (0x1f << 8) | (0x3 << 6), - (0x2 << 16) | (0x6 << 8) | (0x2 << 6)); - setbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 28) | (0x1 << 15)); - clrbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 19)); - clrsetbits_le32(reg_base + AHCI_PHYCS0R, (0x7 << 20), (0x3 << 20)); - clrsetbits_le32(reg_base + AHCI_PHYCS2R, (0x1f << 5), (0x19 << 5)); - mdelay(5); - - setbits_le32(reg_base + AHCI_PHYCS0R, (0x1 << 19)); - - timeout = 250; /* Power up takes approx 50 us */ - for (;;) { - reg_val = readl(reg_base + AHCI_PHYCS0R) & (0x7 << 28); - if (reg_val == (0x2 << 28)) - break; - if (--timeout == 0) { - printf("AHCI PHY power up failed.\n"); - return -EIO; - } - udelay(1); - }; - - setbits_le32(reg_base + AHCI_PHYCS2R, (0x1 << 24)); - - timeout = 100; /* Calibration takes approx 10 us */ - for (;;) { - reg_val = readl(reg_base + AHCI_PHYCS2R) & (0x1 << 24); - if (reg_val == 0x0) - break; - if (--timeout == 0) { - printf("AHCI PHY calibration failed.\n"); - return -EIO; - } - udelay(1); - } - - mdelay(15); - - writel(0x7, reg_base + AHCI_RWCR); - - return 0; -} - -#ifndef CONFIG_DM_SCSI -void scsi_init(void) -{ - if (sunxi_ahci_phy_init((u8 *)SUNXI_SATA_BASE) < 0) - return; - - ahci_init((void __iomem *)SUNXI_SATA_BASE); -} -#else -static int sunxi_sata_probe(struct udevice *dev) -{ - ulong base; - u8 *reg; - int ret; - - base = dev_read_addr(dev); - if (base == FDT_ADDR_T_NONE) { - debug("%s: Failed to find address (err=%d\n)", __func__, ret); - return -EINVAL; - } - reg = (u8 *)base; - ret = sunxi_ahci_phy_init(reg); - if (ret) { - debug("%s: Failed to init phy (err=%d\n)", __func__, ret); - return ret; - } - ret = ahci_probe_scsi(dev, base); - if (ret) { - debug("%s: Failed to probe (err=%d\n)", __func__, ret); - return ret; - } - - return 0; -} - -static int sunxi_sata_bind(struct udevice *dev) -{ - struct udevice *scsi_dev; - int ret; - - ret = ahci_bind_scsi(dev, &scsi_dev); - if (ret) { - debug("%s: Failed to bind (err=%d\n)", __func__, ret); - return ret; - } - - return 0; -} - -static const struct udevice_id sunxi_ahci_ids[] = { - { .compatible = "allwinner,sun4i-a10-ahci" }, - { } -}; - -U_BOOT_DRIVER(ahci_sunxi_drv) = { - .name = "ahci_sunxi", - .id = UCLASS_AHCI, - .of_match = sunxi_ahci_ids, - .bind = sunxi_sata_bind, - .probe = sunxi_sata_probe, -}; -#endif diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c index 826650c89b..d8fdf7728e 100644 --- a/board/sunxi/gmac.c +++ b/board/sunxi/gmac.c @@ -12,14 +12,6 @@ void eth_init_board(void) struct sunxi_ccm_reg *const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - /* Set up clock gating */ -#ifdef CONFIG_SUNXI_GEN_SUN6I - setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC); - setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC); -#else - setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC); -#endif - /* Set MII clock */ #ifdef CONFIG_RGMII setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII | diff --git a/board/synopsys/axs10x/axs10x.c b/board/synopsys/axs10x/axs10x.c index ffa7c154b5..7c4fcf281c 100644 --- a/board/synopsys/axs10x/axs10x.c +++ b/board/synopsys/axs10x/axs10x.c @@ -11,35 +11,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_mmc_init(bd_t *bis) -{ - struct dwmci_host *host = NULL; - - host = malloc(sizeof(struct dwmci_host)); - if (!host) { - printf("dwmci_host malloc fail!\n"); - return 1; - } - - memset(host, 0, sizeof(struct dwmci_host)); - host->name = "Synopsys Mobile storage"; - host->ioaddr = (void *)ARC_DWMMC_BASE; - host->buswidth = 4; - host->dev_index = 0; - host->bus_hz = 50000000; - - add_dwmci(host, host->bus_hz / 2, 400000); - - return 0; -} - -int board_mmc_getcd(struct mmc *mmc) -{ - struct dwmci_host *host = mmc->priv; - - return !(dwmci_readl(host, DWMCI_CDETECT) & 1); -} - #define AXS_MB_CREG 0xE0011000 int board_early_init_f(void) diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c index 8a2c201477..ac4d980c49 100644 --- a/board/synopsys/hsdk/hsdk.c +++ b/board/synopsys/hsdk/hsdk.c @@ -982,6 +982,12 @@ int board_early_init_f(void) */ init_memory_bridge(); + /* + * Switch SDIO external ciu clock divider from default div-by-8 to + * minimum possible div-by-2. + */ + writel(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *)SDIO_UHS_REG_EXT); + return 0; } @@ -1019,41 +1025,6 @@ int board_late_init(void) return 0; } -int board_mmc_getcd(struct mmc *mmc) -{ - struct dwmci_host *host = mmc->priv; - - return !(dwmci_readl(host, DWMCI_CDETECT) & 1); -} - -int board_mmc_init(bd_t *bis) -{ - struct dwmci_host *host = NULL; - - host = malloc(sizeof(struct dwmci_host)); - if (!host) { - printf("dwmci_host malloc fail!\n"); - return 1; - } - - /* - * Switch SDIO external ciu clock divider from default div-by-8 to - * minimum possible div-by-2. - */ - writel(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *)SDIO_UHS_REG_EXT); - - memset(host, 0, sizeof(struct dwmci_host)); - host->name = "Synopsys Mobile storage"; - host->ioaddr = (void *)ARC_DWMMC_BASE; - host->buswidth = 4; - host->dev_index = 0; - host->bus_hz = 50000000; - - add_dwmci(host, host->bus_hz / 2, 400000); - - return 0; -} - int checkboard(void) { puts("Board: Synopsys ARC HS Development Kit\n"); diff --git a/board/tbs/tbs2910/MAINTAINERS b/board/tbs/tbs2910/MAINTAINERS index bf176553d2..a3ad2f712a 100644 --- a/board/tbs/tbs2910/MAINTAINERS +++ b/board/tbs/tbs2910/MAINTAINERS @@ -1,6 +1,7 @@ TBS2910 BOARD M: Soeren Moch <smoch@web.de> S: Maintained +F: arch/arm/dts/imx6q-tbs2910.dts F: board/tbs/tbs2910/ F: configs/tbs2910_defconfig F: include/configs/tbs2910.h diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c index ecb45f208d..fb0e773afc 100644 --- a/board/tbs/tbs2910/tbs2910.c +++ b/board/tbs/tbs2910/tbs2910.c @@ -9,9 +9,7 @@ #include <asm/arch/mx6-pins.h> #include <linux/errno.h> #include <asm/gpio.h> -#include <asm/mach-imx/mxc_i2c.h> #include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/sata.h> #include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/video.h> #include <mmc.h> @@ -22,7 +20,6 @@ #include <asm/arch/crm_regs.h> #include <asm/io.h> #include <asm/arch/sys_proto.h> -#include <i2c.h> DECLARE_GLOBAL_DATA_PTR; #define WEAK_PULLUP (PAD_CTL_PUS_47K_UP | \ @@ -33,63 +30,9 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - -#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) - -#ifdef CONFIG_SYS_I2C -/* I2C1, SGTL5000 */ -static struct i2c_pads_info i2c_pad_info0 = { - .scl = { - .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD, - .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD, - .gp = IMX_GPIO_NR(5, 27) - }, - .sda = { - .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD, - .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD, - .gp = IMX_GPIO_NR(5, 26) - } -}; - -/* I2C2 HDMI */ -static struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, - .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD, - .gp = IMX_GPIO_NR(4, 12) - }, - .sda = { - .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, - .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, - .gp = IMX_GPIO_NR(4, 13) - } -}; - -/* I2C3, CON11, DS1307, PCIe_SMB */ -static struct i2c_pads_info i2c_pad_info2 = { - .scl = { - .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD, - .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD, - .gp = IMX_GPIO_NR(1, 3) - }, - .sda = { - .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD, - .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD, - .gp = IMX_GPIO_NR(1, 6) - } -}; -#endif /* CONFIG_SYS_I2C */ - static iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), @@ -138,6 +81,7 @@ static void setup_iomux_enet(void) imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); /* Reset AR8035 PHY */ + gpio_request(IMX_GPIO_NR(1, 25), "ETH_PHY_RESET"); gpio_direction_output(IMX_GPIO_NR(1, 25) , 0); udelay(500); gpio_set_value(IMX_GPIO_NR(1, 25), 1); @@ -155,108 +99,6 @@ static void setup_iomux_uart(void) } #ifdef CONFIG_FSL_ESDHC -static iomux_v3_cfg_t const usdhc2_pads[] = { - MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ -}; - -static iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ -}; - -static iomux_v3_cfg_t const usdhc4_pads[] = { - MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - -static struct fsl_esdhc_cfg usdhc_cfg[3] = { - {USDHC2_BASE_ADDR}, - {USDHC3_BASE_ADDR}, - {USDHC4_BASE_ADDR}, -}; - -#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2) -#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0) - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC2_BASE_ADDR: - ret = !gpio_get_value(USDHC2_CD_GPIO); - break; - case USDHC3_BASE_ADDR: - ret = !gpio_get_value(USDHC3_CD_GPIO); - break; - case USDHC4_BASE_ADDR: - ret = 1; /* eMMC/uSDHC4 is always present */ - break; - } - return ret; -} - -int board_mmc_init(bd_t *bis) -{ - /* - * (U-Boot device node) (Physical Port) - * mmc0 SD2 - * mmc1 SD3 - * mmc2 eMMC - */ - int i, ret; - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - imx_iomux_v3_setup_multiple_pads( - usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); - gpio_direction_input(USDHC2_CD_GPIO); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - break; - case 1: - imx_iomux_v3_setup_multiple_pads( - usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - gpio_direction_input(USDHC3_CD_GPIO); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - break; - case 2: - imx_iomux_v3_setup_multiple_pads( - usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); - usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - break; - default: - printf("Warning: you configured more USDHC controllers" - "(%d) then supported by the board (%d)\n", - i + 1, CONFIG_SYS_FSL_USDHC_NUM); - return -EINVAL; - } - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) - return ret; - } - return 0; -} - /* set environment device to boot device when booting from SD */ int board_mmc_get_env_dev(int devno) { @@ -415,12 +257,6 @@ static const struct boot_mode board_boot_modes[] = { }; #endif -#ifdef CONFIG_USB_EHCI_MX6 -static iomux_v3_cfg_t const usb_otg_pads[] = { - MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), -}; -#endif - int board_init(void) { /* address of boot parameters */ @@ -429,26 +265,8 @@ int board_init(void) #ifdef CONFIG_VIDEO_IPUV3 setup_display(); #endif -#ifdef CONFIG_SYS_I2C - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); -#endif -#ifdef CONFIG_DWC_AHSATA - setup_sata(); -#endif #ifdef CONFIG_CMD_BMODE add_board_boot_modes(board_boot_modes); #endif -#ifdef CONFIG_USB_EHCI_MX6 - imx_iomux_v3_setup_multiple_pads( - usb_otg_pads, ARRAY_SIZE(usb_otg_pads)); -#endif - return 0; -} - -int checkboard(void) -{ - puts("Board: TBS2910 Matrix ARM mini PC\n"); return 0; } diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c index dd6def5e6e..d42350319c 100644 --- a/board/theadorable/theadorable.c +++ b/board/theadorable/theadorable.c @@ -1,11 +1,15 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> + * Copyright (C) 2015-2019 Stefan Roese <sr@denx.de> */ #include <common.h> +#include <console.h> #include <i2c.h> #include <pci.h> +#if !defined(CONFIG_SPL_BUILD) +#include <bootcount.h> +#endif #include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/cpu.h> @@ -42,6 +46,7 @@ DECLARE_GLOBAL_DATA_PTR; #define STM_I2C_BUS 1 #define STM_I2C_ADDR 0x27 #define REBOOT_DELAY 1000 /* reboot-delay in ms */ +#define ABORT_TIMEOUT 3000 /* 3 seconds reboot abort timeout */ /* DDR3 static configuration */ static MV_DRAM_MC_INIT ddr3_theadorable[MV_MAX_DDR3_STATIC_SIZE] = { @@ -127,15 +132,15 @@ MV_DRAM_MODES *ddr3_get_static_ddr_mode(void) return &board_ddr_modes[0]; } -MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode) +MV_BIN_SERDES_CFG *board_serdes_cfg_get(void) { return &theadorable_serdes_cfg[0]; } u8 board_sat_r_get(u8 dev_num, u8 reg) { - /* Bit 0 enables PCI 2.0 link capabilities instead of PCI 1.x */ - return 0x01; + /* Bit x enables PCI 2.0 link capabilities instead of PCI 1.x */ + return 0xe; /* PEX port 0 is PCIe Gen1, PEX port 1..3 PCIe Gen2 */ } int board_early_init_f(void) @@ -218,7 +223,7 @@ int board_eth_init(bd_t *bis) } #endif -#ifdef CONFIG_BOARD_LATE_INIT +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_LATE_INIT) int board_late_init(void) { pci_dev_t bdf; @@ -232,6 +237,7 @@ int board_late_init(void) */ bdf = pci_find_device(PCI_VENDOR_ID_PLX, 0x8619, 0); if (bdf == -1) { + unsigned long start_time = get_timer(0); u8 i2c_buf[8]; int ret; @@ -239,6 +245,28 @@ int board_late_init(void) bootcount = bootcount_load(); printf("Failed to find PLX PEX-switch (bootcount=%ld)\n", bootcount); + + /* + * The user can exit this boot-loop in the error case by + * hitting Ctrl-C. So wait some time for this key here. + */ + printf("Continue booting with Ctrl-C, otherwise rebooting\n"); + do { + /* Handle control-c and timeouts */ + if (ctrlc()) { + printf("PEX error boot-loop aborted!\n"); + return 0; + } + } while (get_timer(start_time) < ABORT_TIMEOUT); + + + /* + * At this stage the bootcounter has not been incremented + * yet. We need to do this manually here to get an actually + * working bootcounter in this error case. + */ + bootcount_inc(); + if (bootcount > PEX_SWITCH_NOT_FOUNT_LIMIT) { printf("Issuing power-switch via uC!\n"); diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index d67f94ad47..2c32b92d94 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -875,157 +875,55 @@ int board_late_init(void) } #endif -#ifndef CONFIG_DM_ETH - -#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ - (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) -static void cpsw_control(int enabled) -{ - /* VTP can be added here */ - - return; -} - -static struct cpsw_slave_data cpsw_slaves[] = { +/* CPSW platdata */ +#if !CONFIG_IS_ENABLED(OF_CONTROL) +struct cpsw_slave_data slave_data[] = { { - .slave_reg_ofs = 0x208, - .sliver_reg_ofs = 0xd80, - .phy_addr = 0, + .slave_reg_ofs = CPSW_SLAVE0_OFFSET, + .sliver_reg_ofs = CPSW_SLIVER0_OFFSET, + .phy_addr = 0, }, { - .slave_reg_ofs = 0x308, - .sliver_reg_ofs = 0xdc0, - .phy_addr = 1, + .slave_reg_ofs = CPSW_SLAVE1_OFFSET, + .sliver_reg_ofs = CPSW_SLIVER1_OFFSET, + .phy_addr = 1, }, }; -static struct cpsw_platform_data cpsw_data = { - .mdio_base = CPSW_MDIO_BASE, +struct cpsw_platform_data am335_eth_data = { .cpsw_base = CPSW_BASE, - .mdio_div = 0xff, + .version = CPSW_CTRL_VERSION_2, + .bd_ram_ofs = CPSW_BD_OFFSET, + .ale_reg_ofs = CPSW_ALE_OFFSET, + .cpdma_reg_ofs = CPSW_CPDMA_OFFSET, + .mdio_div = CPSW_MDIO_DIV, + .host_port_reg_ofs = CPSW_HOST_PORT_OFFSET, .channels = 8, - .cpdma_reg_ofs = 0x800, - .slaves = 1, - .slave_data = cpsw_slaves, - .ale_reg_ofs = 0xd00, + .slaves = 2, + .slave_data = slave_data, .ale_entries = 1024, - .host_port_reg_ofs = 0x108, - .hw_stats_reg_ofs = 0x900, .bd_ram_ofs = 0x2000, - .mac_control = (1 << 5), - .control = cpsw_control, - .host_port_num = 0, - .version = CPSW_CTRL_VERSION_2, + .mac_control = 0x20, + .active_slave = 0, + .mdio_base = 0x4a101000, + .gmii_sel = 0x44e10650, + .phy_sel_compat = "ti,am3352-cpsw-phy-sel", + .syscon_addr = 0x44e10630, + .macid_sel_compat = "cpsw,am33xx", }; -#endif - -#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USB_ETHER)) &&\ - defined(CONFIG_SPL_BUILD)) || \ - ((defined(CONFIG_DRIVER_TI_CPSW) || \ - defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \ - !defined(CONFIG_SPL_BUILD)) -/* - * This function will: - * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr - * in the environment - * Perform fixups to the PHY present on certain boards. We only need this - * function in: - * - SPL with either CPSW or USB ethernet support - * - Full U-Boot, with either CPSW or USB ethernet - * Build in only these cases to avoid warnings about unused variables - * when we build an SPL that has neither option but full U-Boot will. - */ -int board_eth_init(bd_t *bis) -{ - int rv, n = 0; -#if defined(CONFIG_USB_ETHER) && \ - (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER)) - uint8_t mac_addr[6]; - uint32_t mac_hi, mac_lo; - - /* - * use efuse mac address for USB ethernet as we know that - * both CPSW and USB ethernet will never be active at the same time - */ - mac_lo = readl(&cdev->macid0l); - mac_hi = readl(&cdev->macid0h); - mac_addr[0] = mac_hi & 0xFF; - mac_addr[1] = (mac_hi & 0xFF00) >> 8; - mac_addr[2] = (mac_hi & 0xFF0000) >> 16; - mac_addr[3] = (mac_hi & 0xFF000000) >> 24; - mac_addr[4] = mac_lo & 0xFF; - mac_addr[5] = (mac_lo & 0xFF00) >> 8; -#endif - - -#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ - (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) - -#ifdef CONFIG_DRIVER_TI_CPSW - if (board_is_bone() || board_is_bone_lt() || board_is_bben() || - board_is_idk()) { - writel(MII_MODE_ENABLE, &cdev->miisel); - cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = - PHY_INTERFACE_MODE_MII; - } else if (board_is_icev2()) { - writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); - cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; - cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII; - cpsw_slaves[0].phy_addr = 1; - cpsw_slaves[1].phy_addr = 3; - } else { - writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); - cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = - PHY_INTERFACE_MODE_RGMII; - } - - rv = cpsw_register(&cpsw_data); - if (rv < 0) - printf("Error %d registering CPSW switch\n", rv); - else - n += rv; -#endif +struct eth_pdata cpsw_pdata = { + .iobase = 0x4a100000, + .phy_interface = 0, + .priv_pdata = &am335_eth_data, +}; - /* - * - * CPSW RGMII Internal Delay Mode is not supported in all PVT - * operating points. So we must set the TX clock delay feature - * in the AR8051 PHY. Since we only support a single ethernet - * device in U-Boot, we only do this for the first instance. - */ -#define AR8051_PHY_DEBUG_ADDR_REG 0x1d -#define AR8051_PHY_DEBUG_DATA_REG 0x1e -#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 -#define AR8051_RGMII_TX_CLK_DLY 0x100 - - if (board_is_evm_sk() || board_is_gp_evm() || board_is_bben()) { - const char *devname; - devname = miiphy_get_current_dev(); - - miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG, - AR8051_DEBUG_RGMII_CLK_DLY_REG); - miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG, - AR8051_RGMII_TX_CLK_DLY); - } -#endif -#if defined(CONFIG_USB_ETHER) && \ - (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER)) - if (is_valid_ethaddr(mac_addr)) - eth_env_set_enetaddr("usbnet_devaddr", mac_addr); - - rv = usb_eth_initialize(bis); - if (rv < 0) - printf("Error %d registering USB_ETHER\n", rv); - else - n += rv; -#endif - return n; -} +U_BOOT_DEVICE(am335x_eth) = { + .name = "eth_cpsw", + .platdata = &cpsw_pdata, +}; #endif -#endif /* CONFIG_DM_ETH */ - #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c index 784b2b0191..52f5d6b11e 100644 --- a/board/ti/am65x/evm.c +++ b/board/ti/am65x/evm.c @@ -10,6 +10,7 @@ #include <common.h> #include <asm/io.h> #include <spl.h> +#include <asm/arch/sys_proto.h> DECLARE_GLOBAL_DATA_PTR; @@ -66,3 +67,16 @@ int board_fit_config_name_match(const char *name) return -1; } #endif + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{ + int ret; + + ret = fdt_fixup_msmc_ram(blob, "/interconnect@100000", "sram@70000000"); + if (ret) + printf("%s: fixing up msmc ram failed %d\n", __func__, ret); + + return ret; +} +#endif diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 060c471032..179adc2fff 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -27,6 +27,7 @@ #include <environment.h> #include <dwc3-uboot.h> #include <dwc3-omap-uboot.h> +#include <i2c.h> #include <ti-usb-phy-uboot.h> #include <miiphy.h> @@ -55,6 +56,10 @@ DECLARE_GLOBAL_DATA_PTR; #define SYSINFO_BOARD_NAME_MAX_LEN 37 +/* I2C I/O Expander */ +#define NAND_PCF8575_ADDR 0x21 +#define NAND_PCF8575_I2C_BUS_NUM 0 + const struct omap_sysinfo sysinfo = { "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n" }; @@ -777,6 +782,44 @@ void set_muxconf_regs(void) early_padconf, ARRAY_SIZE(early_padconf)); } +#if defined(CONFIG_NAND) +static int nand_sw_detect(void) +{ + int rc; + uchar data[2]; + struct udevice *dev; + + rc = i2c_get_chip_for_busnum(NAND_PCF8575_I2C_BUS_NUM, + NAND_PCF8575_ADDR, 0, &dev); + if (rc) + return -1; + + rc = dm_i2c_read(dev, 0, (uint8_t *)&data, sizeof(data)); + if (rc) + return -1; + + /* We are only interested in P10 and P11 on PCF8575 which is equal to + * bits 8 and 9. + */ + data[1] = data[1] & 0x3; + + /* Ensure only P11 is set and P10 is cleared. This ensures only + * NAND (P10) is configured and not NOR (P11) which are both low + * true signals. NAND and NOR settings should not be enabled at + * the same time. + */ + if (data[1] == 0x2) + return 0; + + return -1; +} +#else +int nand_sw_detect(void) +{ + return -1; +} +#endif + #ifdef CONFIG_IODELAY_RECALIBRATION void recalibrate_iodelay(void) { @@ -796,6 +839,19 @@ void recalibrate_iodelay(void) npads = ARRAY_SIZE(dra71x_core_padconf_array); iodelay = dra71_iodelay_cfg_array; niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array); + /* If SW8 on the EVM is set to enable NAND then + * overwrite the pins used by VOUT3 with NAND. + */ + if (!nand_sw_detect()) { + delta_pads = dra71x_nand_padconf_array; + delta_npads = + ARRAY_SIZE(dra71x_nand_padconf_array); + } else { + delta_pads = dra71x_vout3_padconf_array; + delta_npads = + ARRAY_SIZE(dra71x_vout3_padconf_array); + } + } else if (board_is_dra72x_revc_or_later()) { delta_pads = dra72x_rgmii_padconf_array_revc; delta_npads = diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index f1f6bd5316..75da5cb608 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -220,22 +220,6 @@ const struct pad_conf_entry dra72x_rgmii_padconf_array_revc[] = { }; const struct pad_conf_entry dra71x_core_padconf_array[] = { - {GPMC_AD0, (M3 | PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */ - {GPMC_AD1, (M3 | PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */ - {GPMC_AD2, (M3 | PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */ - {GPMC_AD3, (M3 | PIN_INPUT)}, /* gpmc_ad3.vout3_d3 */ - {GPMC_AD4, (M3 | PIN_INPUT)}, /* gpmc_ad4.vout3_d4 */ - {GPMC_AD5, (M3 | PIN_INPUT)}, /* gpmc_ad5.vout3_d5 */ - {GPMC_AD6, (M3 | PIN_INPUT)}, /* gpmc_ad6.vout3_d6 */ - {GPMC_AD7, (M3 | PIN_INPUT)}, /* gpmc_ad7.vout3_d7 */ - {GPMC_AD8, (M3 | PIN_INPUT)}, /* gpmc_ad8.vout3_d8 */ - {GPMC_AD9, (M3 | PIN_INPUT)}, /* gpmc_ad9.vout3_d9 */ - {GPMC_AD10, (M3 | PIN_INPUT)}, /* gpmc_ad10.vout3_d10 */ - {GPMC_AD11, (M3 | PIN_INPUT)}, /* gpmc_ad11.vout3_d11 */ - {GPMC_AD12, (M3 | PIN_INPUT)}, /* gpmc_ad12.vout3_d12 */ - {GPMC_AD13, (M3 | PIN_INPUT)}, /* gpmc_ad13.vout3_d13 */ - {GPMC_AD14, (M3 | PIN_INPUT)}, /* gpmc_ad14.vout3_d14 */ - {GPMC_AD15, (M3 | PIN_INPUT)}, /* gpmc_ad15.vout3_d15 */ {GPMC_A0, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a0.vout3_d16 */ {GPMC_A1, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a1.vout3_d17 */ {GPMC_A2, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a2.vout3_d18 */ @@ -370,6 +354,50 @@ const struct pad_conf_entry dra71x_core_padconf_array[] = { {WAKEUP3, (M1 | PULL_ENA | PULL_UP)}, /* Wakeup3.sys_nirq1 */ }; +const struct pad_conf_entry dra71x_vout3_padconf_array[] = { + {GPMC_AD0, (M3 | PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */ + {GPMC_AD1, (M3 | PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */ + {GPMC_AD2, (M3 | PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */ + {GPMC_AD3, (M3 | PIN_INPUT)}, /* gpmc_ad3.vout3_d3 */ + {GPMC_AD4, (M3 | PIN_INPUT)}, /* gpmc_ad4.vout3_d4 */ + {GPMC_AD5, (M3 | PIN_INPUT)}, /* gpmc_ad5.vout3_d5 */ + {GPMC_AD6, (M3 | PIN_INPUT)}, /* gpmc_ad6.vout3_d6 */ + {GPMC_AD7, (M3 | PIN_INPUT)}, /* gpmc_ad7.vout3_d7 */ + {GPMC_AD8, (M3 | PIN_INPUT)}, /* gpmc_ad8.vout3_d8 */ + {GPMC_AD9, (M3 | PIN_INPUT)}, /* gpmc_ad9.vout3_d9 */ + {GPMC_AD10, (M3 | PIN_INPUT)}, /* gpmc_ad10.vout3_d10 */ + {GPMC_AD11, (M3 | PIN_INPUT)}, /* gpmc_ad11.vout3_d11 */ + {GPMC_AD12, (M3 | PIN_INPUT)}, /* gpmc_ad12.vout3_d12 */ + {GPMC_AD13, (M3 | PIN_INPUT)}, /* gpmc_ad13.vout3_d13 */ + {GPMC_AD14, (M3 | PIN_INPUT)}, /* gpmc_ad14.vout3_d14 */ + {GPMC_AD15, (M3 | PIN_INPUT)}, /* gpmc_ad15.vout3_d15 */ +}; + +const struct pad_conf_entry dra71x_nand_padconf_array[] = { + {GPMC_AD0, (M0 | PIN_INPUT)}, /* gpmc_ad0.gpmc_ad0 */ + {GPMC_AD1, (M0 | PIN_INPUT)}, /* gpmc_ad1.gpmc_ad1 */ + {GPMC_AD2, (M0 | PIN_INPUT)}, /* gpmc_ad2.gpmc_ad2 */ + {GPMC_AD3, (M0 | PIN_INPUT)}, /* gpmc_ad3.gpmc_ad3 */ + {GPMC_AD4, (M0 | PIN_INPUT)}, /* gpmc_ad4.gpmc_ad4 */ + {GPMC_AD5, (M0 | PIN_INPUT)}, /* gpmc_ad5.gpmc_ad5 */ + {GPMC_AD6, (M0 | PIN_INPUT)}, /* gpmc_ad6.gpmc_ad6 */ + {GPMC_AD7, (M0 | PIN_INPUT)}, /* gpmc_ad7.gpmc_ad7 */ + {GPMC_AD8, (M0 | PIN_INPUT)}, /* gpmc_ad8.gpmc_ad8 */ + {GPMC_AD9, (M0 | PIN_INPUT)}, /* gpmc_ad9.gpmc_ad9 */ + {GPMC_AD10, (M0 | PIN_INPUT)}, /* gpmc_ad10.gpmc_ad10 */ + {GPMC_AD11, (M0 | PIN_INPUT)}, /* gpmc_ad11.gpmc_ad11 */ + {GPMC_AD12, (M0 | PIN_INPUT)}, /* gpmc_ad12.gpmc_ad12 */ + {GPMC_AD13, (M0 | PIN_INPUT)}, /* gpmc_ad13.gpmc_ad13 */ + {GPMC_AD14, (M0 | PIN_INPUT)}, /* gpmc_ad14.gpmc_ad14 */ + {GPMC_AD15, (M0 | PIN_INPUT)}, /* gpmc_ad15.gpmc_ad15 */ + {GPMC_CS0, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_cs0.gpmc_cs0 */ + {GPMC_ADVN_ALE, (M0 | PIN_INPUT_PULLDOWN)}, /* gpmc_advn_ale.gpmc_advn_ale */ + {GPMC_OEN_REN, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_oen_ren.gpmc_oen_ren */ + {GPMC_WEN, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_wen.gpmc_wen */ + {GPMC_BEN0, (M0 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben0.gpmc_ben0 */ + {GPMC_WAIT0, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* gpmc_wait0.gpmc_wait0 */ +}; + const struct pad_conf_entry early_padconf[] = { {UART1_RXD, (PIN_INPUT_SLEW | M0)}, /* UART1_RXD */ {UART1_TXD, (PIN_INPUT_SLEW | M0)}, /* UART1_TXD */ diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c index 39a782e479..6d0fc21c67 100644 --- a/board/ti/ks2_evm/board_k2g.c +++ b/board/ti/ks2_evm/board_k2g.c @@ -315,6 +315,21 @@ int embedded_dtb_select(void) BIT(9)); setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET, BIT(9)); + } else if (board_is_k2g_ice()) { + /* GBE Phy workaround. For Phy to latch the input + * configuration, a GPIO reset is asserted at the + * Phy reset pin to latch configuration correctly after SoC + * reset. GPIO0 Pin 10 (Ball AA20) is used for this on ICE + * board. Just do a low to high transition. + */ + clrbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_DIR_OFFSET, + BIT(10)); + setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_CLRDATA_OFFSET, + BIT(10)); + /* Delay just to get a transition to high */ + udelay(100); + setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_SETDATA_OFFSET, + BIT(10)); } return 0; diff --git a/board/ti/ks2_evm/mux-k2g.h b/board/ti/ks2_evm/mux-k2g.h index 706fb7e838..89c49f9e4f 100644 --- a/board/ti/ks2_evm/mux-k2g.h +++ b/board/ti/ks2_evm/mux-k2g.h @@ -125,21 +125,23 @@ struct pin_cfg k2g_evm_pin_cfg[] = { { 70, MODE(0) }, /* SOC_MMC1_SDWP */ { 71, MODE(0) }, /* MMC1POW TP124 */ - /* RGMII */ - { 72, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXCLK */ - { 77, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD3 */ - { 78, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD2 */ - { 79, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD1 */ - { 80, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD0 */ - { 81, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXCTL */ - { 85, MODE(1) }, /* SOC_RGMII_TXCLK */ - { 91, MODE(1) }, /* SOC_RGMII_TXD3 */ - { 92, MODE(1) }, /* SOC_RGMII_TXD2 */ - { 93, MODE(1) }, /* SOC_RGMII_TXD1 */ - { 94, MODE(1) }, /* SOC_RGMII_TXD0 */ - { 95, MODE(1) }, /* SOC_RGMII_TXCTL */ - { 98, MODE(0) }, /* SOC_MDIO_DATA */ - { 99, MODE(0) }, /* SOC_MDIO_CLK */ + /* EMAC */ + { 79, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD1 */ + { 78, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD2 */ + { 77, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD3 */ + { 80, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD0 */ + { 94, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD0 */ + { 93, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD1 */ + { 92, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD2 */ + { 91, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD3 */ + { 85, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXC */ + { 95, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXCTL */ + { 72, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXC */ + { 81, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXCTL */ + + /* MDIO */ + { 99, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_CLK */ + { 98, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_DATA */ /* PWM */ { 73, MODE(4) }, /* SOC_EHRPWM3A */ @@ -346,6 +348,25 @@ struct pin_cfg k2g_ice_evm_pin_cfg[] = { { 133, MODE(0) }, /* SOC_QSPI_D2 */ { 134, MODE(0) }, /* SOC_QSPI_D3 */ { 135, MODE(0) }, /* SOC_QSPI_CSN0 */ + + /* EMAC */ + { 79, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD1 */ + { 78, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD2 */ + { 77, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD3 */ + { 80, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD0 */ + { 94, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD0 */ + { 93, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD1 */ + { 92, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD2 */ + { 91, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD3 */ + { 85, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXC */ + { 95, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXCTL */ + { 72, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXC */ + { 81, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXCTL */ + + /* MDIO */ + { 99, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_CLK */ + { 98, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_DATA */ + { MAX_PIN_N, } }; diff --git a/board/toradex/apalis_imx6/1066mhz_4x128mx16.cfg b/board/toradex/apalis_imx6/1066mhz_4x128mx16.cfg deleted file mode 100644 index 29d1c3126c..0000000000 --- a/board/toradex/apalis_imx6/1066mhz_4x128mx16.cfg +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2014-2016 Toradex AG - */ - -DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 -DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7954 -DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB328F64 -DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB -DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 -DATA 4, MX6_MMDC_P0_MDOR, 0x005A1023 -DATA 4, MX6_MMDC_P0_MDOTC, 0x09555050 -DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 -DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 -DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000 -DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031 -DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030 -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 -DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 -DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 -DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 -DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000000 -DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000 - -DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x432A0338 -DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03260324 -DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43340344 -DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x031E027C - -DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x33272D2E -DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x2F312B37 - -DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3A35433C -DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4336453F - -DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E -DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B -DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00060015 -DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E - -DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 -DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 -DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/toradex/apalis_imx6/1066mhz_4x256mx16.cfg b/board/toradex/apalis_imx6/1066mhz_4x256mx16.cfg deleted file mode 100644 index 02e90dd5e6..0000000000 --- a/board/toradex/apalis_imx6/1066mhz_4x256mx16.cfg +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2014-2016 Toradex AG - */ - -DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 -DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E78f5 -DATA 4, MX6_MMDC_P0_MDCFG1, 0xff328f64 -DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB -DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 -DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023 -DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 -DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 -DATA 4, MX6_MMDC_P0_MDASP, 0x00000047 -DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000 -DATA 4, MX6_MMDC_P0_MDSCR, 0x02888032 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 -DATA 4, MX6_MMDC_P0_MDSCR, 0x19408030 -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 -DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 -DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 -DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 -DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 -DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 - -DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x03300338 -DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03240324 -DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x03440350 -DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x032C0308 - -DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x40363C3E -DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x3C3E3C46 - -DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x403E463E -DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4A384C46 - -DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E -DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B -DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00060015 -DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E - -DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 -DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 -DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/toradex/apalis_imx6/MAINTAINERS b/board/toradex/apalis_imx6/MAINTAINERS index 2c70ab4fbd..7efe816a78 100644 --- a/board/toradex/apalis_imx6/MAINTAINERS +++ b/board/toradex/apalis_imx6/MAINTAINERS @@ -1,9 +1,9 @@ Apalis iMX6 M: Max Krummenacher <max.krummenacher@toradex.com> W: http://developer.toradex.com/software/linux/linux-software +W: https://www.toradex.com/community S: Maintained F: board/toradex/apalis_imx6/ F: include/configs/apalis_imx6.h F: configs/apalis_imx6_defconfig -F: configs/apalis_imx6_nospl_com_defconfig -F: configs/apalis_imx6_nospl_it_defconfig +F: arch/arm/dts/imx6-apalis.dts diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c index d11207c7f4..3e59185438 100644 --- a/board/toradex/apalis_imx6/apalis_imx6.c +++ b/board/toradex/apalis_imx6/apalis_imx6.c @@ -2,38 +2,33 @@ /* * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com> - * Copyright (C) 2014-2016, Toradex AG + * Copyright (C) 2014-2019, Toradex AG * copied from nitrogen6x */ #include <common.h> #include <dm.h> -#include <environment.h> + +#include <ahci.h> #include <asm/arch/clock.h> #include <asm/arch/crm_regs.h> -#include <asm/arch/mxc_hdmi.h> #include <asm/arch/imx-regs.h> -#include <asm/arch/iomux.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/mx6-pins.h> #include <asm/arch/mx6-ddr.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/mxc_hdmi.h> +#include <asm/arch/sys_proto.h> #include <asm/bootm.h> #include <asm/gpio.h> -#include <asm/io.h> +#include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/mxc_i2c.h> #include <asm/mach-imx/sata.h> -#include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/video.h> +#include <dm/device-internal.h> #include <dm/platform_data/serial_mxc.h> -#include <dm/platdata.h> +#include <dwc_ahsata.h> +#include <environment.h> #include <fsl_esdhc.h> -#include <i2c.h> -#include <input.h> #include <imx_thermal.h> -#include <linux/errno.h> -#include <malloc.h> -#include <mmc.h> #include <micrel.h> #include <miiphy.h> #include <netdev.h> @@ -50,40 +45,30 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SRE_FAST | PAD_CTL_HYS) #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) -#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_SRE_SLOW) -#define NO_PULLUP ( \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_SRE_SLOW) - #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_HYS | PAD_CTL_SRE_SLOW) #define TRISTATE (PAD_CTL_HYS | PAD_CTL_SPEED_MED) -#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) - #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST) +#define APALIS_IMX6_SATA_INIT_RETRIES 10 + int dram_init(void) { /* use the DDR controllers configured size */ @@ -103,63 +88,7 @@ iomux_v3_cfg_t const uart1_pads_dte[] = { MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -/* Apalis I2C1 */ -struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC, - .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC, - .gp = IMX_GPIO_NR(5, 27) - }, - .sda = { - .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC, - .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC, - .gp = IMX_GPIO_NR(5, 26) - } -}; - -/* Apalis local, PMIC, SGTL5000, STMPE811 */ -struct i2c_pads_info i2c_pad_info_loc = { - .scl = { - .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, - .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC, - .gp = IMX_GPIO_NR(4, 12) - }, - .sda = { - .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, - .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC, - .gp = IMX_GPIO_NR(4, 13) - } -}; - -/* Apalis I2C3 / CAM */ -struct i2c_pads_info i2c_pad_info3 = { - .scl = { - .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC, - .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC, - .gp = IMX_GPIO_NR(3, 17) - }, - .sda = { - .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, - .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, - .gp = IMX_GPIO_NR(3, 18) - } -}; - -/* Apalis I2C2 / DDC */ -struct i2c_pads_info i2c_pad_info_ddc = { - .scl = { - .i2c_mode = MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL | PC, - .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, - .gp = IMX_GPIO_NR(2, 30) - }, - .sda = { - .i2c_mode = MX6_PAD_EIM_D16__HDMI_TX_DDC_SDA | PC, - .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC, - .gp = IMX_GPIO_NR(3, 16) - } -}; - +#if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD) /* Apalis MMC1 */ iomux_v3_cfg_t const usdhc1_pads[] = { MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -190,18 +119,19 @@ iomux_v3_cfg_t const usdhc2_pads[] = { /* eMMC */ iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION, }; +#endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */ int mx6_rgmii_rework(struct phy_device *phydev) { @@ -241,7 +171,8 @@ iomux_v3_cfg_t const enet_pads[] = { MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), /* KSZ9031 PHY Reset */ - MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL) | + MUX_MODE_SION, # define GPIO_ENET_PHY_RESET IMX_GPIO_NR(1, 25) }; @@ -253,6 +184,7 @@ static void setup_iomux_enet(void) static int reset_enet_phy(struct mii_dev *bus) { /* Reset KSZ9031 PHY */ + gpio_request(GPIO_ENET_PHY_RESET, "ETH_RESET#"); gpio_direction_output(GPIO_ENET_PHY_RESET, 0); mdelay(10); gpio_set_value(GPIO_ENET_PHY_RESET, 1); @@ -263,15 +195,24 @@ static int reset_enet_phy(struct mii_dev *bus) /* mux the Apalis GPIO pins, so they can be used from the U-Boot cmdline */ iomux_v3_cfg_t const gpio_pads[] = { /* Apalis GPIO1 - GPIO8 */ - MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(WEAK_PULLDOWN), - MX6_PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(WEAK_PULLDOWN) | + MUX_MODE_SION, + MX6_PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, }; static void setup_iomux_gpio(void) @@ -281,7 +222,7 @@ static void setup_iomux_gpio(void) iomux_v3_cfg_t const usb_pads[] = { /* USBH_EN */ - MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION, # define GPIO_USBH_EN IMX_GPIO_NR(1, 0) /* USB_VBUS_DET */ MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), @@ -289,7 +230,7 @@ iomux_v3_cfg_t const usb_pads[] = { /* USBO1_ID */ MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP), /* USBO1_EN */ - MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION, # define GPIO_USBO_EN IMX_GPIO_NR(3, 22) }; @@ -297,8 +238,11 @@ iomux_v3_cfg_t const usb_pads[] = { * UARTs are used in DTE mode, switch the mode on all UARTs before * any pinmuxing connects a (DCE) output to a transceiver output. */ +#define UCR3 0x88 /* FIFO Control Register */ +#define UCR3_RI BIT(8) /* RIDELT DTE mode */ +#define UCR3_DCD BIT(9) /* DCDDELT DTE mode */ #define UFCR 0x90 /* FIFO Control Register */ -#define UFCR_DCEDTE (1<<6) /* DCE=0 */ +#define UFCR_DCEDTE BIT(6) /* DCE=0 */ static void setup_dtemode_uart(void) { @@ -306,6 +250,11 @@ static void setup_dtemode_uart(void) setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE); setbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE); setbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE); + + clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI); + clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI); + clrbits_le32((u32 *)(UART4_BASE + UCR3), UCR3_DCD | UCR3_RI); + clrbits_le32((u32 *)(UART5_BASE + UCR3), UCR3_DCD | UCR3_RI); } static void setup_dcemode_uart(void) { @@ -321,7 +270,6 @@ static void setup_iomux_dte_uart(void) imx_iomux_v3_setup_multiple_pads(uart1_pads_dte, ARRAY_SIZE(uart1_pads_dte)); } - static void setup_iomux_dce_uart(void) { setup_dcemode_uart(); @@ -335,32 +283,10 @@ int board_ehci_hcd_init(int port) imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); return 0; } - -int board_ehci_power(int port, int on) -{ - switch (port) { - case 0: - /* control OTG power */ - gpio_direction_output(GPIO_USBO_EN, on); - mdelay(100); - break; - case 1: - /* Control MXM USBH */ - gpio_direction_output(GPIO_USBH_EN, on); - mdelay(2); - /* Control onboard USB Hub VBUS */ - gpio_direction_output(GPIO_USB_VBUS_DET, on); - mdelay(100); - break; - default: - break; - } - return 0; -} #endif -#ifdef CONFIG_FSL_ESDHC -/* use the following sequence: eMMC, MMC, SD */ +#if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD) +/* use the following sequence: eMMC, MMC1, SD1 */ struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { {USDHC3_BASE_ADDR}, {USDHC1_BASE_ADDR}, @@ -374,10 +300,12 @@ int board_mmc_getcd(struct mmc *mmc) switch (cfg->esdhc_base) { case USDHC1_BASE_ADDR: + gpio_request(GPIO_MMC_CD, "MMC_CD"); gpio_direction_input(GPIO_MMC_CD); ret = !gpio_get_value(GPIO_MMC_CD); break; case USDHC2_BASE_ADDR: + gpio_request(GPIO_MMC_CD, "SD_CD"); gpio_direction_input(GPIO_SD_CD); ret = !gpio_get_value(GPIO_SD_CD); break; @@ -388,43 +316,6 @@ int board_mmc_getcd(struct mmc *mmc) int board_mmc_init(bd_t *bis) { -#ifndef CONFIG_SPL_BUILD - s32 status = 0; - u32 index = 0; - - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - - usdhc_cfg[0].max_bus_width = 8; - usdhc_cfg[1].max_bus_width = 8; - usdhc_cfg[2].max_bus_width = 4; - - for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { - switch (index) { - case 0: - imx_iomux_v3_setup_multiple_pads( - usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - break; - case 1: - imx_iomux_v3_setup_multiple_pads( - usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); - break; - case 2: - imx_iomux_v3_setup_multiple_pads( - usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); - break; - default: - printf("Warning: you configured more USDHC controllers (%d) then supported by the board (%d)\n", - index + 1, CONFIG_SYS_FSL_USDHC_NUM); - return status; - } - - status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); - } - - return status; -#else struct src *psrc = (struct src *)SRC_BASE_ADDR; unsigned reg = readl(&psrc->sbmr1) >> 11; /* @@ -463,9 +354,8 @@ int board_mmc_init(bd_t *bis) } return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -#endif } -#endif +#endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */ int board_phy_config(struct phy_device *phydev) { @@ -489,6 +379,7 @@ int board_eth_init(bd_t *bis) bus = fec_get_miibus(base, -1); if (!bus) return 0; + bus->reset = reset_enet_phy; /* scan PHY 4,5,6,7 */ phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII); @@ -497,6 +388,7 @@ int board_eth_init(bd_t *bis) puts("no PHY found\n"); return 0; } + printf("using PHY at %d\n", phydev->addr); ret = fec_probe(bis, -1, base, bus, phydev); if (ret) { @@ -504,7 +396,8 @@ int board_eth_init(bd_t *bis) free(phydev); free(bus); } -#endif +#endif /* CONFIG_FEC_MXC */ + return 0; } @@ -520,18 +413,21 @@ static iomux_v3_cfg_t const pwr_intb_pads[] = { static iomux_v3_cfg_t const backlight_pads[] = { /* Backlight on RGB connector: J15 */ - MX6_PAD_EIM_DA13__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_DA13__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL) | + MUX_MODE_SION, #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 13) /* additional CPU pin on BKL_PWM, keep in tristate */ MX6_PAD_EIM_DA14__GPIO3_IO14 | MUX_PAD_CTRL(TRISTATE), /* Backlight PWM, used as GPIO in U-Boot */ - MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL) | + MUX_MODE_SION, #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 10) /* buffer output enable 0: buffer enabled */ - MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION, #define RGB_BACKLIGHTPWM_OE IMX_GPIO_NR(5, 2) /* PSAVE# integrated VDAC */ - MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) | + MUX_MODE_SION, #define VGA_PSAVE_NOT_GP IMX_GPIO_NR(6, 31) }; @@ -571,12 +467,6 @@ static void do_enable_hdmi(struct display_info_t const *dev) imx_enable_hdmi_phy(); } -static int detect_i2c(struct display_info_t const *dev) -{ - return (0 == i2c_set_bus_num(dev->bus)) && - (0 == i2c_probe(dev->addr)); -} - static void enable_lvds(struct display_info_t const *dev) { struct iomuxc *iomux = (struct iomuxc *) @@ -670,7 +560,6 @@ struct display_info_t const displays[] = {{ .bus = -1, .addr = 0, .pixfmt = IPU_PIX_FMT_LVDS666, - .detect = detect_i2c, .enable = enable_lvds, .mode = { .name = "wsvga-lvds", @@ -741,6 +630,9 @@ static void setup_display(void) imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads)); /* use 0 for EDT 7", use 1 for LG fullHD panel */ + gpio_request(RGB_BACKLIGHTPWM_GP, "BKL1_PWM"); + gpio_request(RGB_BACKLIGHTPWM_OE, "BKL1_PWM_EN"); + gpio_request(RGB_BACKLIGHT_GP, "BKL1_ON"); gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0); gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0); gpio_direction_output(RGB_BACKLIGHT_GP, 1); @@ -782,10 +674,6 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info_loc); - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3); - #if defined(CONFIG_VIDEO_IPUV3) setup_display(); #endif @@ -835,16 +723,17 @@ int board_late_init(void) #endif /* CONFIG_TDX_APALIS_IMX6_V1_0 */ #endif /* CONFIG_REVISION_TAG */ - return 0; -} -#endif /* CONFIG_BOARD_LATE_INIT */ +#ifdef CONFIG_CMD_USB_SDP + if (is_boot_from_usb()) { + printf("Serial Downloader recovery mode, using sdp command\n"); + env_set("bootdelay", "0"); + env_set("bootcmd", "sdp 0"); + } +#endif /* CONFIG_CMD_USB_SDP */ -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_SYSTEM_SETUP) -int ft_system_setup(void *blob, bd_t *bd) -{ return 0; } -#endif +#endif /* CONFIG_BOARD_LATE_INIT */ int checkboard(void) { @@ -1143,7 +1032,6 @@ MX6_MMDC_P0_MDSCR, 0x00000000, MX6_MMDC_P0_MAPSR, 0x00011006, }; - static void ccgr_init(void) { struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; @@ -1204,7 +1092,7 @@ void board_init_f(ulong dummy) ccgr_init(); gpr_init(); - /* iomux and setup of i2c */ + /* iomux */ board_early_init_f(); /* setup GP timer */ @@ -1232,7 +1120,7 @@ void reset_cpu(ulong addr) { } -#endif +#endif /* CONFIG_SPL_BUILD */ static struct mxc_serial_platdata mxc_serial_plat = { .reg = (struct mxc_uart *)UART1_BASE, @@ -1243,3 +1131,52 @@ U_BOOT_DEVICE(mxc_serial) = { .name = "serial_mxc", .platdata = &mxc_serial_plat, }; + +#if CONFIG_IS_ENABLED(AHCI) +static int sata_imx_probe(struct udevice *dev) +{ + int i, err; + + for (i = 0; i < APALIS_IMX6_SATA_INIT_RETRIES; i++) { + err = setup_sata(); + if (err) { + printf("SATA setup failed: %d\n", err); + return err; + } + + udelay(100); + + err = dwc_ahsata_probe(dev); + if (!err) + break; + + /* There is no device on the SATA port */ + if (sata_dm_port_status(0, 0) == 0) + break; + + /* There's a device, but link not established. Retry */ + device_remove(dev, DM_REMOVE_NORMAL); + } + + return 0; +} + +struct ahci_ops sata_imx_ops = { + .port_status = dwc_ahsata_port_status, + .reset = dwc_ahsata_bus_reset, + .scan = dwc_ahsata_scan, +}; + +static const struct udevice_id sata_imx_ids[] = { + { .compatible = "fsl,imx6q-ahci" }, + { } +}; + +U_BOOT_DRIVER(sata_imx) = { + .name = "dwc_ahci", + .id = UCLASS_AHCI, + .of_match = sata_imx_ids, + .ops = &sata_imx_ops, + .probe = sata_imx_probe, +}; +#endif /* AHCI */ diff --git a/board/toradex/apalis_imx6/apalis_imx6q.cfg b/board/toradex/apalis_imx6/apalis_imx6q.cfg deleted file mode 100644 index 739b1b7061..0000000000 --- a/board/toradex/apalis_imx6/apalis_imx6q.cfg +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2014-2016, Toradex AG - * - * Refer doc/README.imximage for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* image version */ -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ -BOOT_FROM sd - -#define __ASSEMBLY__ -#include <config.h> -#include "asm/arch/mx6-ddr.h" -#include "asm/arch/iomux.h" -#include "asm/arch/crm_regs.h" - -#include "ddr-setup.cfg" -#if CONFIG_DDR_MB == 2048 -#include "1066mhz_4x256mx16.cfg" -#else -#include "1066mhz_4x128mx16.cfg" -#endif -#include "clocks.cfg" diff --git a/board/toradex/apalis_imx6/clocks.cfg b/board/toradex/apalis_imx6/clocks.cfg deleted file mode 100644 index 1bcbc4fa38..0000000000 --- a/board/toradex/apalis_imx6/clocks.cfg +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2014-2016, Toradex AG - * - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -/* set the default clock gate to save power */ -DATA 4, CCM_CCGR0, 0x00C03F3F -DATA 4, CCM_CCGR1, 0x0030FC03 -DATA 4, CCM_CCGR2, 0x0FFFC000 -DATA 4, CCM_CCGR3, 0x3FF00000 -DATA 4, CCM_CCGR4, 0x00FFF300 -DATA 4, CCM_CCGR5, 0x0F0000C3 -DATA 4, CCM_CCGR6, 0x000003FF - -/* enable AXI cache for VDOA/VPU/IPU */ -DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -DATA 4, MX6_IOMUXC_GPR6, 0x007F007F -DATA 4, MX6_IOMUXC_GPR7, 0x007F007F - -/* - * Setup CCM_CCOSR register as follows: - * - * cko1_en = 1 --> CKO1 enabled - * cko1_div = 111 --> divide by 8 - * cko1_sel = 1011 --> ahb_clk_root - * - * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz - */ -DATA 4, CCM_CCOSR, 0x000000fb diff --git a/board/toradex/apalis_imx6/ddr-setup.cfg b/board/toradex/apalis_imx6/ddr-setup.cfg deleted file mode 100644 index e42e3ce438..0000000000 --- a/board/toradex/apalis_imx6/ddr-setup.cfg +++ /dev/null @@ -1,96 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2014-2016, Toradex AG - * - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -/* - * DDR3 settings - * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock), - * memory bus width: 64 bits x16/x32/x64 - * MX6DL ddr is limited to 800 MHz(400 MHz clock) - * memory bus width: 64 bits x16/x32/x64 - * MX6SOLO ddr is limited to 800 MHz(400 MHz clock) - * memory bus width: 32 bits x16/x32 - */ -DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 - -DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 -DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 -/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ -DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 - -DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 - -DATA 4, MX6_IOM_DRAM_CAS, 0x00020030 -DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 -DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 -DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 - -DATA 4, MX6_IOM_DRAM_RESET, 0x00020030 -DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 -DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 - -DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 -DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 - -/* (differential input) */ -DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 -/* (differential input) */ -DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 -/* disable ddr pullups */ -DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 -DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 -/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ -DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 - -/* Read data DQ Byte0-3 delay */ -DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 - -/* - * MDMISC mirroring interleaved (row/bank/col) - */ -DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 - -/* - * MDSCR con_req - */ -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 diff --git a/board/toradex/apalis_imx6/do_fuse.c b/board/toradex/apalis_imx6/do_fuse.c index e6793e366a..22d191f52a 100644 --- a/board/toradex/apalis_imx6/do_fuse.c +++ b/board/toradex/apalis_imx6/do_fuse.c @@ -29,7 +29,7 @@ static int mfgr_fuse(void) return CMD_RET_FAILURE; } /* boot cfg */ - fuse_prog(0, 5, 0x00005072); + fuse_prog(0, 5, 0x00005062); /* BT_FUSE_SEL */ fuse_prog(0, 6, 0x00000010); return CMD_RET_SUCCESS; diff --git a/board/toradex/apalis_imx6/pf0100.c b/board/toradex/apalis_imx6/pf0100.c index 7334e92f2e..ebd6418fd4 100644 --- a/board/toradex/apalis_imx6/pf0100.c +++ b/board/toradex/apalis_imx6/pf0100.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2014-2016, Toradex AG + * Copyright (C) 2014-2019, Toradex AG */ /* @@ -9,7 +9,6 @@ #include <common.h> #include <i2c.h> -#include <linux/compiler.h> #include <asm/arch/imx-regs.h> #include <asm/arch/iomux.h> #include <asm/arch/mx6-pins.h> @@ -22,6 +21,8 @@ /* define for PMIC register dump */ /*#define DEBUG */ +#define WARNBAR "@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\n" + /* use Apalis GPIO1 to switch on VPGM, ON: 1 */ static __maybe_unused iomux_v3_cfg_t const pmic_prog_pads[] = { MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), @@ -30,99 +31,100 @@ static __maybe_unused iomux_v3_cfg_t const pmic_prog_pads[] = { unsigned pmic_init(void) { + int rc; + struct udevice *dev = NULL; unsigned programmed = 0; uchar bus = 1; uchar devid, revid, val; - puts("PMIC: "); - if (!((0 == i2c_set_bus_num(bus)) && - (0 == i2c_probe(PFUZE100_I2C_ADDR)))) { - puts("i2c bus failed\n"); + puts("PMIC: "); + rc = i2c_get_chip_for_busnum(bus, PFUZE100_I2C_ADDR, 1, &dev); + if (rc) { + printf("failed to get device for PMIC at address 0x%x\n", + PFUZE100_I2C_ADDR); + return 0; + } + + /* check for errors in PMIC fuses */ + if (dm_i2c_read(dev, PFUZE100_INTSTAT3, &val, 1) < 0) { + puts("i2c pmic INTSTAT3 register read failed\n"); + return 0; + } + if (val & PFUZE100_BIT_OTP_ECCI) { + puts("\n" WARNBAR); + puts("WARNING: ecc errors found in pmic fuse banks\n"); + puts(WARNBAR); + } + if (dm_i2c_read(dev, PFUZE100_OTP_ECC_SE1, &val, 1) < 0) { + puts("i2c pmic ECC_SE1 register read failed\n"); + return 0; + } + if (val & PFUZE100_BITS_ECC_SE1) { + puts(WARNBAR); + puts("WARNING: ecc has made bit corrections in banks 1 to 5\n"); + puts(WARNBAR); + } + if (dm_i2c_read(dev, PFUZE100_OTP_ECC_SE2, &val, 1) < 0) { + puts("i2c pmic ECC_SE2 register read failed\n"); + return 0; + } + if (val & PFUZE100_BITS_ECC_SE2) { + puts(WARNBAR); + puts("WARNING: ecc has made bit corrections in banks 6 to 10\n" + ); + puts(WARNBAR); + } + if (dm_i2c_read(dev, PFUZE100_OTP_ECC_DE1, &val, 1) < 0) { + puts("i2c pmic ECC_DE register read failed\n"); return 0; } + if (val & PFUZE100_BITS_ECC_DE1) { + puts(WARNBAR); + puts("ERROR: banks 1 to 5 have uncorrectable bits\n"); + puts(WARNBAR); + } + if (dm_i2c_read(dev, PFUZE100_OTP_ECC_DE2, &val, 1) < 0) { + puts("i2c pmic ECC_DE register read failed\n"); + return 0; + } + if (val & PFUZE100_BITS_ECC_DE2) { + puts(WARNBAR); + puts("ERROR: banks 6 to 10 have uncorrectable bits\n"); + puts(WARNBAR); + } + /* get device ident */ - if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_DEVICEID, 1, &devid, 1) < 0) { + if (dm_i2c_read(dev, PFUZE100_DEVICEID, &devid, 1) < 0) { puts("i2c pmic devid read failed\n"); return 0; } - if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_REVID, 1, &revid, 1) < 0) { + if (dm_i2c_read(dev, PFUZE100_REVID, &revid, 1) < 0) { puts("i2c pmic revid read failed\n"); return 0; } - printf("device id: 0x%.2x, revision id: 0x%.2x\n", devid, revid); - -#ifdef DEBUG - { - unsigned i, j; - - for (i = 0; i < 16; i++) - printf("\t%x", i); - for (j = 0; j < 0x80; ) { - printf("\n%2x", j); - for (i = 0; i < 16; i++) { - i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1); - printf("\t%2x", val); - } - j += 0x10; - } - printf("\nEXT Page 1"); - - val = PFUZE100_PAGE_REGISTER_PAGE1; - if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, - &val, 1)) { - puts("i2c write failed\n"); - return 0; - } - - for (j = 0x80; j < 0x100; ) { - printf("\n%2x", j); - for (i = 0; i < 16; i++) { - i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1); - printf("\t%2x", val); - } - j += 0x10; - } - printf("\nEXT Page 2"); + printf("device id: 0x%.2x, revision id: 0x%.2x, ", devid, revid); - val = PFUZE100_PAGE_REGISTER_PAGE2; - if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, - &val, 1)) { - puts("i2c write failed\n"); - return 0; - } - - for (j = 0x80; j < 0x100; ) { - printf("\n%2x", j); - for (i = 0; i < 16; i++) { - i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1); - printf("\t%2x", val); - } - j += 0x10; - } - printf("\n"); - } -#endif /* get device programmed state */ val = PFUZE100_PAGE_REGISTER_PAGE1; - if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, &val, 1)) { + if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) { puts("i2c write failed\n"); return 0; } - if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR1, 1, &val, 1) < 0) { + if (dm_i2c_read(dev, PFUZE100_FUSE_POR1, &val, 1) < 0) { puts("i2c fuse_por read failed\n"); return 0; } if (val & PFUZE100_FUSE_POR_M) programmed++; - if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR2, 1, &val, 1) < 0) { + if (dm_i2c_read(dev, PFUZE100_FUSE_POR2, &val, 1) < 0) { puts("i2c fuse_por read failed\n"); return programmed; } if (val & PFUZE100_FUSE_POR_M) programmed++; - if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR3, 1, &val, 1) < 0) { + if (dm_i2c_read(dev, PFUZE100_FUSE_POR3, &val, 1) < 0) { puts("i2c fuse_por read failed\n"); return programmed; } @@ -131,13 +133,13 @@ unsigned pmic_init(void) switch (programmed) { case 0: - printf("PMIC: not programmed\n"); + puts("not programmed\n"); break; case 3: - printf("PMIC: programmed\n"); + puts("programmed\n"); break; default: - printf("PMIC: undefined programming state\n"); + puts("undefined programming state\n"); break; } @@ -145,25 +147,75 @@ unsigned pmic_init(void) if (programmed != 3) { /* set VGEN1 to 1.2V */ val = PFUZE100_VGEN1_VAL; - if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_VGEN1CTL, 1, - &val, 1)) { + if (dm_i2c_write(dev, PFUZE100_VGEN1CTL, &val, 1)) { puts("i2c write failed\n"); return programmed; } /* set SWBST to 5.0V */ val = PFUZE100_SWBST_VAL; - if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_SWBSTCTL, 1, - &val, 1)) { + if (dm_i2c_write(dev, PFUZE100_SWBSTCTL, &val, 1)) puts("i2c write failed\n"); + } + +#ifdef DEBUG + { + unsigned int i, j; + + for (i = 0; i < 16; i++) + printf("\t%x", i); + for (j = 0; j < 0x80; ) { + printf("\n%2x", j); + for (i = 0; i < 16; i++) { + dm_i2c_read(dev, j + i, &val, 1); + printf("\t%2x", val); + } + j += 0x10; } + printf("\nEXT Page 1"); + + val = PFUZE100_PAGE_REGISTER_PAGE1; + if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) { + puts("i2c write failed\n"); + return 0; + } + + for (j = 0x80; j < 0x100; ) { + printf("\n%2x", j); + for (i = 0; i < 16; i++) { + dm_i2c_read(dev, j + i, &val, 1); + printf("\t%2x", val); + } + j += 0x10; + } + printf("\nEXT Page 2"); + + val = PFUZE100_PAGE_REGISTER_PAGE2; + if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) { + puts("i2c write failed\n"); + return 0; + } + + for (j = 0x80; j < 0x100; ) { + printf("\n%2x", j); + for (i = 0; i < 16; i++) { + dm_i2c_read(dev, j + i, &val, 1); + printf("\t%2x", val); + } + j += 0x10; + } + printf("\n"); } +#endif /* DEBUG */ + return programmed; } #ifndef CONFIG_SPL_BUILD static int pf0100_prog(void) { + int rc; + struct udevice *dev = NULL; unsigned char bus = 1; unsigned char val; unsigned int i; @@ -177,9 +229,10 @@ static int pf0100_prog(void) ARRAY_SIZE(pmic_prog_pads)); gpio_direction_output(PMIC_PROG_VOLTAGE, 0); - if (!((0 == i2c_set_bus_num(bus)) && - (0 == i2c_probe(PFUZE100_I2C_ADDR)))) { - puts("i2c bus failed\n"); + rc = i2c_get_chip_for_busnum(bus, PFUZE100_I2C_ADDR, 1, &dev); + if (rc) { + printf("failed to get device for PMIC at address 0x%x\n", + PFUZE100_I2C_ADDR); return CMD_RET_FAILURE; } @@ -187,8 +240,7 @@ static int pf0100_prog(void) switch (pmic_otp_prog[i].cmd) { case pmic_i2c: val = (unsigned char) (pmic_otp_prog[i].value & 0xff); - if (i2c_write(PFUZE100_I2C_ADDR, pmic_otp_prog[i].reg, - 1, &val, 1)) { + if (dm_i2c_write(dev, pmic_otp_prog[i].reg, &val, 1)) { printf("i2c write failed, reg 0x%2x, value 0x%2x\n", pmic_otp_prog[i].reg, val); return CMD_RET_FAILURE; @@ -227,4 +279,4 @@ U_BOOT_CMD( "Program the OTP fuses on the PMIC PF0100", "" ); -#endif +#endif /* CONFIG_SPL_BUILD */ diff --git a/board/toradex/apalis_imx6/pf0100.h b/board/toradex/apalis_imx6/pf0100.h index c0efb79bbc..9257620511 100644 --- a/board/toradex/apalis_imx6/pf0100.h +++ b/board/toradex/apalis_imx6/pf0100.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2014-2016, Toradex AG + * Copyright (C) 2014-2019, Toradex AG */ /* @@ -10,11 +10,23 @@ #ifndef PF0100_H_ #define PF0100_H_ +/* bit definitions */ +#define PFUZE100_BIT_0 (0x01 << 0) +#define PFUZE100_BIT_1 (0x01 << 1) +#define PFUZE100_BIT_2 (0x01 << 2) +#define PFUZE100_BIT_3 (0x01 << 3) +#define PFUZE100_BIT_4 (0x01 << 4) +#define PFUZE100_BIT_5 (0x01 << 5) +#define PFUZE100_BIT_6 (0x01 << 6) +#define PFUZE100_BIT_7 (0x01 << 7) + /* 7-bit I2C bus slave address */ #define PFUZE100_I2C_ADDR (0x08) /* Register Addresses */ #define PFUZE100_DEVICEID (0x0) #define PFUZE100_REVID (0x3) +#define PFUZE100_INTSTAT3 (0xe) +#define PFUZE100_BIT_OTP_ECCI PFUZE100_BIT_7 #define PFUZE100_SW1AMODE (0x23) #define PFUZE100_SW1ACON 36 #define PFUZE100_SW1ACON_SPEED_VAL (0x1<<6) /*default */ @@ -39,12 +51,55 @@ #define PFUZE100_PAGE_REGISTER_PAGE2 (0x02 & PFUZE100_PAGE_REGISTER_PAGE_M) /* extended page 1 */ +#define PFUZE100_OTP_ECC_SE1 0x8a +#define PFUZE100_BIT_ECC1_SE PFUZE100_BIT_0 +#define PFUZE100_BIT_ECC2_SE PFUZE100_BIT_1 +#define PFUZE100_BIT_ECC3_SE PFUZE100_BIT_2 +#define PFUZE100_BIT_ECC4_SE PFUZE100_BIT_3 +#define PFUZE100_BIT_ECC5_SE PFUZE100_BIT_4 +#define PFUZE100_BITS_ECC_SE1 ((PFUZE100_BIT_ECC1_SE) | \ + (PFUZE100_BIT_ECC2_SE) | \ + (PFUZE100_BIT_ECC3_SE) | \ + (PFUZE100_BIT_ECC4_SE) | \ + (PFUZE100_BIT_ECC5_SE)) +#define PFUZE100_OTP_ECC_SE2 0x8b +#define PFUZE100_BIT_ECC6_SE PFUZE100_BIT_0 +#define PFUZE100_BIT_ECC7_SE PFUZE100_BIT_1 +#define PFUZE100_BIT_ECC8_SE PFUZE100_BIT_2 +#define PFUZE100_BIT_ECC9_SE PFUZE100_BIT_3 +#define PFUZE100_BIT_ECC10_SE PFUZE100_BIT_4 +#define PFUZE100_BITS_ECC_SE2 ((PFUZE100_BIT_ECC6_SE) | \ + (PFUZE100_BIT_ECC7_SE) | \ + (PFUZE100_BIT_ECC8_SE) | \ + (PFUZE100_BIT_ECC9_SE) | \ + (PFUZE100_BIT_ECC10_SE)) +#define PFUZE100_OTP_ECC_DE1 0x8c +#define PFUZE100_BIT_ECC1_DE PFUZE100_BIT_0 +#define PFUZE100_BIT_ECC2_DE PFUZE100_BIT_1 +#define PFUZE100_BIT_ECC3_DE PFUZE100_BIT_2 +#define PFUZE100_BIT_ECC4_DE PFUZE100_BIT_3 +#define PFUZE100_BIT_ECC5_DE PFUZE100_BIT_4 +#define PFUZE100_BITS_ECC_DE1 ((PFUZE100_BIT_ECC1_DE) | \ + (PFUZE100_BIT_ECC2_DE) | \ + (PFUZE100_BIT_ECC3_DE) | \ + (PFUZE100_BIT_ECC4_DE) | \ + (PFUZE100_BIT_ECC5_DE)) +#define PFUZE100_OTP_ECC_DE2 0x8d +#define PFUZE100_BIT_ECC6_DE PFUZE100_BIT_0 +#define PFUZE100_BIT_ECC7_DE PFUZE100_BIT_1 +#define PFUZE100_BIT_ECC8_DE PFUZE100_BIT_2 +#define PFUZE100_BIT_ECC9_DE PFUZE100_BIT_3 +#define PFUZE100_BIT_ECC10_DE PFUZE100_BIT_4 +#define PFUZE100_BITS_ECC_DE2 ((PFUZE100_BIT_ECC6_DE) | \ + (PFUZE100_BIT_ECC7_DE) | \ + (PFUZE100_BIT_ECC8_DE) | \ + (PFUZE100_BIT_ECC9_DE) | \ + (PFUZE100_BIT_ECC10_DE)) #define PFUZE100_FUSE_POR1 0xe4 #define PFUZE100_FUSE_POR2 0xe5 #define PFUZE100_FUSE_POR3 0xe6 #define PFUZE100_FUSE_POR_M (0x1 << 1) - /* output some informational messages, return the number FUSE_POR=1 */ /* i.e. 0: unprogrammed, 3: programmed, other: undefined prog. state */ unsigned pmic_init(void); diff --git a/board/toradex/colibri_imx6/800mhz_2x64mx16.cfg b/board/toradex/colibri_imx6/800mhz_2x64mx16.cfg deleted file mode 100644 index c9407143d2..0000000000 --- a/board/toradex/colibri_imx6/800mhz_2x64mx16.cfg +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2014-2016, Toradex AG - */ - -DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D -DATA 4, MX6_MMDC_P0_MDCFG0, 0x2C305503 -DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66D8D63 -DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB -DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 -DATA 4, MX6_MMDC_P0_MDOR, 0x00301023 -DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 -DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D -/* CS0 End: 7MSB of ((0x10000000 + 512M) -1) >> 25 */ -DATA 4, MX6_MMDC_P0_MDASP, 0x00000017 -/* DDR3 DATA BUS SIZE: 64BIT */ -/* DATA 4, MX6_MMDC_P0_MDCTL, 0x821A0000 */ -/* DDR3 DATA BUS SIZE: 32BIT */ -DATA 4, MX6_MMDC_P0_MDCTL, 0x82190000 - -/* Write commands to DDR */ -/* Load Mode Registers */ -/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/ -/* DATA 4, MX6_MMDC_P0_MDSCR, 0x04408032 */ -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 -DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030 -/* ZQ calibration */ -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 - -DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 -DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 -DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 - -DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000000 -DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000 - -DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42360232 -DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021F022A -DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x421E0224 -DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02110218 - -DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x41434344 -DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4345423E -DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x39383339 -DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3E363930 - -DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00340039 -DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D -DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00120019 -DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D - -DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 -DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 -DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/toradex/colibri_imx6/800mhz_4x64mx16.cfg b/board/toradex/colibri_imx6/800mhz_4x64mx16.cfg deleted file mode 100644 index c319d2a729..0000000000 --- a/board/toradex/colibri_imx6/800mhz_4x64mx16.cfg +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2014-2016, Toradex AG - */ - -DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D -DATA 4, MX6_MMDC_P0_MDCFG0, 0x2C305503 -DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66D8D63 -DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB -DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 -DATA 4, MX6_MMDC_P0_MDOR, 0x00301023 -DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 -DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D -/* CS0 End: 7MSB of ((0x10000000 + 512M) -1) >> 25 */ -DATA 4, MX6_MMDC_P0_MDASP, 0x00000017 -/* DDR3 DATA BUS SIZE: 64BIT */ -DATA 4, MX6_MMDC_P0_MDCTL, 0x821A0000 -/* DDR3 DATA BUS SIZE: 32BIT */ -/* DATA 4, MX6_MMDC_P0_MDCTL, 0x82190000 */ - -/* Write commands to DDR */ -/* Load Mode Registers */ -/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/ -/* DATA 4, MX6_MMDC_P0_MDSCR, 0x04408032 */ -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 -DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030 -/* ZQ calibration */ -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 - -DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 -DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 -DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 - -DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000000 -DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000 - -DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42360232 -DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021F022A -DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x421E0224 -DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02110218 - -DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x41434344 -DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4345423E -DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x39383339 -DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3E363930 - -DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00340039 -DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D -DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00120019 -DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D - -DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 -DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 -DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/toradex/colibri_imx6/MAINTAINERS b/board/toradex/colibri_imx6/MAINTAINERS index 1cc7ef2e71..e25c07306c 100644 --- a/board/toradex/colibri_imx6/MAINTAINERS +++ b/board/toradex/colibri_imx6/MAINTAINERS @@ -1,8 +1,9 @@ Colibri iMX6 M: Max Krummenacher <max.krummenacher@toradex.com> W: http://developer.toradex.com/software/linux/linux-software +W: https://www.toradex.com/community S: Maintained F: board/toradex/colibri_imx6/ F: include/configs/colibri_imx6.h F: configs/colibri_imx6_defconfig -F: configs/colibri_imx6_nospl_defconfig +F: arch/arm/dts/imx6-colibri.dts diff --git a/board/toradex/colibri_imx6/clocks.cfg b/board/toradex/colibri_imx6/clocks.cfg deleted file mode 100644 index 1bcbc4fa38..0000000000 --- a/board/toradex/colibri_imx6/clocks.cfg +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2014-2016, Toradex AG - * - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -/* set the default clock gate to save power */ -DATA 4, CCM_CCGR0, 0x00C03F3F -DATA 4, CCM_CCGR1, 0x0030FC03 -DATA 4, CCM_CCGR2, 0x0FFFC000 -DATA 4, CCM_CCGR3, 0x3FF00000 -DATA 4, CCM_CCGR4, 0x00FFF300 -DATA 4, CCM_CCGR5, 0x0F0000C3 -DATA 4, CCM_CCGR6, 0x000003FF - -/* enable AXI cache for VDOA/VPU/IPU */ -DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -DATA 4, MX6_IOMUXC_GPR6, 0x007F007F -DATA 4, MX6_IOMUXC_GPR7, 0x007F007F - -/* - * Setup CCM_CCOSR register as follows: - * - * cko1_en = 1 --> CKO1 enabled - * cko1_div = 111 --> divide by 8 - * cko1_sel = 1011 --> ahb_clk_root - * - * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz - */ -DATA 4, CCM_CCOSR, 0x000000fb diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c index 17876f27e9..c634e3243d 100644 --- a/board/toradex/colibri_imx6/colibri_imx6.c +++ b/board/toradex/colibri_imx6/colibri_imx6.c @@ -2,40 +2,35 @@ /* * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com> - * Copyright (C) 2014-2016, Toradex AG + * Copyright (C) 2014-2019, Toradex AG * copied from nitrogen6x */ #include <common.h> #include <dm.h> + #include <asm/arch/clock.h> #include <asm/arch/crm_regs.h> #include <asm/arch/imx-regs.h> -#include <asm/arch/iomux.h> -#include <asm/arch/mx6-pins.h> #include <asm/arch/mx6-ddr.h> +#include <asm/arch/mx6-pins.h> #include <asm/arch/mxc_hdmi.h> #include <asm/arch/sys_proto.h> #include <asm/bootm.h> #include <asm/gpio.h> +#include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/mxc_i2c.h> #include <asm/mach-imx/sata.h> -#include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/video.h> -#include <asm/io.h> +#include <cpu.h> #include <dm/platform_data/serial_mxc.h> -#include <dm/platdata.h> +#include <environment.h> #include <fsl_esdhc.h> -#include <i2c.h> -#include <input.h> #include <imx_thermal.h> -#include <linux/errno.h> -#include <malloc.h> #include <micrel.h> #include <miiphy.h> -#include <mmc.h> #include <netdev.h> +#include <cpu.h> #include "../common/tdx-cfg-block.h" #ifdef CONFIG_TDX_CMD_IMX_MFGR @@ -49,22 +44,16 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SRE_FAST | PAD_CTL_HYS) #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) -#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_SRE_SLOW) @@ -77,8 +66,6 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_HYS | PAD_CTL_SRE_SLOW) -#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) - #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST) int dram_init(void) @@ -96,36 +83,8 @@ iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -/* Colibri I2C */ -struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC, - .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC, - .gp = IMX_GPIO_NR(1, 3) - }, - .sda = { - .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC, - .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC, - .gp = IMX_GPIO_NR(1, 6) - } -}; - -/* Colibri local, PMIC, SGTL5000, STMPE811 */ -struct i2c_pads_info i2c_pad_info_loc = { - .scl = { - .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC, - .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, - .gp = IMX_GPIO_NR(2, 30) - }, - .sda = { - .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC, - .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC, - .gp = IMX_GPIO_NR(3, 16) - } -}; - -/* Apalis MMC */ +#if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD) +/* Colibri MMC */ iomux_v3_cfg_t const usdhc1_pads[] = { MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -139,18 +98,19 @@ iomux_v3_cfg_t const usdhc1_pads[] = { /* eMMC */ iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; +#endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */ iomux_v3_cfg_t const enet_pads[] = { MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), @@ -173,68 +133,123 @@ static void setup_iomux_enet(void) /* mux auxiliary pins to GPIO, so they can be used from the U-Boot cmdline */ iomux_v3_cfg_t const gpio_pads[] = { /* ADDRESS[17:18] [25] used as GPIO */ - MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, /* ADDRESS[19:24] used as GPIO */ - MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_DISP0_DAT22__GPIO5_IO16 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_DISP0_DAT21__GPIO5_IO15 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_DISP0_DAT19__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_DISP0_DAT22__GPIO5_IO16 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_DISP0_DAT21__GPIO5_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_DISP0_DAT19__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, /* DATA[16:29] [31] used as GPIO */ - MX6_PAD_EIM_LBA__GPIO2_IO27 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_CSI0_MCLK__GPIO5_IO19 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_EIM_LBA__GPIO2_IO27 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_CSI0_MCLK__GPIO5_IO19 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, /* DQM[0:3] used as GPIO */ - MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_EIM_EB1__GPIO2_IO29 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_SD2_DAT2__GPIO1_IO13 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_EIM_EB1__GPIO2_IO29 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_SD2_DAT2__GPIO1_IO13 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, /* RDY used as GPIO */ - MX6_PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, /* ADDRESS[16] DATA[30] used as GPIO */ - MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(WEAK_PULLDOWN), - MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(WEAK_PULLDOWN) | + MUX_MODE_SION, + MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, /* CSI pins used as GPIO */ - MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_SD2_CMD__GPIO1_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_EIM_D18__GPIO3_IO18 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(WEAK_PULLDOWN), - MX6_PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_EIM_A18__GPIO2_IO20 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_EIM_D17__GPIO3_IO17 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_SD2_CMD__GPIO1_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_EIM_D18__GPIO3_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(WEAK_PULLDOWN) | + MUX_MODE_SION, + MX6_PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_EIM_A18__GPIO2_IO20 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_EIM_D17__GPIO3_IO17 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, /* GPIO */ - MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_EIM_D27__GPIO3_IO27 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_ENET_REF_CLK__GPIO1_IO23 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_EIM_D27__GPIO3_IO27 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_ENET_REF_CLK__GPIO1_IO23 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, /* USBH_OC */ MX6_PAD_EIM_D30__GPIO3_IO30 | MUX_PAD_CTRL(WEAK_PULLUP), /* USBC_ID */ @@ -249,8 +264,8 @@ static void setup_iomux_gpio(void) } iomux_v3_cfg_t const usb_pads[] = { - /* USB_PE */ - MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* USBH_PEN */ + MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION, # define GPIO_USBH_EN IMX_GPIO_NR(3, 31) }; @@ -258,14 +273,21 @@ iomux_v3_cfg_t const usb_pads[] = { * UARTs are used in DTE mode, switch the mode on all UARTs before * any pinmuxing connects a (DCE) output to a transceiver output. */ +#define UCR3 0x88 /* FIFO Control Register */ +#define UCR3_RI BIT(8) /* RIDELT DTE mode */ +#define UCR3_DCD BIT(9) /* DCDDELT DTE mode */ #define UFCR 0x90 /* FIFO Control Register */ -#define UFCR_DCEDTE (1<<6) /* DCE=0 */ +#define UFCR_DCEDTE BIT(6) /* DCE=0 */ static void setup_dtemode_uart(void) { setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE); setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE); setbits_le32((u32 *)(UART3_BASE + UFCR), UFCR_DCEDTE); + + clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI); + clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI); + clrbits_le32((u32 *)(UART3_BASE + UCR3), UCR3_DCD | UCR3_RI); } static void setup_iomux_uart(void) @@ -280,29 +302,9 @@ int board_ehci_hcd_init(int port) imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); return 0; } - -int board_ehci_power(int port, int on) -{ - switch (port) { - case 0: - /* control OTG power */ - /* No special PE for USBC, always on when ID pin signals - host mode */ - break; - case 1: - /* Control MXM USBH */ - /* Set MXM USBH power enable, '0' means on */ - gpio_direction_output(GPIO_USBH_EN, !on); - mdelay(100); - break; - default: - break; - } - return 0; -} #endif -#ifdef CONFIG_FSL_ESDHC +#if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD) /* use the following sequence: eMMC, MMC */ struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { {USDHC3_BASE_ADDR}, @@ -316,6 +318,7 @@ int board_mmc_getcd(struct mmc *mmc) switch (cfg->esdhc_base) { case USDHC1_BASE_ADDR: + gpio_request(GPIO_MMC_CD, "MMC_CD"); gpio_direction_input(GPIO_MMC_CD); ret = !gpio_get_value(GPIO_MMC_CD); break; @@ -326,37 +329,6 @@ int board_mmc_getcd(struct mmc *mmc) int board_mmc_init(bd_t *bis) { -#ifndef CONFIG_SPL_BUILD - s32 status = 0; - u32 index = 0; - - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - - usdhc_cfg[0].max_bus_width = 8; - usdhc_cfg[1].max_bus_width = 4; - - for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { - switch (index) { - case 0: - imx_iomux_v3_setup_multiple_pads( - usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - break; - case 1: - imx_iomux_v3_setup_multiple_pads( - usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); - break; - default: - printf("Warning: you configured more USDHC controllers (%d) then supported by the board (%d)\n", - index + 1, CONFIG_SYS_FSL_USDHC_NUM); - return status; - } - - status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); - } - - return status; -#else struct src *psrc = (struct src *)SRC_BASE_ADDR; unsigned reg = readl(&psrc->sbmr1) >> 11; /* @@ -388,9 +360,8 @@ int board_mmc_init(bd_t *bis) } return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -#endif } -#endif +#endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */ int board_phy_config(struct phy_device *phydev) { @@ -412,6 +383,7 @@ int board_eth_init(bd_t *bis) ret = enable_fec_anatop_clock(0, ENET_50MHZ); if (ret) return ret; + /* set gpr1[ENET_CLK_SEL] */ setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); @@ -421,6 +393,7 @@ int board_eth_init(bd_t *bis) bus = fec_get_miibus(base, -1); if (!bus) return 0; + /* scan PHY 1..7 */ phydev = phy_find_by_mask(bus, 0xff, PHY_INTERFACE_MODE_RMII); if (!phydev) { @@ -428,6 +401,7 @@ int board_eth_init(bd_t *bis) puts("no PHY found\n"); return 0; } + phy_reset(phydev); printf("using PHY at %d\n", phydev->addr); ret = fec_probe(bis, -1, base, bus, phydev); @@ -436,7 +410,8 @@ int board_eth_init(bd_t *bis) free(phydev); free(bus); } -#endif +#endif /* CONFIG_FEC_MXC */ + return 0; } @@ -452,11 +427,12 @@ static iomux_v3_cfg_t const pwr_intb_pads[] = { static iomux_v3_cfg_t const backlight_pads[] = { /* Backlight On */ - MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION, #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 26) /* Backlight PWM, used as GPIO in U-Boot */ MX6_PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PULLUP), - MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL) | + MUX_MODE_SION, #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 9) }; @@ -619,6 +595,8 @@ static void setup_display(void) imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads)); /* use 0 for EDT 7", use 1 for LG fullHD panel */ + gpio_request(RGB_BACKLIGHTPWM_GP, "PWM<A>"); + gpio_request(RGB_BACKLIGHT_GP, "BL_ON"); gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0); gpio_direction_output(RGB_BACKLIGHT_GP, 1); } @@ -656,9 +634,6 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info_loc); - #if defined(CONFIG_VIDEO_IPUV3) setup_display(); #endif @@ -689,16 +664,17 @@ int board_late_init(void) env_set("board_rev", env_str); #endif - return 0; -} -#endif /* CONFIG_BOARD_LATE_INIT */ +#ifdef CONFIG_CMD_USB_SDP + if (is_boot_from_usb()) { + printf("Serial Downloader recovery mode, using sdp command\n"); + env_set("bootdelay", "0"); + env_set("bootcmd", "sdp 0"); + } +#endif /* CONFIG_CMD_USB_SDP */ -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_SYSTEM_SETUP) -int ft_system_setup(void *blob, bd_t *bd) -{ return 0; } -#endif +#endif /* CONFIG_BOARD_LATE_INIT */ int checkboard(void) { @@ -722,7 +698,18 @@ int checkboard(void) #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, bd_t *bd) { - return ft_common_board_setup(blob, bd); + u32 cma_size; + + ft_common_board_setup(blob, bd); + + cma_size = env_get_ulong("cma-size", 10, 320 * 1024 * 1024); + cma_size = min((u32)(gd->ram_size >> 1), cma_size); + + fdt_setprop_u32(blob, + fdt_path_offset(blob, "/reserved-memory/linux,cma"), + "size", + cma_size); + return 0; } #endif @@ -1073,6 +1060,7 @@ static void spl_dram_init(void) case TEMP_AUTOMOTIVE: default: if (is_cpu_type(MXC_CPU_MX6DL)) { + puts("Industrial temperature grade DDR3 timings, 64bit bus width.\n"); ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table)); } else { puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n"); @@ -1083,6 +1071,26 @@ static void spl_dram_init(void) udelay(100); } +static iomux_v3_cfg_t const gpio_reset_pad[] = { + MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL) | + MUX_MODE_SION +#define GPIO_NRESET IMX_GPIO_NR(6, 27) +}; + +#define IMX_RESET_CAUSE_POR 0x00011 +static void nreset_out(void) +{ + int reset_cause = get_imx_reset_cause(); + + if (reset_cause != IMX_RESET_CAUSE_POR) { + imx_iomux_v3_setup_multiple_pads(gpio_reset_pad, + ARRAY_SIZE(gpio_reset_pad)); + gpio_direction_output(GPIO_NRESET, 1); + udelay(100); + gpio_direction_output(GPIO_NRESET, 0); + } +} + void board_init_f(ulong dummy) { /* setup AIPS and disable watchdog */ @@ -1091,7 +1099,7 @@ void board_init_f(ulong dummy) ccgr_init(); gpr_init(); - /* iomux and setup of i2c */ + /* iomux */ board_early_init_f(); /* setup GP timer */ @@ -1109,6 +1117,9 @@ void board_init_f(ulong dummy) /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); + /* Assert nReset_Out */ + nreset_out(); + /* load/boot image from boot device */ board_init_r(NULL, 0); } @@ -1117,7 +1128,7 @@ void reset_cpu(ulong addr) { } -#endif +#endif /* CONFIG_SPL_BUILD */ static struct mxc_serial_platdata mxc_serial_plat = { .reg = (struct mxc_uart *)UART1_BASE, diff --git a/board/toradex/colibri_imx6/colibri_imx6.cfg b/board/toradex/colibri_imx6/colibri_imx6.cfg deleted file mode 100644 index 517c5eb107..0000000000 --- a/board/toradex/colibri_imx6/colibri_imx6.cfg +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2014 Toradex AG - * - * Refer doc/README.imximage for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* image version */ -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ -BOOT_FROM sd - -#define __ASSEMBLY__ -#include <config.h> -#include "asm/arch/mx6-ddr.h" -#include "asm/arch/iomux.h" -#include "asm/arch/crm_regs.h" - -#include "ddr-setup.cfg" - -#if CONFIG_DDR_MB == 256 -#include "800mhz_2x64mx16.cfg" -#elif CONFIG_DDR_MB == 512 -#include "800mhz_4x64mx16.cfg" -#else -#error "unknown DDR size" -#endif - -#include "clocks.cfg" diff --git a/board/toradex/colibri_imx6/ddr-setup.cfg b/board/toradex/colibri_imx6/ddr-setup.cfg deleted file mode 100644 index a943fd228c..0000000000 --- a/board/toradex/colibri_imx6/ddr-setup.cfg +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2014-2016, Toradex AG - * - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -/* - * DDR3 settings - * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock), - * memory bus width: 64 bits x16/x32/x64 - * MX6DL ddr is limited to 800 MHz(400 MHz clock) - * memory bus width: 64 bits x16/x32/x64 - * MX6SOLO ddr is limited to 800 MHz(400 MHz clock) - * memory bus width: 32 bits x16/x32 - */ -DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 - -DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 -DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 -/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ -DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 - -DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 - -DATA 4, MX6_IOM_DRAM_CAS, 0x00020030 -DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 -DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 -DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 - -DATA 4, MX6_IOM_DRAM_RESET, 0x00020030 -DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 -DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 - -DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 -DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 - -/* (differential input) */ -DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 -/* (differential input) */ -DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 -/* disable ddr pullups */ -DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 -DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 -/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ -DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 - -/* Read data DQ Byte0-3 delay */ -DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 - -/* - * MDMISC mirroring interleaved (row/bank/col) - */ -/* TODO: check what the RALAT field does */ -DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 - -/* - * MDSCR con_req - */ -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 diff --git a/board/toradex/colibri_imx6/do_fuse.c b/board/toradex/colibri_imx6/do_fuse.c index e6793e366a..22d191f52a 100644 --- a/board/toradex/colibri_imx6/do_fuse.c +++ b/board/toradex/colibri_imx6/do_fuse.c @@ -29,7 +29,7 @@ static int mfgr_fuse(void) return CMD_RET_FAILURE; } /* boot cfg */ - fuse_prog(0, 5, 0x00005072); + fuse_prog(0, 5, 0x00005062); /* BT_FUSE_SEL */ fuse_prog(0, 6, 0x00000010); return CMD_RET_SUCCESS; diff --git a/board/toradex/colibri_imx6/pf0100.c b/board/toradex/colibri_imx6/pf0100.c index fa63865670..e744243297 100644 --- a/board/toradex/colibri_imx6/pf0100.c +++ b/board/toradex/colibri_imx6/pf0100.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2014-2016, Toradex AG + * Copyright (C) 2014-2019, Toradex AG */ /* @@ -21,6 +21,8 @@ /* define for PMIC register dump */ /*#define DEBUG */ +#define WARNBAR "@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\n" + /* use GPIO: EXT_IO1 to switch on VPGM, ON: 1 */ static __maybe_unused iomux_v3_cfg_t const pmic_prog_pads[] = { MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL), @@ -29,37 +31,128 @@ static __maybe_unused iomux_v3_cfg_t const pmic_prog_pads[] = { unsigned pmic_init(void) { + int rc; + struct udevice *dev = NULL; unsigned programmed = 0; uchar bus = 1; uchar devid, revid, val; - puts("PMIC: "); - if (!((0 == i2c_set_bus_num(bus)) && - (0 == i2c_probe(PFUZE100_I2C_ADDR)))) { - puts("i2c bus failed\n"); + puts("PMIC: "); + rc = i2c_get_chip_for_busnum(bus, PFUZE100_I2C_ADDR, 1, &dev); + if (rc) { + printf("failed to get device for PMIC at address 0x%x\n", + PFUZE100_I2C_ADDR); + return 0; + } + + /* check for errors in PMIC fuses */ + if (dm_i2c_read(dev, PFUZE100_INTSTAT3, &val, 1) < 0) { + puts("i2c pmic INTSTAT3 register read failed\n"); return 0; } + if (val & PFUZE100_BIT_OTP_ECCI) { + puts("\n" WARNBAR); + puts("WARNING: ecc errors found in pmic fuse banks\n"); + puts(WARNBAR); + } + if (dm_i2c_read(dev, PFUZE100_OTP_ECC_SE1, &val, 1) < 0) { + puts("i2c pmic ECC_SE1 register read failed\n"); + return 0; + } + if (val & PFUZE100_BITS_ECC_SE1) { + puts(WARNBAR); + puts("WARNING: ecc has made bit corrections in banks 1 to 5\n"); + puts(WARNBAR); + } + if (dm_i2c_read(dev, PFUZE100_OTP_ECC_SE2, &val, 1) < 0) { + puts("i2c pmic ECC_SE2 register read failed\n"); + return 0; + } + if (val & PFUZE100_BITS_ECC_SE2) { + puts(WARNBAR); + puts("WARNING: ecc has made bit corrections in banks 6 to 10\n" + ); + puts(WARNBAR); + } + if (dm_i2c_read(dev, PFUZE100_OTP_ECC_DE1, &val, 1) < 0) { + puts("i2c pmic ECC_DE register read failed\n"); + return 0; + } + if (val & PFUZE100_BITS_ECC_DE1) { + puts(WARNBAR); + puts("ERROR: banks 1 to 5 have uncorrectable bits\n"); + puts(WARNBAR); + } + if (dm_i2c_read(dev, PFUZE100_OTP_ECC_DE2, &val, 1) < 0) { + puts("i2c pmic ECC_DE register read failed\n"); + return 0; + } + if (val & PFUZE100_BITS_ECC_DE2) { + puts(WARNBAR); + puts("ERROR: banks 6 to 10 have uncorrectable bits\n"); + puts(WARNBAR); + } + /* get device ident */ - if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_DEVICEID, 1, &devid, 1) < 0) { + if (dm_i2c_read(dev, PFUZE100_DEVICEID, &devid, 1) < 0) { puts("i2c pmic devid read failed\n"); return 0; } - if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_REVID, 1, &revid, 1) < 0) { + if (dm_i2c_read(dev, PFUZE100_REVID, &revid, 1) < 0) { puts("i2c pmic revid read failed\n"); return 0; } - printf("device id: 0x%.2x, revision id: 0x%.2x\n", devid, revid); + printf("device id: 0x%.2x, revision id: 0x%.2x, ", devid, revid); + + /* get device programmed state */ + val = PFUZE100_PAGE_REGISTER_PAGE1; + if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) { + puts("i2c write failed\n"); + return 0; + } + if (dm_i2c_read(dev, PFUZE100_FUSE_POR1, &val, 1) < 0) { + puts("i2c fuse_por read failed\n"); + return 0; + } + if (val & PFUZE100_FUSE_POR_M) + programmed++; + + if (dm_i2c_read(dev, PFUZE100_FUSE_POR2, &val, 1) < 0) { + puts("i2c fuse_por read failed\n"); + return programmed; + } + if (val & PFUZE100_FUSE_POR_M) + programmed++; + + if (dm_i2c_read(dev, PFUZE100_FUSE_POR3, &val, 1) < 0) { + puts("i2c fuse_por read failed\n"); + return programmed; + } + if (val & PFUZE100_FUSE_POR_M) + programmed++; + + switch (programmed) { + case 0: + puts("not programmed\n"); + break; + case 3: + puts("programmed\n"); + break; + default: + puts("undefined programming state\n"); + break; + } #ifdef DEBUG { - unsigned i, j; + unsigned int i, j; for (i = 0; i < 16; i++) printf("\t%x", i); for (j = 0; j < 0x80; ) { printf("\n%2x", j); for (i = 0; i < 16; i++) { - i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1); + dm_i2c_read(dev, j + i, &val, 1); printf("\t%2x", val); } j += 0x10; @@ -67,8 +160,7 @@ unsigned pmic_init(void) printf("\nEXT Page 1"); val = PFUZE100_PAGE_REGISTER_PAGE1; - if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, - &val, 1)) { + if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) { puts("i2c write failed\n"); return 0; } @@ -76,7 +168,7 @@ unsigned pmic_init(void) for (j = 0x80; j < 0x100; ) { printf("\n%2x", j); for (i = 0; i < 16; i++) { - i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1); + dm_i2c_read(dev, j + i, &val, 1); printf("\t%2x", val); } j += 0x10; @@ -84,8 +176,7 @@ unsigned pmic_init(void) printf("\nEXT Page 2"); val = PFUZE100_PAGE_REGISTER_PAGE2; - if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, - &val, 1)) { + if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) { puts("i2c write failed\n"); return 0; } @@ -93,52 +184,14 @@ unsigned pmic_init(void) for (j = 0x80; j < 0x100; ) { printf("\n%2x", j); for (i = 0; i < 16; i++) { - i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1); + dm_i2c_read(dev, j + i, &val, 1); printf("\t%2x", val); } j += 0x10; } printf("\n"); } -#endif - /* get device programmed state */ - val = PFUZE100_PAGE_REGISTER_PAGE1; - if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, &val, 1)) { - puts("i2c write failed\n"); - return 0; - } - if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR1, 1, &val, 1) < 0) { - puts("i2c fuse_por read failed\n"); - return 0; - } - if (val & PFUZE100_FUSE_POR_M) - programmed++; - - if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR2, 1, &val, 1) < 0) { - puts("i2c fuse_por read failed\n"); - return programmed; - } - if (val & PFUZE100_FUSE_POR_M) - programmed++; - - if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR3, 1, &val, 1) < 0) { - puts("i2c fuse_por read failed\n"); - return programmed; - } - if (val & PFUZE100_FUSE_POR_M) - programmed++; - - switch (programmed) { - case 0: - printf("PMIC: not programmed\n"); - break; - case 3: - printf("PMIC: programmed\n"); - break; - default: - printf("PMIC: undefined programming state\n"); - break; - } +#endif /* DEBUG */ return programmed; } @@ -146,6 +199,8 @@ unsigned pmic_init(void) #ifndef CONFIG_SPL_BUILD static int pf0100_prog(void) { + int rc; + struct udevice *dev = NULL; unsigned char bus = 1; unsigned char val; unsigned int i; @@ -159,9 +214,10 @@ static int pf0100_prog(void) ARRAY_SIZE(pmic_prog_pads)); gpio_direction_output(PMIC_PROG_VOLTAGE, 0); - if (!((0 == i2c_set_bus_num(bus)) && - (0 == i2c_probe(PFUZE100_I2C_ADDR)))) { - puts("i2c bus failed\n"); + rc = i2c_get_chip_for_busnum(bus, PFUZE100_I2C_ADDR, 1, &dev); + if (rc) { + printf("failed to get device for PMIC at address 0x%x\n", + PFUZE100_I2C_ADDR); return CMD_RET_FAILURE; } @@ -169,8 +225,7 @@ static int pf0100_prog(void) switch (pmic_otp_prog[i].cmd) { case pmic_i2c: val = (unsigned char) (pmic_otp_prog[i].value & 0xff); - if (i2c_write(PFUZE100_I2C_ADDR, pmic_otp_prog[i].reg, - 1, &val, 1)) { + if (dm_i2c_write(dev, pmic_otp_prog[i].reg, &val, 1)) { printf("i2c write failed, reg 0x%2x, value 0x%2x\n", pmic_otp_prog[i].reg, val); return CMD_RET_FAILURE; @@ -209,4 +264,4 @@ U_BOOT_CMD( "Program the OTP fuses on the PMIC PF0100", "" ); -#endif +#endif /* CONFIG_SPL_BUILD */ diff --git a/board/toradex/colibri_imx6/pf0100.h b/board/toradex/colibri_imx6/pf0100.h index c0efb79bbc..9257620511 100644 --- a/board/toradex/colibri_imx6/pf0100.h +++ b/board/toradex/colibri_imx6/pf0100.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2014-2016, Toradex AG + * Copyright (C) 2014-2019, Toradex AG */ /* @@ -10,11 +10,23 @@ #ifndef PF0100_H_ #define PF0100_H_ +/* bit definitions */ +#define PFUZE100_BIT_0 (0x01 << 0) +#define PFUZE100_BIT_1 (0x01 << 1) +#define PFUZE100_BIT_2 (0x01 << 2) +#define PFUZE100_BIT_3 (0x01 << 3) +#define PFUZE100_BIT_4 (0x01 << 4) +#define PFUZE100_BIT_5 (0x01 << 5) +#define PFUZE100_BIT_6 (0x01 << 6) +#define PFUZE100_BIT_7 (0x01 << 7) + /* 7-bit I2C bus slave address */ #define PFUZE100_I2C_ADDR (0x08) /* Register Addresses */ #define PFUZE100_DEVICEID (0x0) #define PFUZE100_REVID (0x3) +#define PFUZE100_INTSTAT3 (0xe) +#define PFUZE100_BIT_OTP_ECCI PFUZE100_BIT_7 #define PFUZE100_SW1AMODE (0x23) #define PFUZE100_SW1ACON 36 #define PFUZE100_SW1ACON_SPEED_VAL (0x1<<6) /*default */ @@ -39,12 +51,55 @@ #define PFUZE100_PAGE_REGISTER_PAGE2 (0x02 & PFUZE100_PAGE_REGISTER_PAGE_M) /* extended page 1 */ +#define PFUZE100_OTP_ECC_SE1 0x8a +#define PFUZE100_BIT_ECC1_SE PFUZE100_BIT_0 +#define PFUZE100_BIT_ECC2_SE PFUZE100_BIT_1 +#define PFUZE100_BIT_ECC3_SE PFUZE100_BIT_2 +#define PFUZE100_BIT_ECC4_SE PFUZE100_BIT_3 +#define PFUZE100_BIT_ECC5_SE PFUZE100_BIT_4 +#define PFUZE100_BITS_ECC_SE1 ((PFUZE100_BIT_ECC1_SE) | \ + (PFUZE100_BIT_ECC2_SE) | \ + (PFUZE100_BIT_ECC3_SE) | \ + (PFUZE100_BIT_ECC4_SE) | \ + (PFUZE100_BIT_ECC5_SE)) +#define PFUZE100_OTP_ECC_SE2 0x8b +#define PFUZE100_BIT_ECC6_SE PFUZE100_BIT_0 +#define PFUZE100_BIT_ECC7_SE PFUZE100_BIT_1 +#define PFUZE100_BIT_ECC8_SE PFUZE100_BIT_2 +#define PFUZE100_BIT_ECC9_SE PFUZE100_BIT_3 +#define PFUZE100_BIT_ECC10_SE PFUZE100_BIT_4 +#define PFUZE100_BITS_ECC_SE2 ((PFUZE100_BIT_ECC6_SE) | \ + (PFUZE100_BIT_ECC7_SE) | \ + (PFUZE100_BIT_ECC8_SE) | \ + (PFUZE100_BIT_ECC9_SE) | \ + (PFUZE100_BIT_ECC10_SE)) +#define PFUZE100_OTP_ECC_DE1 0x8c +#define PFUZE100_BIT_ECC1_DE PFUZE100_BIT_0 +#define PFUZE100_BIT_ECC2_DE PFUZE100_BIT_1 +#define PFUZE100_BIT_ECC3_DE PFUZE100_BIT_2 +#define PFUZE100_BIT_ECC4_DE PFUZE100_BIT_3 +#define PFUZE100_BIT_ECC5_DE PFUZE100_BIT_4 +#define PFUZE100_BITS_ECC_DE1 ((PFUZE100_BIT_ECC1_DE) | \ + (PFUZE100_BIT_ECC2_DE) | \ + (PFUZE100_BIT_ECC3_DE) | \ + (PFUZE100_BIT_ECC4_DE) | \ + (PFUZE100_BIT_ECC5_DE)) +#define PFUZE100_OTP_ECC_DE2 0x8d +#define PFUZE100_BIT_ECC6_DE PFUZE100_BIT_0 +#define PFUZE100_BIT_ECC7_DE PFUZE100_BIT_1 +#define PFUZE100_BIT_ECC8_DE PFUZE100_BIT_2 +#define PFUZE100_BIT_ECC9_DE PFUZE100_BIT_3 +#define PFUZE100_BIT_ECC10_DE PFUZE100_BIT_4 +#define PFUZE100_BITS_ECC_DE2 ((PFUZE100_BIT_ECC6_DE) | \ + (PFUZE100_BIT_ECC7_DE) | \ + (PFUZE100_BIT_ECC8_DE) | \ + (PFUZE100_BIT_ECC9_DE) | \ + (PFUZE100_BIT_ECC10_DE)) #define PFUZE100_FUSE_POR1 0xe4 #define PFUZE100_FUSE_POR2 0xe5 #define PFUZE100_FUSE_POR3 0xe6 #define PFUZE100_FUSE_POR_M (0x1 << 1) - /* output some informational messages, return the number FUSE_POR=1 */ /* i.e. 0: unprogrammed, 3: programmed, other: undefined prog. state */ unsigned pmic_init(void); diff --git a/board/toradex/colibri_imx6/pf0100_otp.inc b/board/toradex/colibri_imx6/pf0100_otp.inc index ce29b95ae2..c3b1f67f81 100644 --- a/board/toradex/colibri_imx6/pf0100_otp.inc +++ b/board/toradex/colibri_imx6/pf0100_otp.inc @@ -5,16 +5,17 @@ // Register Output for PF0100 programmer // Customer: Toradex AG -// Program: Colibri iMX6 +// Program: Colibri iMX6 V1.1 // Sample marking: -// Date: 24.07.2015 -// Time: 10:52:58 +// Date: 01.05.2017 +// Time: 16:22:32 // Generated from Spreadsheet Revision: P1.8 -/* sed commands to get from programmer script to struct */ +/* sed commands to get from programmer script to struct content */ /* sed -e 's/^WRITE_I2C:\(..\):\(..\)/\{pmic_i2c, 0x\1, 0x\2\},/g' -e 's/^DELAY:\([0-9]*\)/\{pmic_delay, 0, \1\},/g' pf0100_otp_Colibri_iMX6.txt > pf0100_otp.inc sed -i -e 's/^VPGM:ON/\{pmic_vpgm, 0, 1},/g' -e 's/^VPGM:OFF/\{pmic_vpgm, 0, 0},/g' pf0100_otp.inc - sed -i -e 's/^PWRON: HIGH/\{pmic_pwr, 0, 1},/g' -e 's/^PWRON:LOW/\{pmic_pwr, 0, 0},/g' pf0100_otp.inc */ + sed -i -e 's/^PWRON: HIGH/\{pmic_pwr, 0, 1},/g' -e 's/^PWRON:LOW/\{pmic_pwr, 0, 0},/g' pf0100_otp.inc +*/ enum { pmic_i2c, pmic_delay, pmic_vpgm, pmic_pwr }; struct pmic_otp_prog_t{ @@ -47,7 +48,8 @@ struct pmic_otp_prog_t pmic_otp_prog[] = { {pmic_i2c, 0xC8, 0x0E}, // Auto gen from Row134 {pmic_i2c, 0xCC, 0x0E}, // Auto gen from Row138 {pmic_i2c, 0xCD, 0x05}, // Auto gen from Row139 -{pmic_i2c, 0xD0, 0x0C}, // Auto gen from Row142 +{pmic_i2c, 0xD0, 0x0F}, // Auto gen from Row142 +{pmic_i2c, 0xD1, 0x05}, // Auto gen from Row143 {pmic_i2c, 0xD5, 0x07}, // Auto gen from Row147 {pmic_i2c, 0xD8, 0x07}, // Auto gen from Row150 {pmic_i2c, 0xD9, 0x06}, // Auto gen from Row151 @@ -185,4 +187,4 @@ struct pmic_otp_prog_t pmic_otp_prog[] = { {pmic_delay, 0, 500}, {pmic_pwr, 0, 1}, #endif -};
\ No newline at end of file +}; diff --git a/board/toradex/colibri_vf/MAINTAINERS b/board/toradex/colibri_vf/MAINTAINERS index a1217a47bd..3ee2b33152 100644 --- a/board/toradex/colibri_vf/MAINTAINERS +++ b/board/toradex/colibri_vf/MAINTAINERS @@ -1,10 +1,12 @@ Colibri VFxx M: Stefan Agner <stefan.agner@toradex.com> +W: http://developer.toradex.com/software/linux/linux-software +W: https://www.toradex.com/community S: Maintained F: board/toradex/colibri_vf/ F: include/configs/colibri_vf.h F: configs/colibri_vf_defconfig -F: configs/colibri_vf_dtb_defconfig F: arch/arm/dts/vf-colibri.dtsi +F: arch/arm/dts/vf-colibri-u-boot.dtsi F: arch/arm/dts/vf500-colibri.dts F: arch/arm/dts/vf610-colibri.dts diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c index 79f702f2bf..9d63fbf3bd 100644 --- a/board/toradex/colibri_vf/colibri_vf.c +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -1,48 +1,41 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2015 Toradex, Inc. + * Copyright 2015-2019 Toradex, Inc. * * Based on vf610twr.c: * Copyright 2013 Freescale Semiconductor, Inc. */ #include <common.h> -#include <asm/io.h> + +#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/ddrmc-vf610.h> #include <asm/arch/imx-regs.h> #include <asm/arch/iomux-vf610.h> -#include <asm/arch/ddrmc-vf610.h> -#include <asm/arch/crm_regs.h> -#include <asm/arch/clock.h> -#include <mmc.h> +#include <asm/gpio.h> +#include <asm/io.h> #include <fdt_support.h> -#include <fsl_esdhc.h> #include <fsl_dcu_fb.h> +#include <g_dnl.h> #include <jffs2/load_kernel.h> -#include <miiphy.h> #include <mtd_node.h> -#include <netdev.h> -#include <i2c.h> -#include <g_dnl.h> -#include <asm/gpio.h> #include <usb.h> + #include "../common/tdx-common.h" DECLARE_GLOBAL_DATA_PTR; -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE) - -#define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \ - PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE) - -#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ - PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE) - -#define USB_PEN_GPIO 83 -#define USB_CDET_GPIO 102 #define PTC0_GPIO_45 45 static struct ddrmc_cr_setting colibri_vf_cr_settings[] = { + { DDRMC_CR79_CTLUPD_AREF(1), 79 }, + /* sets manual values for read lvl. (gate) delay of data slice 0/1 */ + { DDRMC_CR105_RDLVL_DL_0(28), 105 }, + { DDRMC_CR106_RDLVL_GTDL_0(24), 106 }, + { DDRMC_CR110_RDLVL_DL_1(28) | DDRMC_CR110_RDLVL_GTDL_1(24), 110 }, + { DDRMC_CR102_RDLVL_GT_REGEN | DDRMC_CR102_RDLVL_REG_EN, 102 }, + /* AXI */ { DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 }, { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 }, @@ -89,11 +82,6 @@ static struct ddrmc_cr_setting colibri_vf_cr_settings[] = { { 0, -1 } }; -static const iomux_v3_cfg_t usb_pads[] = { - VF610_PAD_PTD4__GPIO_83, - VF610_PAD_PTC29__GPIO_102, -}; - int dram_init(void) { static const struct ddr3_jedec_timings timings = { @@ -120,15 +108,21 @@ int dram_init(void) .tras_lockout = 0, .tdal = 12, .bstlen = 3, - .tdll = 512, + .tdll = 512, /* not applicable since freq. scaling + * is not used + */ .trp_ab = 6, .tref = 3120, .trfc = 64, .tref_int = 0, .tpdex = 3, .txpdll = 10, - .txsnr = 48, - .txsr = 468, + .txsnr = 68, /* changed to conform to JEDEC + * specifications + */ + .txsr = 506, /* changed to conform to JEDEC + * specifications + */ .cksrx = 5, .cksre = 5, .freq_chg_en = 0, @@ -147,92 +141,12 @@ int dram_init(void) .wldqsen = 25, }; - ddrmc_setup_iomux(NULL, 0); - ddrmc_ctrl_init_ddr3(&timings, colibri_vf_cr_settings, NULL, 1, 2); gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); return 0; } -static void setup_iomux_uart(void) -{ - static const iomux_v3_cfg_t uart_pads[] = { - NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTB10__UART0_TX, UART_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTB11__UART0_RX, UART_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); -} - -static void setup_iomux_enet(void) -{ - static const iomux_v3_cfg_t enet0_pads[] = { - NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKOUT, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC10__RMII1_MDIO, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC9__RMII1_MDC, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC11__RMII1_CRS_DV, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC12__RMII1_RD1, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC13__RMII1_RD0, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC14__RMII1_RXER, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC15__RMII1_TD1, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC16__RMII1_TD0, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC17__RMII1_TXEN, ENET_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads)); -} - -static void setup_iomux_i2c(void) -{ - static const iomux_v3_cfg_t i2c0_pads[] = { - VF610_PAD_PTB14__I2C0_SCL, - VF610_PAD_PTB15__I2C0_SDA, - }; - - imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads)); -} - -#ifdef CONFIG_NAND_VF610_NFC -static void setup_iomux_nfc(void) -{ - static const iomux_v3_cfg_t nfc_pads[] = { - VF610_PAD_PTD23__NF_IO7, - VF610_PAD_PTD22__NF_IO6, - VF610_PAD_PTD21__NF_IO5, - VF610_PAD_PTD20__NF_IO4, - VF610_PAD_PTD19__NF_IO3, - VF610_PAD_PTD18__NF_IO2, - VF610_PAD_PTD17__NF_IO1, - VF610_PAD_PTD16__NF_IO0, - VF610_PAD_PTB24__NF_WE_B, - VF610_PAD_PTB25__NF_CE0_B, - VF610_PAD_PTB27__NF_RE_B, - VF610_PAD_PTC26__NF_RB_B, - VF610_PAD_PTC27__NF_ALE, - VF610_PAD_PTC28__NF_CLE - }; - - imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); -} -#endif - -#ifdef CONFIG_FSL_DSPI -static void setup_iomux_dspi(void) -{ - static const iomux_v3_cfg_t dspi1_pads[] = { - VF610_PAD_PTD5__DSPI1_CS0, - VF610_PAD_PTD6__DSPI1_SIN, - VF610_PAD_PTD7__DSPI1_SOUT, - VF610_PAD_PTD8__DSPI1_SCK, - }; - - imx_iomux_v3_setup_multiple_pads(dspi1_pads, ARRAY_SIZE(dspi1_pads)); -} -#endif - #ifdef CONFIG_VYBRID_GPIO static void setup_iomux_gpio(void) { @@ -331,37 +245,6 @@ static void setup_tcon(void) } #endif -#ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg esdhc_cfg[1] = { - {ESDHC1_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - /* eSDHC1 is always present */ - return 1; -} - -int board_mmc_init(bd_t *bis) -{ - static const iomux_v3_cfg_t esdhc1_pads[] = { - NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL), - }; - - esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - - imx_iomux_v3_setup_multiple_pads( - esdhc1_pads, ARRAY_SIZE(esdhc1_pads)); - - return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); -} -#endif - static inline int is_colibri_vf61(void) { struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR; @@ -394,7 +277,7 @@ static void clock_init(void) CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK); clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK | - CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK); + CCM_CCGR4_GPC_CTRL_MASK); clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK); clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, @@ -483,34 +366,15 @@ static void mscm_init(void) writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]); } -int board_phy_config(struct phy_device *phydev) -{ - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - int board_early_init_f(void) { clock_init(); mscm_init(); - setup_iomux_uart(); - setup_iomux_enet(); - setup_iomux_i2c(); -#ifdef CONFIG_NAND_VF610_NFC - setup_iomux_nfc(); -#endif - #ifdef CONFIG_VYBRID_GPIO setup_iomux_gpio(); #endif -#ifdef CONFIG_FSL_DSPI - setup_iomux_dspi(); -#endif - #ifdef CONFIG_VIDEO_FSL_DCU_FB setup_tcon(); setup_iomux_fsl_dcu(); @@ -548,22 +412,17 @@ int board_init(void) * so we must use the external oscillator in order * to maintain correct time in the hwclock */ - setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN); -#ifdef CONFIG_USB_EHCI_VF - gpio_request(USB_CDET_GPIO, "usb-cdet-gpio"); -#endif - return 0; } int checkboard(void) { if (is_colibri_vf61()) - puts("Board: Colibri VF61\n"); + puts("Model: Toradex Colibri VF61\n"); else - puts("Board: Colibri VF50\n"); + puts("Model: Toradex Colibri VF50\n"); return 0; } @@ -591,49 +450,6 @@ int ft_board_setup(void *blob, bd_t *bd) } #endif -#ifdef CONFIG_USB_EHCI_VF -int board_ehci_hcd_init(int port) -{ - imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); - - switch (port) { - case 0: - /* USBC does not have PEN, also configured as USB client only */ - break; - case 1: - gpio_request(USB_PEN_GPIO, "usb-pen-gpio"); - gpio_direction_output(USB_PEN_GPIO, 0); - break; - } - return 0; -} - -int board_usb_phy_mode(int port) -{ - switch (port) { - case 0: - /* - * Port 0 is used only in client mode on Colibri Vybrid modules - * Check for state of USB client gpio pin and accordingly return - * USB_INIT_DEVICE or USB_INIT_HOST. - */ - if (gpio_get_value(USB_CDET_GPIO)) - return USB_INIT_DEVICE; - else - return USB_INIT_HOST; - case 1: - /* Port 1 is used only in host mode on Colibri Vybrid modules */ - return USB_INIT_HOST; - default: - /* - * There are only two USB controllers on Vybrid. Ideally we will - * not reach here. However return USB_INIT_HOST if we do. - */ - return USB_INIT_HOST; - } -} -#endif - /* * Backlight off before OS handover */ diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index d4f5b1803a..b90077bedc 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -261,7 +261,7 @@ int read_tdx_cfg_block(void) } /* Cap product id to avoid issues with a yet unknown one */ - if (tdx_hw_tag.prodid > (sizeof(toradex_modules) / + if (tdx_hw_tag.prodid >= (sizeof(toradex_modules) / sizeof(toradex_modules[0]))) tdx_hw_tag.prodid = 0; @@ -418,6 +418,7 @@ static int do_cfgblock_create(cmd_tbl_t *cmdtp, int flag, int argc, int offset = 0; int ret = CMD_RET_SUCCESS; int err; + int force_overwrite = 0; /* Allocate RAM area for config block */ config_block = memalign(ARCH_DMA_MINALIGN, size); @@ -428,6 +429,11 @@ static int do_cfgblock_create(cmd_tbl_t *cmdtp, int flag, int argc, memset(config_block, 0xff, size); + if (argc >= 3) { + if (argv[2][0] == '-' && argv[2][1] == 'y') + force_overwrite = 1; + } + read_tdx_cfg_block(); if (valid_cfgblock) { #if defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NAND) @@ -448,24 +454,31 @@ static int do_cfgblock_create(cmd_tbl_t *cmdtp, int flag, int argc, CONFIG_TDX_CFG_BLOCK_OFFSET); goto out; #else - char message[CONFIG_SYS_CBSIZE]; - sprintf(message, - "A valid Toradex config block is present, still recreate? [y/N] "); + if (!force_overwrite) { + char message[CONFIG_SYS_CBSIZE]; - if (!cli_readline(message)) - goto out; + sprintf(message, + "A valid Toradex config block is present, still recreate? [y/N] "); - if (console_buffer[0] != 'y' && console_buffer[0] != 'Y') - goto out; + if (!cli_readline(message)) + goto out; + + if (console_buffer[0] != 'y' && + console_buffer[0] != 'Y') + goto out; + } #endif } /* Parse new Toradex config block data... */ - if (argc < 3) + if (argc < 3 || (force_overwrite && argc < 4)) { err = get_cfgblock_interactive(); - else - err = get_cfgblock_barcode(argv[2]); - + } else { + if (force_overwrite) + err = get_cfgblock_barcode(argv[3]); + else + err = get_cfgblock_barcode(argv[2]); + } if (err) { ret = CMD_RET_FAILURE; goto out; @@ -549,8 +562,8 @@ static int do_cfgblock(cmd_tbl_t *cmdtp, int flag, int argc, } U_BOOT_CMD( - cfgblock, 3, 0, do_cfgblock, + cfgblock, 4, 0, do_cfgblock, "Toradex config block handling commands", - "create [barcode] - (Re-)create Toradex config block\n" + "create [-y] [barcode] - (Re-)create Toradex config block\n" "cfgblock reload - Reload Toradex config block from flash" ); diff --git a/board/toradex/common/tdx-common.c b/board/toradex/common/tdx-common.c index fde230c955..2d560cceaf 100644 --- a/board/toradex/common/tdx-common.c +++ b/board/toradex/common/tdx-common.c @@ -12,6 +12,8 @@ #include <asm/setup.h> #include "tdx-common.h" +#define TORADEX_OUI 0x00142dUL + #ifdef CONFIG_TDX_CFG_BLOCK static char tdx_serial_str[9]; static char tdx_board_rev_str[6]; @@ -68,20 +70,25 @@ int show_board_info(void) unsigned char ethaddr[6]; if (read_tdx_cfg_block()) { - printf("Missing Toradex config block\n"); + printf("MISSING TORADEX CONFIG BLOCK\n"); + tdx_eth_addr.oui = htonl(TORADEX_OUI << 8); + tdx_eth_addr.nic = htonl(tdx_serial << 8); checkboard(); - return 0; + } else { + sprintf(tdx_serial_str, "%08u", tdx_serial); + sprintf(tdx_board_rev_str, "V%1d.%1d%c", + tdx_hw_tag.ver_major, + tdx_hw_tag.ver_minor, + (char)tdx_hw_tag.ver_assembly + 'A'); + + env_set("serial#", tdx_serial_str); + + printf("Model: Toradex %s %s, Serial# %s\n", + toradex_modules[tdx_hw_tag.prodid], + tdx_board_rev_str, + tdx_serial_str); } - /* board serial-number */ - sprintf(tdx_serial_str, "%08u", tdx_serial); - sprintf(tdx_board_rev_str, "V%1d.%1d%c", - tdx_hw_tag.ver_major, - tdx_hw_tag.ver_minor, - (char)tdx_hw_tag.ver_assembly + 'A'); - - env_set("serial#", tdx_serial_str); - /* * Check if environment contains a valid MAC address, * set the one from config block if not @@ -101,11 +108,6 @@ int show_board_info(void) } #endif - printf("Model: Toradex %s %s, Serial# %s\n", - toradex_modules[tdx_hw_tag.prodid], - tdx_board_rev_str, - tdx_serial_str); - return 0; } diff --git a/board/wandboard/MAINTAINERS b/board/wandboard/MAINTAINERS index d7cbae8f95..00a31a9346 100644 --- a/board/wandboard/MAINTAINERS +++ b/board/wandboard/MAINTAINERS @@ -1,6 +1,9 @@ WANDBOARD BOARD M: Fabio Estevam <fabio.estevam@nxp.com> S: Maintained +F: arch/arm/dts/imx6qdl-wandboard.dtsi +F: arch/arm/dts/imx6qdl-wandboard-revb1.dtsi +F: arch/arm/dts/imx6dl-wandboard-revb1.dts F: board/wandboard/ F: include/configs/wandboard.h F: configs/wandboard_defconfig diff --git a/board/wandboard/spl.c b/board/wandboard/spl.c index 9c3350019c..000cb109fc 100644 --- a/board/wandboard/spl.c +++ b/board/wandboard/spl.c @@ -422,4 +422,96 @@ void board_init_f(ulong dummy) /* DDR initialization */ spl_dram_init(); } + +#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2) +#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC3_BASE_ADDR}, + {USDHC1_BASE_ADDR}, +}; + +static iomux_v3_cfg_t const usdhc1_pads[] = { + IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + /* Carrier MicroSD Card Detect */ + IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + /* SOM MicroSD Card Detect */ + IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + int ret; + u32 index = 0; + + /* + * Following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 SOM MicroSD + * mmc1 Carrier board MicroSD + */ + for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { + switch (index) { + case 0: + SETUP_IOMUX_PADS(usdhc3_pads); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[0].max_bus_width = 4; + gpio_direction_input(USDHC3_CD_GPIO); + break; + case 1: + SETUP_IOMUX_PADS(usdhc1_pads); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + usdhc_cfg[1].max_bus_width = 4; + gpio_direction_input(USDHC1_CD_GPIO); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) then supported by the board (%d)\n", + index + 1, CONFIG_SYS_FSL_USDHC_NUM); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + if (ret) + return ret; + } + + return 0; +} + #endif diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index 6af1b45882..69fbc8b690 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -22,8 +22,6 @@ #include <asm/io.h> #include <linux/sizes.h> #include <common.h> -#include <fsl_esdhc.h> -#include <mmc.h> #include <miiphy.h> #include <netdev.h> #include <phy.h> @@ -37,10 +35,6 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) @@ -48,8 +42,6 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_ODE | PAD_CTL_SRE_FAST) -#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2) -#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9) #define ETH_PHY_RESET IMX_GPIO_NR(3, 29) #define ETH_PHY_AR8035_POWER IMX_GPIO_NR(7, 13) #define REV_DETECTION IMX_GPIO_NR(2, 28) @@ -68,28 +60,6 @@ static iomux_v3_cfg_t const uart1_pads[] = { IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), }; -static iomux_v3_cfg_t const usdhc1_pads[] = { - IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - /* Carrier MicroSD Card Detect */ - IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - -static iomux_v3_cfg_t const usdhc3_pads[] = { - IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - /* SOM MicroSD Card Detect */ - IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - static iomux_v3_cfg_t const enet_pads[] = { IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), @@ -131,80 +101,20 @@ static void setup_iomux_enet(void) if (with_pmic) { SETUP_IOMUX_PADS(enet_ar8035_power_pads); /* enable AR8035 POWER */ + gpio_request(ETH_PHY_AR8035_POWER, "PHY_POWER"); gpio_direction_output(ETH_PHY_AR8035_POWER, 0); } /* wait until 3.3V of PHY and clock become stable */ mdelay(10); /* Reset AR8031 PHY */ + gpio_request(ETH_PHY_RESET, "PHY_RESET"); gpio_direction_output(ETH_PHY_RESET, 0); mdelay(10); gpio_set_value(ETH_PHY_RESET, 1); udelay(100); } -static struct fsl_esdhc_cfg usdhc_cfg[2] = { - {USDHC3_BASE_ADDR}, - {USDHC1_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC1_BASE_ADDR: - ret = !gpio_get_value(USDHC1_CD_GPIO); - break; - case USDHC3_BASE_ADDR: - ret = !gpio_get_value(USDHC3_CD_GPIO); - break; - } - - return ret; -} - -int board_mmc_init(bd_t *bis) -{ - int ret; - u32 index = 0; - - /* - * Following map is done: - * (U-Boot device node) (Physical Port) - * mmc0 SOM MicroSD - * mmc1 Carrier board MicroSD - */ - for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { - switch (index) { - case 0: - SETUP_IOMUX_PADS(usdhc3_pads); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - usdhc_cfg[0].max_bus_width = 4; - gpio_direction_input(USDHC3_CD_GPIO); - break; - case 1: - SETUP_IOMUX_PADS(usdhc1_pads); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - usdhc_cfg[1].max_bus_width = 4; - gpio_direction_input(USDHC1_CD_GPIO); - break; - default: - printf("Warning: you configured more USDHC controllers" - "(%d) then supported by the board (%d)\n", - index + 1, CONFIG_SYS_FSL_USDHC_NUM); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); - if (ret) - return ret; - } - - return 0; -} - static int ar8031_phy_fixup(struct phy_device *phydev) { unsigned short val; @@ -348,14 +258,29 @@ static void do_enable_hdmi(struct display_info_t const *dev) static int detect_i2c(struct display_info_t const *dev) { +#ifdef CONFIG_DM_I2C + struct udevice *bus, *udev; + int rc; + + rc = uclass_get_device_by_seq(UCLASS_I2C, dev->bus, &bus); + if (rc) + return rc; + rc = dm_i2c_probe(bus, dev->addr, 0, &udev); + if (rc) + return 0; + return 1; +#else return (0 == i2c_set_bus_num(dev->bus)) && (0 == i2c_probe(dev->addr)); +#endif } static void enable_fwadapt_7wvga(struct display_info_t const *dev) { SETUP_IOMUX_PADS(fwadapt_7wvga_pads); + gpio_request(IMX_GPIO_NR(2, 10), "DISP0_BKLEN"); + gpio_request(IMX_GPIO_NR(2, 11), "DISP0_VDDEN"); gpio_direction_output(IMX_GPIO_NR(2, 10), 1); gpio_direction_output(IMX_GPIO_NR(2, 11), 1); } @@ -418,6 +343,7 @@ static void setup_display(void) /* Disable LCD backlight */ SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20); + gpio_request(IMX_GPIO_NR(4, 20), "LCD_BKLEN"); gpio_direction_input(IMX_GPIO_NR(4, 20)); } #endif /* CONFIG_VIDEO_IPUV3 */ @@ -443,24 +369,30 @@ int board_early_init_f(void) int power_init_board(void) { - struct pmic *p; - u32 reg; - - /* configure PFUZE100 PMIC */ - power_pfuze100_init(PMIC_I2C_BUS); - p = pmic_get("PFUZE100"); - if (p && !pmic_probe(p)) { - pmic_reg_read(p, PFUZE100_DEVICEID, ®); - printf("PMIC: PFUZE100 ID=0x%02x\n", reg); - with_pmic = true; - - /* Set VGEN2 to 1.5V and enable */ - pmic_reg_read(p, PFUZE100_VGEN2VOL, ®); - reg &= ~(LDO_VOL_MASK); - reg |= (LDOA_1_50V | (1 << (LDO_EN))); - pmic_reg_write(p, PFUZE100_VGEN2VOL, reg); + struct udevice *dev; + int reg, ret; + + puts("PMIC: "); + + ret = pmic_get("pfuze100", &dev); + if (ret < 0) { + printf("pmic_get() ret %d\n", ret); + return 0; } + reg = pmic_reg_read(dev, PFUZE100_DEVICEID); + if (reg < 0) { + printf("pmic_reg_read() ret %d\n", reg); + return 0; + } + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + with_pmic = true; + + /* Set VGEN2 to 1.5V and enable */ + reg = pmic_reg_read(dev, PFUZE100_VGEN2VOL); + reg &= ~(LDO_VOL_MASK); + reg |= (LDOA_1_50V | (1 << (LDO_EN))); + pmic_reg_write(dev, PFUZE100_VGEN2VOL, reg); return 0; } @@ -531,13 +463,13 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; #if defined(CONFIG_VIDEO_IPUV3) - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info); + setup_i2c(1, CONFIG_SYS_MXC_I2C1_SPEED, 0x7f, &mx6dl_i2c2_pad_info); if (is_mx6dq() || is_mx6dqp()) { - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info); - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c3_pad_info); + setup_i2c(1, CONFIG_SYS_MXC_I2C1_SPEED, 0x7f, &mx6q_i2c2_pad_info); + setup_i2c(2, CONFIG_SYS_MXC_I2C2_SPEED, 0x7f, &mx6q_i2c3_pad_info); } else { - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info); - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c3_pad_info); + setup_i2c(1, CONFIG_SYS_MXC_I2C1_SPEED, 0x7f, &mx6dl_i2c2_pad_info); + setup_i2c(2, CONFIG_SYS_MXC_I2C2_SPEED, 0x7f, &mx6dl_i2c3_pad_info); } setup_display(); @@ -548,6 +480,8 @@ int board_init(void) int checkboard(void) { + gpio_request(REV_DETECTION, "REV_DETECT"); + if (is_revd1()) puts("Board: Wandboard rev D1\n"); else if (is_revc1()) diff --git a/board/xilinx/zynq/cmds.c b/board/xilinx/zynq/cmds.c index 8b48ea3a03..27d44b760d 100644 --- a/board/xilinx/zynq/cmds.c +++ b/board/xilinx/zynq/cmds.c @@ -414,9 +414,13 @@ static int do_zynq_rsa(cmd_tbl_t *cmdtp, int flag, int argc, u32 src_ptr; char *endp; + if (argc != cmdtp->maxargs) + return CMD_RET_FAILURE; + src_ptr = simple_strtoul(argv[2], &endp, 16); if (*argv[2] == 0 || *endp != 0) return CMD_RET_USAGE; + if (zynq_verify_image(src_ptr)) return CMD_RET_FAILURE; @@ -432,6 +436,9 @@ static int zynq_decrypt_image(cmd_tbl_t *cmdtp, int flag, int argc, u32 srcaddr, srclen, dstaddr, dstlen; int status; + if (argc < 5 && argc > cmdtp->maxargs) + return CMD_RET_USAGE; + srcaddr = simple_strtoul(argv[2], &endp, 16); if (*argv[2] == 0 || *endp != 0) return CMD_RET_USAGE; @@ -485,7 +492,7 @@ static int do_zynq(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return CMD_RET_USAGE; zynq_cmd = find_cmd_tbl(argv[1], zynq_commands, ARRAY_SIZE(zynq_commands)); - if (!zynq_cmd || argc != zynq_cmd->maxargs) + if (!zynq_cmd) return CMD_RET_USAGE; ret = zynq_cmd->cmd(zynq_cmd, flag, argc, argv); diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index db27247850..5189925beb 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -170,6 +170,10 @@ static const struct { .id = 0x62, .name = "29dr", }, + { + .id = 0x66, + .name = "39dr", + }, }; #endif @@ -482,18 +486,20 @@ static const struct { {} }; -static u32 reset_reason(void) +static int reset_reason(void) { - u32 ret; - int i; + u32 reg; + int i, ret; const char *reason = NULL; - ret = readl(&crlapb_base->reset_reason); + ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, ®); + if (ret) + return -EINVAL; puts("Reset reason:\t"); for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) { - if (ret & reset_reasons[i].bit) { + if (reg & reset_reasons[i].bit) { reason = reset_reasons[i].name; printf("%s ", reset_reasons[i].name); break; @@ -504,7 +510,9 @@ static u32 reset_reason(void) env_set("reset_reason", reason); - writel(~0, &crlapb_base->reset_reason); + ret = zynqmp_mmio_write(~0, ~0, (ulong)&crlapb_base->reset_reason); + if (ret) + return -EINVAL; return ret; } |