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-rw-r--r--board/freescale/mx6ul_14x14_evk/Kconfig2
-rw-r--r--board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c183
2 files changed, 152 insertions, 33 deletions
diff --git a/board/freescale/mx6ul_14x14_evk/Kconfig b/board/freescale/mx6ul_14x14_evk/Kconfig
index 393aca629b..eda02c9f78 100644
--- a/board/freescale/mx6ul_14x14_evk/Kconfig
+++ b/board/freescale/mx6ul_14x14_evk/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_MX6UL_14X14_EVK
+if TARGET_MX6UL_14X14_EVK || TARGET_MX6UL_9X9_EVK
config SYS_BOARD
default "mx6ul_14x14_evk"
diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
index c09d84e540..612fb78834 100644
--- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@@ -23,6 +23,9 @@
#include <linux/sizes.h>
#include <mmc.h>
#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze3000_pmic.h>
+#include "../common/pfuze.h"
#include <usb.h>
#include <usb/ehci-fsl.h>
@@ -210,11 +213,56 @@ struct i2c_pads_info i2c_pad_info1 = {
.gp = IMX_GPIO_NR(1, 29),
},
};
+
+#ifdef CONFIG_POWER
+#define I2C_PMIC 0
+int power_init_board(void)
+{
+ if (is_mx6ul_9x9_evk()) {
+ struct pmic *pfuze;
+ int ret;
+ unsigned int reg, rev_id;
+
+ ret = power_pfuze3000_init(I2C_PMIC);
+ if (ret)
+ return ret;
+
+ pfuze = pmic_get("PFUZE3000");
+ ret = pmic_probe(pfuze);
+ if (ret)
+ return ret;
+
+ pmic_reg_read(pfuze, PFUZE3000_DEVICEID, &reg);
+ pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id);
+ printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n",
+ reg, rev_id);
+
+ /* disable Low Power Mode during standby mode */
+ pmic_reg_read(pfuze, PFUZE3000_LDOGCTL, &reg);
+ reg |= 0x1;
+ pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, reg);
+
+ /* SW1B step ramp up time from 2us to 4us/25mV */
+ reg = 0x40;
+ pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, reg);
+
+ /* SW1B mode to APS/PFM */
+ reg = 0xc;
+ pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, reg);
+
+ /* SW1B standby voltage set to 0.975V */
+ reg = 0xb;
+ pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, reg);
+ }
+
+ return 0;
+}
+#endif
#endif
int dram_init(void)
{
- gd->ram_size = PHYS_SDRAM_SIZE;
+ gd->ram_size = imx_ddr_size();
return 0;
}
@@ -614,6 +662,15 @@ int board_late_init(void)
add_board_boot_modes(board_boot_modes);
#endif
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ setenv("board_name", "EVK");
+
+ if (is_mx6ul_9x9_evk())
+ setenv("board_rev", "9X9");
+ else
+ setenv("board_rev", "14X14");
+#endif
+
return 0;
}
@@ -624,7 +681,10 @@ u32 get_board_rev(void)
int checkboard(void)
{
- puts("Board: MX6UL 14x14 EVK\n");
+ if (is_mx6ul_9x9_evk())
+ puts("Board: MX6UL 9x9 EVK\n");
+ else
+ puts("Board: MX6UL 14x14 EVK\n");
return 0;
}
@@ -634,7 +694,76 @@ int checkboard(void)
#include <spl.h>
#include <asm/arch/mx6-ddr.h>
-const struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
+
+static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
+ .grp_addds = 0x00000030,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_b0ds = 0x00000030,
+ .grp_ctlds = 0x00000030,
+ .grp_b1ds = 0x00000030,
+ .grp_ddrpke = 0x00000000,
+ .grp_ddrmode = 0x00020000,
+#ifdef CONFIG_TARGET_MX6UL_9X9_EVK
+ .grp_ddr_type = 0x00080000,
+#else
+ .grp_ddr_type = 0x000c0000,
+#endif
+};
+
+#ifdef CONFIG_TARGET_MX6UL_9X9_EVK
+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
+ .dram_dqm0 = 0x00000030,
+ .dram_dqm1 = 0x00000030,
+ .dram_ras = 0x00000030,
+ .dram_cas = 0x00000030,
+ .dram_odt0 = 0x00000000,
+ .dram_odt1 = 0x00000000,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdclk_0 = 0x00000030,
+ .dram_sdqs0 = 0x00003030,
+ .dram_sdqs1 = 0x00003030,
+ .dram_reset = 0x00000030,
+};
+
+static struct mx6_mmdc_calibration mx6_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x00000000,
+ .p0_mpdgctrl0 = 0x20000000,
+ .p0_mprddlctl = 0x4040484f,
+ .p0_mpwrdlctl = 0x40405247,
+ .mpzqlp2ctl = 0x1b4700c7,
+};
+
+static struct mx6_lpddr2_cfg mem_ddr = {
+ .mem_speed = 800,
+ .density = 2,
+ .width = 16,
+ .banks = 4,
+ .rowaddr = 14,
+ .coladdr = 10,
+ .trcd_lp = 1500,
+ .trppb_lp = 1500,
+ .trpab_lp = 2000,
+ .trasmin = 4250,
+};
+
+struct mx6_ddr_sysinfo ddr_sysinfo = {
+ .dsize = 0,
+ .cs_density = 18,
+ .ncs = 1,
+ .cs1_mirror = 0,
+ .walat = 0,
+ .ralat = 5,
+ .mif3_mode = 3,
+ .bi_on = 1,
+ .rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */
+ .rtt_nom = 0,
+ .sde_to_rst = 0, /* LPDDR2 does not need this field */
+ .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
+ .ddr_type = DDR_TYPE_LPDDR2,
+};
+
+#else
+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
.dram_dqm0 = 0x00000030,
.dram_dqm1 = 0x00000030,
.dram_ras = 0x00000030,
@@ -648,24 +777,29 @@ const struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
.dram_reset = 0x00000030,
};
-const struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
- .grp_addds = 0x00000030,
- .grp_ddrmode_ctl = 0x00020000,
- .grp_b0ds = 0x00000030,
- .grp_ctlds = 0x00000030,
- .grp_b1ds = 0x00000030,
- .grp_ddrpke = 0x00000000,
- .grp_ddrmode = 0x00020000,
- .grp_ddr_type = 0x000c0000,
-};
-
-const struct mx6_mmdc_calibration mx6_mmcd_calib = {
+static struct mx6_mmdc_calibration mx6_mmcd_calib = {
.p0_mpwldectrl0 = 0x00070007,
.p0_mpdgctrl0 = 0x41490145,
.p0_mprddlctl = 0x40404546,
.p0_mpwrdlctl = 0x4040524D,
};
+struct mx6_ddr_sysinfo ddr_sysinfo = {
+ .dsize = 0,
+ .cs_density = 20,
+ .ncs = 1,
+ .cs1_mirror = 0,
+ .rtt_wr = 2,
+ .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
+ .walat = 1, /* Write additional latency */
+ .ralat = 5, /* Read additional latency */
+ .mif3_mode = 3, /* Command prediction working mode */
+ .bi_on = 1, /* Bank interleaving enabled */
+ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
+ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+ .ddr_type = DDR_TYPE_DDR3,
+};
+
static struct mx6_ddr3_cfg mem_ddr = {
.mem_speed = 800,
.density = 4,
@@ -678,6 +812,7 @@ static struct mx6_ddr3_cfg mem_ddr = {
.trcmin = 4875,
.trasmin = 3500,
};
+#endif
static void ccgr_init(void)
{
@@ -695,24 +830,8 @@ static void ccgr_init(void)
static void spl_dram_init(void)
{
- struct mx6_ddr_sysinfo sysinfo = {
- .dsize = 0,
- .cs_density = 20,
- .ncs = 1,
- .cs1_mirror = 0,
- .rtt_wr = 2,
- .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
- .walat = 1, /* Write additional latency */
- .ralat = 5, /* Read additional latency */
- .mif3_mode = 3, /* Command prediction working mode */
- .bi_on = 1, /* Bank interleaving enabled */
- .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
- .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
- .ddr_type = DDR_TYPE_DDR3,
- };
-
mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
- mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
+ mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
}
void board_init_f(ulong dummy)
generated by cgit (git 2.34.1) at 2025-01-13 20:48:03 +0000