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-rw-r--r--cpu/arm920t/Makefile6
-rw-r--r--cpu/arm920t/imx_generic.c90
-rw-r--r--cpu/arm920t/imx_interrupts.c117
-rw-r--r--cpu/arm920t/imx_speed.c102
-rw-r--r--cpu/arm920t/interrupts.c143
-rw-r--r--cpu/arm920t/s3c24x0_interrupts.c180
-rw-r--r--cpu/arm920t/s3c24x0_serial.c (renamed from cpu/arm920t/serial.c)34
-rw-r--r--cpu/arm920t/s3c24x0_speed.c (renamed from cpu/arm920t/speed.c)6
-rw-r--r--cpu/arm920t/start.S24
9 files changed, 530 insertions, 172 deletions
diff --git a/cpu/arm920t/Makefile b/cpu/arm920t/Makefile
index 605adf301f..68a33d6559 100644
--- a/cpu/arm920t/Makefile
+++ b/cpu/arm920t/Makefile
@@ -26,7 +26,11 @@ include $(TOPDIR)/config.mk
LIB = lib$(CPU).a
START = start.o
-OBJS = serial.o interrupts.o cpu.o speed.o usb_ohci.o
+OBJS = cpu.o \
+ imx_generic.o imx_interrupts.o imx_speed.o \
+ interrupts.o \
+ s3c24x0_interrupts.o s3c24x0_serial.o s3c24x0_speed.o \
+ usb_ohci.o
all: .depend $(START) $(LIB)
diff --git a/cpu/arm920t/imx_generic.c b/cpu/arm920t/imx_generic.c
new file mode 100644
index 0000000000..aa7c8c159d
--- /dev/null
+++ b/cpu/arm920t/imx_generic.c
@@ -0,0 +1,90 @@
+/*
+ * arch/arm/mach-imx/generic.c
+ *
+ * author: Sascha Hauer
+ * Created: april 20th, 2004
+ * Copyright: Synertronixx GmbH
+ *
+ * Common code for i.MX machines
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_IMX
+
+#include <asm/arch/imx-regs.h>
+
+void imx_gpio_mode(int gpio_mode)
+{
+ unsigned int pin = gpio_mode & GPIO_PIN_MASK;
+ unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> 5;
+ unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> 10;
+ unsigned int tmp;
+
+ /* Pullup enable */
+ if(gpio_mode & GPIO_PUEN)
+ PUEN(port) |= (1<<pin);
+ else
+ PUEN(port) &= ~(1<<pin);
+
+ /* Data direction */
+ if(gpio_mode & GPIO_OUT)
+ DDIR(port) |= 1<<pin;
+ else
+ DDIR(port) &= ~(1<<pin);
+
+ /* Primary / alternate function */
+ if(gpio_mode & GPIO_AF)
+ GPR(port) |= (1<<pin);
+ else
+ GPR(port) &= ~(1<<pin);
+
+ /* use as gpio? */
+ if( ocr == 3 )
+ GIUS(port) |= (1<<pin);
+ else
+ GIUS(port) &= ~(1<<pin);
+
+ /* Output / input configuration */
+ /* FIXME: I'm not very sure about OCR and ICONF, someone
+ * should have a look over it
+ */
+ if(pin<16) {
+ tmp = OCR1(port);
+ tmp &= ~( 3<<(pin*2));
+ tmp |= (ocr << (pin*2));
+ OCR1(port) = tmp;
+
+ if( gpio_mode & GPIO_AOUT )
+ ICONFA1(port) &= ~( 3<<(pin*2));
+ if( gpio_mode & GPIO_BOUT )
+ ICONFB1(port) &= ~( 3<<(pin*2));
+ } else {
+ tmp = OCR2(port);
+ tmp &= ~( 3<<((pin-16)*2));
+ tmp |= (ocr << ((pin-16)*2));
+ OCR2(port) = tmp;
+
+ if( gpio_mode & GPIO_AOUT )
+ ICONFA2(port) &= ~( 3<<((pin-16)*2));
+ if( gpio_mode & GPIO_BOUT )
+ ICONFB2(port) &= ~( 3<<((pin-16)*2));
+ }
+}
+
+#endif /* CONFIG_IMX */
diff --git a/cpu/arm920t/imx_interrupts.c b/cpu/arm920t/imx_interrupts.c
new file mode 100644
index 0000000000..12ae2faf28
--- /dev/null
+++ b/cpu/arm920t/imx_interrupts.c
@@ -0,0 +1,117 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#if defined (CONFIG_IMX)
+
+#include <arm920t.h>
+#include <asm/arch/imx-regs.h>
+
+int interrupt_init (void)
+{
+ int i;
+ /* setup GP Timer 1 */
+ TCTL1 = TCTL_SWR;
+ for ( i=0; i<100; i++) TCTL1 = 0; /* We have no udelay by now */
+ TPRER1 = get_PERCLK1() / 1000000; /* 1 MHz */
+ TCTL1 |= TCTL_FRR | (1<<1); /* Freerun Mode, PERCLK1 input */
+
+ reset_timer_masked();
+
+ return (0);
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer (void)
+{
+ reset_timer_masked ();
+}
+
+ulong get_timer (ulong base)
+{
+ return get_timer_masked ();
+}
+
+void set_timer (ulong t)
+{
+ /* nop */
+}
+
+void reset_timer_masked (void)
+{
+ TCTL1 &= ~TCTL_TEN;
+ TCTL1 |= TCTL_TEN; /* Enable timer */
+}
+
+ulong get_timer_masked (void)
+{
+ return TCN1;
+}
+
+void udelay_masked (unsigned long usec)
+{
+ ulong start = get_timer_masked();
+
+ while (get_timer_masked () - start < usec )
+ /*NOP*/;
+}
+
+void udelay (unsigned long usec)
+{
+ udelay_masked(usec);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+ ulong tbclk;
+
+ tbclk = CFG_HZ;
+
+ return tbclk;
+}
+
+#endif /* defined (CONFIG_IMX) */
diff --git a/cpu/arm920t/imx_speed.c b/cpu/arm920t/imx_speed.c
new file mode 100644
index 0000000000..1e296987d6
--- /dev/null
+++ b/cpu/arm920t/imx_speed.c
@@ -0,0 +1,102 @@
+/*
+ *
+ * (c) 2004 Sascha Hauer <sascha@saschahauer.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#if defined (CONFIG_IMX)
+
+#include <asm/arch/imx-regs.h>
+
+/* ------------------------------------------------------------------------- */
+/* NOTE: This describes the proper use of this file.
+ *
+ * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
+ * SH FIXME: 16780000 in our case
+ * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
+ * the specified bus in HZ.
+ */
+/* ------------------------------------------------------------------------- */
+
+ulong get_systemPLLCLK(void)
+{
+ /* FIXME: We assume System_SEL = 0 here */
+ u32 spctl0 = SPCTL0;
+ u32 mfi = (spctl0 >> 10) & 0xf;
+ u32 mfn = spctl0 & 0x3f;
+ u32 mfd = (spctl0 >> 16) & 0x3f;
+ u32 pd = (spctl0 >> 26) & 0xf;
+
+ mfi = mfi<=5 ? 5 : mfi;
+
+ return (2*(CONFIG_SYSPLL_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
+}
+
+ulong get_mcuPLLCLK(void)
+{
+ /* FIXME: We assume System_SEL = 0 here */
+ u32 mpctl0 = MPCTL0;
+ u32 mfi = (mpctl0 >> 10) & 0xf;
+ u32 mfn = mpctl0 & 0x3f;
+ u32 mfd = (mpctl0 >> 16) & 0x3f;
+ u32 pd = (mpctl0 >> 26) & 0xf;
+
+ mfi = mfi<=5 ? 5 : mfi;
+
+ return (2*(CONFIG_SYS_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
+}
+
+ulong get_FCLK(void)
+{
+ return (( CSCR>>15)&1) ? get_mcuPLLCLK()>>1 : get_mcuPLLCLK();
+}
+
+/* return HCLK frequency */
+ulong get_HCLK(void)
+{
+ u32 bclkdiv = (( CSCR >> 10 ) & 0xf) + 1;
+ printf("bclkdiv: %d\n", bclkdiv);
+ return get_systemPLLCLK() / bclkdiv;
+}
+
+/* return BCLK frequency */
+ulong get_BCLK(void)
+{
+ return get_HCLK();
+}
+
+ulong get_PERCLK1(void)
+{
+ return get_systemPLLCLK() / (((PCDR) & 0xf)+1);
+}
+
+ulong get_PERCLK2(void)
+{
+ return get_systemPLLCLK() / (((PCDR>>4) & 0xf)+1);
+}
+
+ulong get_PERCLK3(void)
+{
+ return get_systemPLLCLK() / (((PCDR>>16) & 0x7f)+1);
+}
+
+#endif /* defined (CONFIG_IMX) */
diff --git a/cpu/arm920t/interrupts.c b/cpu/arm920t/interrupts.c
index 521c4f479d..ea58f154d4 100644
--- a/cpu/arm920t/interrupts.c
+++ b/cpu/arm920t/interrupts.c
@@ -30,25 +30,11 @@
*/
#include <common.h>
-#include <arm920t.h>
-#if defined(CONFIG_S3C2400)
-#include <s3c2400.h>
-#elif defined(CONFIG_S3C2410)
-#include <s3c2410.h>
-#endif
+#include <arm920t.h>
#include <asm/proc-armv/ptrace.h>
extern void reset_cpu(ulong addr);
-int timer_load_val = 0;
-
-/* macro to read the 16 bit timer */
-static inline ulong READ_TIMER(void)
-{
- S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
-
- return (timers->TCNTO4 & 0xffff);
-}
#ifdef CONFIG_USE_IRQ
/* enable IRQ interrupts */
@@ -182,130 +168,3 @@ void do_irq (struct pt_regs *pt_regs)
show_regs (pt_regs);
bad_mode ();
}
-
-static ulong timestamp;
-static ulong lastdec;
-
-int interrupt_init (void)
-{
- S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
-
- /* use PWM Timer 4 because it has no output */
- /* prescaler for Timer 4 is 16 */
- timers->TCFG0 = 0x0f00;
- if (timer_load_val == 0)
- {
- /*
- * for 10 ms clock period @ PCLK with 4 bit divider = 1/2
- * (default) and prescaler = 16. Should be 10390
- * @33.25MHz and 15625 @ 50 MHz
- */
- timer_load_val = get_PCLK()/(2 * 16 * 100);
- }
- /* load value for 10 ms timeout */
- lastdec = timers->TCNTB4 = timer_load_val;
- /* auto load, manual update of Timer 4 */
- timers->TCON = (timers->TCON & ~0x0700000) | 0x600000;
- /* auto load, start Timer 4 */
- timers->TCON = (timers->TCON & ~0x0700000) | 0x500000;
- timestamp = 0;
-
- return (0);
-}
-
-/*
- * timer without interrupts
- */
-
-void reset_timer (void)
-{
- reset_timer_masked ();
-}
-
-ulong get_timer (ulong base)
-{
- return get_timer_masked () - base;
-}
-
-void set_timer (ulong t)
-{
- timestamp = t;
-}
-
-void udelay (unsigned long usec)
-{
- ulong tmo;
- ulong start = get_timer(0);
-
- tmo = usec / 1000;
- tmo *= (timer_load_val * 100);
- tmo /= 1000;
-
- while ((ulong)(get_timer_masked () - start) < tmo)
- /*NOP*/;
-}
-
-void reset_timer_masked (void)
-{
- /* reset time */
- lastdec = READ_TIMER();
- timestamp = 0;
-}
-
-ulong get_timer_masked (void)
-{
- ulong now = READ_TIMER();
-
- if (lastdec >= now) {
- /* normal mode */
- timestamp += lastdec - now;
- } else {
- /* we have an overflow ... */
- timestamp += lastdec + timer_load_val - now;
- }
- lastdec = now;
-
- return timestamp;
-}
-
-void udelay_masked (unsigned long usec)
-{
- ulong tmo;
-
- tmo = usec / 1000;
- tmo *= (timer_load_val * 100);
- tmo /= 1000;
-
- reset_timer_masked ();
-
- while (get_timer_masked () < tmo)
- /*NOP*/;
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
- ulong tbclk;
-
-#if defined(CONFIG_SMDK2400) || defined(CONFIG_TRAB)
- tbclk = timer_load_val * 100;
-#elif defined(CONFIG_SMDK2410) || defined(CONFIG_VCMA9)
- tbclk = CFG_HZ;
-#else
-# error "tbclk not configured"
-#endif
-
- return tbclk;
-}
diff --git a/cpu/arm920t/s3c24x0_interrupts.c b/cpu/arm920t/s3c24x0_interrupts.c
new file mode 100644
index 0000000000..92298b09f0
--- /dev/null
+++ b/cpu/arm920t/s3c24x0_interrupts.c
@@ -0,0 +1,180 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
+
+#include <arm920t.h>
+#if defined(CONFIG_S3C2400)
+#include <s3c2400.h>
+#elif defined(CONFIG_S3C2410)
+#include <s3c2410.h>
+#endif
+
+extern void reset_cpu(ulong addr);
+int timer_load_val = 0;
+
+/* macro to read the 16 bit timer */
+static inline ulong READ_TIMER(void)
+{
+ S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
+
+ return (timers->TCNTO4 & 0xffff);
+}
+
+static ulong timestamp;
+static ulong lastdec;
+
+int interrupt_init (void)
+{
+ S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
+
+ /* use PWM Timer 4 because it has no output */
+ /* prescaler for Timer 4 is 16 */
+ timers->TCFG0 = 0x0f00;
+ if (timer_load_val == 0)
+ {
+ /*
+ * for 10 ms clock period @ PCLK with 4 bit divider = 1/2
+ * (default) and prescaler = 16. Should be 10390
+ * @33.25MHz and 15625 @ 50 MHz
+ */
+ timer_load_val = get_PCLK()/(2 * 16 * 100);
+ }
+ /* load value for 10 ms timeout */
+ lastdec = timers->TCNTB4 = timer_load_val;
+ /* auto load, manual update of Timer 4 */
+ timers->TCON = (timers->TCON & ~0x0700000) | 0x600000;
+ /* auto load, start Timer 4 */
+ timers->TCON = (timers->TCON & ~0x0700000) | 0x500000;
+ timestamp = 0;
+
+ return (0);
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer (void)
+{
+ reset_timer_masked ();
+}
+
+ulong get_timer (ulong base)
+{
+ return get_timer_masked () - base;
+}
+
+void set_timer (ulong t)
+{
+ timestamp = t;
+}
+
+void udelay (unsigned long usec)
+{
+ ulong tmo;
+ ulong start = get_timer(0);
+
+ tmo = usec / 1000;
+ tmo *= (timer_load_val * 100);
+ tmo /= 1000;
+
+ while ((ulong)(get_timer_masked () - start) < tmo)
+ /*NOP*/;
+}
+
+void reset_timer_masked (void)
+{
+ /* reset time */
+ lastdec = READ_TIMER();
+ timestamp = 0;
+}
+
+ulong get_timer_masked (void)
+{
+ ulong now = READ_TIMER();
+
+ if (lastdec >= now) {
+ /* normal mode */
+ timestamp += lastdec - now;
+ } else {
+ /* we have an overflow ... */
+ timestamp += lastdec + timer_load_val - now;
+ }
+ lastdec = now;
+
+ return timestamp;
+}
+
+void udelay_masked (unsigned long usec)
+{
+ ulong tmo;
+
+ tmo = usec / 1000;
+ tmo *= (timer_load_val * 100);
+ tmo /= 1000;
+
+ reset_timer_masked ();
+
+ while (get_timer_masked () < tmo)
+ /*NOP*/;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+ ulong tbclk;
+
+#if defined(CONFIG_SMDK2400) || defined(CONFIG_TRAB)
+ tbclk = timer_load_val * 100;
+#elif defined(CONFIG_SMDK2410) || defined(CONFIG_VCMA9)
+ tbclk = CFG_HZ;
+#else
+# error "tbclk not configured"
+#endif
+
+ return tbclk;
+}
+
+#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
diff --git a/cpu/arm920t/serial.c b/cpu/arm920t/s3c24x0_serial.c
index 1749e820a1..83274432e4 100644
--- a/cpu/arm920t/serial.c
+++ b/cpu/arm920t/s3c24x0_serial.c
@@ -1,24 +1,26 @@
- /*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <common.h>
+#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
+
#if defined(CONFIG_S3C2400) || defined(CONFIG_TRAB)
#include <s3c2400.h>
#elif defined(CONFIG_S3C2410)
@@ -176,3 +178,5 @@ serial_puts (const char *s)
serial_putc (*s++);
}
}
+
+#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
diff --git a/cpu/arm920t/speed.c b/cpu/arm920t/s3c24x0_speed.c
index 1f435436b0..e0dca62563 100644
--- a/cpu/arm920t/speed.c
+++ b/cpu/arm920t/s3c24x0_speed.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2001-2002
+ * (C) Copyright 2001-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2002
@@ -30,6 +30,8 @@
*/
#include <common.h>
+#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
+
#if defined(CONFIG_S3C2400)
#include <s3c2400.h>
#elif defined(CONFIG_S3C2410)
@@ -95,3 +97,5 @@ ulong get_UCLK(void)
{
return(get_PLLCLK(UPLL));
}
+
+#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S
index 0e372d0e4c..78c470d7b6 100644
--- a/cpu/arm920t/start.S
+++ b/cpu/arm920t/start.S
@@ -118,20 +118,17 @@ reset:
/* turn off the watchdog */
#if defined(CONFIG_S3C2400)
-#define pWTCON 0x15300000
-/* Interupt-Controller base addresses */
-#define INTMSK 0x14400008
-/* clock divisor register */
-#define CLKDIVN 0x14800014
+# define pWTCON 0x15300000
+# define INTMSK 0x14400008 /* Interupt-Controller base addresses */
+# define CLKDIVN 0x14800014 /* clock divisor register */
#elif defined(CONFIG_S3C2410)
-#define pWTCON 0x53000000
-/* Interupt-Controller base addresses */
-#define INTMSK 0x4A000008
-#define INTSUBMSK 0x4A00001C
-/* clock divisor register */
-#define CLKDIVN 0x4C000014
+# define pWTCON 0x53000000
+# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
+# define INTSUBMSK 0x4A00001C
+# define CLKDIVN 0x4C000014 /* clock divisor register */
#endif
+#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
ldr r0, =pWTCON
mov r1, #0x0
str r1, [r0]
@@ -142,17 +139,18 @@ reset:
mov r1, #0xffffffff
ldr r0, =INTMSK
str r1, [r0]
-#if defined(CONFIG_S3C2410)
+# if defined(CONFIG_S3C2410)
ldr r1, =0x3ff
ldr r0, =INTSUBMSK
str r1, [r0]
-#endif
+# endif
/* FCLK:HCLK:PCLK = 1:2:4 */
/* default FCLK is 120 MHz ! */
ldr r0, =CLKDIVN
mov r1, #3
str r1, [r0]
+#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 */
/*
* we do sys-critical inits only at reboot,
generated by cgit (git 2.34.1) at 2024-12-25 01:44:39 +0000