diff options
Diffstat (limited to 'cpu/mpc83xx')
| -rw-r--r-- | cpu/mpc83xx/cpu_init.c | 8 | ||||
| -rw-r--r-- | cpu/mpc83xx/qe_io.c | 2 | ||||
| -rw-r--r-- | cpu/mpc83xx/speed.c | 14 |
3 files changed, 12 insertions, 12 deletions
diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index e5725fb91d..7574fabf86 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -202,12 +202,12 @@ void cpu_init_f (volatile immap_t * im) im->sysconf.lblaw[7].ar = CFG_LBLAWAR7_PRELIM; #endif #ifdef CFG_GPIO1_PRELIM - im->pgio[0].dir = CFG_GPIO1_DIR; - im->pgio[0].dat = CFG_GPIO1_DAT; + im->gpio[0].dir = CFG_GPIO1_DIR; + im->gpio[0].dat = CFG_GPIO1_DAT; #endif #ifdef CFG_GPIO2_PRELIM - im->pgio[1].dir = CFG_GPIO2_DIR; - im->pgio[1].dat = CFG_GPIO2_DAT; + im->gpio[1].dir = CFG_GPIO2_DIR; + im->gpio[1].dat = CFG_GPIO2_DAT; #endif } diff --git a/cpu/mpc83xx/qe_io.c b/cpu/mpc83xx/qe_io.c index ebe3487112..8b3937aa9b 100644 --- a/cpu/mpc83xx/qe_io.c +++ b/cpu/mpc83xx/qe_io.c @@ -35,7 +35,7 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) u32 pin_1bit_mask; u32 tmp_val; volatile immap_t *im = (volatile immap_t *)CFG_IMMR; - volatile gpio83xx_t *par_io =(volatile gpio83xx_t *)&im->gpio; + volatile qepio83xx_t *par_io = (volatile qepio83xx_t *)&im->qepio; /* Caculate pin location and 2bit mask and dir */ pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2)); diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c index 7e53b1e606..40ba6b04a3 100644 --- a/cpu/mpc83xx/speed.c +++ b/cpu/mpc83xx/speed.c @@ -139,7 +139,7 @@ int get_clocks(void) #endif } - spmf = ((im->reset.rcwl & RCWL_SPMF) >> RCWL_SPMF_SHIFT); + spmf = ((im->reset.rcwl & HRCWL_SPMF) >> HRCWL_SPMF_SHIFT); csb_clk = pci_sync_in * (1 + clkin_div) * spmf; sccr = im->clk.sccr; @@ -251,7 +251,7 @@ int get_clocks(void) } #if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360) lbiu_clk = csb_clk * - (1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT)); + (1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT)); #else #error Unknown MPC83xx chip #endif @@ -268,11 +268,11 @@ int get_clocks(void) } #if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360) ddr_clk = csb_clk * - (1 + ((im->reset.rcwl & RCWL_DDRCM) >> RCWL_DDRCM_SHIFT)); - corepll = (im->reset.rcwl & RCWL_COREPLL) >> RCWL_COREPLL_SHIFT; + (1 + ((im->reset.rcwl & HRCWL_DDRCM) >> HRCWL_DDRCM_SHIFT)); + corepll = (im->reset.rcwl & HRCWL_COREPLL) >> HRCWL_COREPLL_SHIFT; #if defined (CONFIG_MPC8360) ddr_sec_clk = csb_clk * (1 + - ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT)); + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT)); #endif #else #error Unknown MPC83xx chip @@ -307,8 +307,8 @@ int get_clocks(void) } #if defined (CONFIG_MPC8360) - qepmf = (im->reset.rcwl & RCWL_CEPMF) >> RCWL_CEPMF_SHIFT; - qepdf = (im->reset.rcwl & RCWL_CEPDF) >> RCWL_CEPDF_SHIFT; + qepmf = (im->reset.rcwl & HRCWL_CEPMF) >> HRCWL_CEPMF_SHIFT; + qepdf = (im->reset.rcwl & HRCWL_CEPDF) >> HRCWL_CEPDF_SHIFT; qe_clk = (pci_sync_in * qepmf) / (1 + qepdf); brg_clk = qe_clk / 2; #endif |