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-rw-r--r--cpu/ppc4xx/44x_spd_ddr2.c10
-rw-r--r--cpu/ppc4xx/4xx_enet.c2
-rw-r--r--cpu/ppc4xx/denali_spd_ddr2.c8
-rw-r--r--cpu/ppc4xx/tlb.c4
-rw-r--r--cpu/ppc4xx/traps.c26
5 files changed, 25 insertions, 25 deletions
diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
index 9a5340c351..a27e276f25 100644
--- a/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/cpu/ppc4xx/44x_spd_ddr2.c
@@ -378,7 +378,7 @@ static phys_size_t sdram_memsize(void)
mem_size+=4096;
break;
default:
- printf("WARNING: Unsupported bank size (SDSZ=0x%x)!\n"
+ printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n"
, sdsz);
mem_size=0;
break;
@@ -860,8 +860,8 @@ static void check_rank_number(unsigned long *dimm_populated,
if (dimm_rank > MAXRANKS) {
- printf("ERROR: DRAM DIMM detected with %d ranks in "
- "slot %d is not supported.\n", dimm_rank, dimm_num);
+ printf("ERROR: DRAM DIMM detected with %lu ranks in "
+ "slot %lu is not supported.\n", dimm_rank, dimm_num);
printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
printf("Replace the DIMM module with a supported DIMM.\n\n");
spd_ddr_init_hang ();
@@ -1062,7 +1062,7 @@ static void program_copt1(unsigned long *dimm_populated,
dimm_32bit = TRUE;
break;
default:
- printf("WARNING: Detected a DIMM with a data width of %d bits.\n",
+ printf("WARNING: Detected a DIMM with a data width of %lu bits.\n",
data_width);
printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
break;
@@ -1615,7 +1615,7 @@ static void program_mode(unsigned long *dimm_populated,
printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
printf("cas3=%d cas4=%d cas5=%d\n",
cas_3_0_available, cas_4_0_available, cas_5_0_available);
- printf("sdram_freq=%d cycle3=%d cycle4=%d cycle5=%d\n\n",
+ printf("sdram_freq=%lu cycle3=%lu cycle4=%lu cycle5=%lu\n\n",
sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
spd_ddr_init_hang ();
}
diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c
index c40e0ca480..4e863dc911 100644
--- a/cpu/ppc4xx/4xx_enet.c
+++ b/cpu/ppc4xx/4xx_enet.c
@@ -1076,7 +1076,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
bd_cached = (u32)malloc_aligned(MAL_ALLOC_SIZE, 4096);
if (!bd_cached) {
- printf("%s: Error allocating MAL descriptor buffers!\n");
+ printf("%s: Error allocating MAL descriptor buffers!\n", __func__);
return -1;
}
diff --git a/cpu/ppc4xx/denali_spd_ddr2.c b/cpu/ppc4xx/denali_spd_ddr2.c
index 3bd637567c..670fc5c6ed 100644
--- a/cpu/ppc4xx/denali_spd_ddr2.c
+++ b/cpu/ppc4xx/denali_spd_ddr2.c
@@ -339,7 +339,7 @@ static void get_spd_info(unsigned long dimm_ranks[],
"\n", dimm_num, ranks_on_dimm);
if (ranks_on_dimm > max_ranks_per_dimm) {
printf("WARNING: DRAM DIMM in slot %lu has %lu "
- "ranks.\n");
+ "ranks.\n", dimm_num, ranks_on_dimm);
if (1 == max_ranks_per_dimm) {
printf("Only one rank will be used.\n");
} else {
@@ -668,8 +668,8 @@ static void program_ddr0_03(unsigned long dimm_ranks[],
"and 5.0 are supported.\n");
printf("Make sure the PLB speed is within the supported range "
"of the DIMMs.\n");
- printf("sdram_freq=%d cycle2=%d cycle3=%d cycle4=%d "
- "cycle5=%d\n\n", sdram_freq, cycle_2_0_clk,
+ printf("sdram_freq=%ld cycle2=%ld cycle3=%ld cycle4=%ld "
+ "cycle5=%ld\n\n", sdram_freq, cycle_2_0_clk,
cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
spd_ddr_init_hang();
}
@@ -1248,7 +1248,7 @@ void board_add_ram_info(int use_default)
if (!is_ecc_enabled()) {
printf(" not");
}
- printf(" enabled, %d MHz", (2 * get_bus_freq(0)) / 1000000);
+ printf(" enabled, %ld MHz", (2 * get_bus_freq(0)) / 1000000);
mfsdram(DDR0_03, val);
printf(", CL%d)", DDR0_03_CASLAT_LIN_DECODE(val) >> 1);
diff --git a/cpu/ppc4xx/tlb.c b/cpu/ppc4xx/tlb.c
index f44822dbab..24a9a9cc28 100644
--- a/cpu/ppc4xx/tlb.c
+++ b/cpu/ppc4xx/tlb.c
@@ -316,12 +316,12 @@ static void program_tlb_addr(u64 phys_addr,
virt_addr += TLB_1KB_SIZE;
}
} else {
- printf("ERROR: no TLB size exists for the base address 0x%0X.\n",
+ printf("ERROR: no TLB size exists for the base address 0x%llx.\n",
phys_addr);
}
if (rc != 0)
- printf("ERROR: no TLB entries available for the base addr 0x%0X.\n",
+ printf("ERROR: no TLB entries available for the base addr 0x%llx.\n",
phys_addr);
}
diff --git a/cpu/ppc4xx/traps.c b/cpu/ppc4xx/traps.c
index 8b7e32a17b..55154b6f01 100644
--- a/cpu/ppc4xx/traps.c
+++ b/cpu/ppc4xx/traps.c
@@ -214,7 +214,7 @@ MachineCheckException(struct pt_regs *regs)
}
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
mfsdram(DDR0_00, val) ;
- printf("DDR0: DDR0_00 %p\n", val);
+ printf("DDR0: DDR0_00 %lx\n", val);
val = (val >> 16) & 0xff;
if (val & 0x80)
printf("DDR0: At least one interrupt active\n");
@@ -263,44 +263,44 @@ MachineCheckException(struct pt_regs *regs)
break;
default:
mfsdram(DDR0_01, value2);
- printf("DDR0: No DDR0 error know 0x%x %p\n", val, value2);
+ printf("DDR0: No DDR0 error know 0x%lx %x\n", val, value2);
}
mfsdram(DDR0_23, val);
if (((val >> 16) & 0xff) && corr_ecc)
- printf("DDR0: Syndrome for correctable ECC event 0x%x\n",
+ printf("DDR0: Syndrome for correctable ECC event 0x%lx\n",
(val >> 16) & 0xff);
mfsdram(DDR0_23, val);
if (((val >> 8) & 0xff) && uncorr_ecc)
- printf("DDR0: Syndrome for uncorrectable ECC event 0x%x\n",
+ printf("DDR0: Syndrome for uncorrectable ECC event 0x%lx\n",
(val >> 8) & 0xff);
mfsdram(DDR0_33, val);
if (val)
printf("DDR0: Address of command that caused an "
- "Out-of-Range interrupt %p\n", val);
+ "Out-of-Range interrupt %lx\n", val);
mfsdram(DDR0_34, val);
if (val && uncorr_ecc)
- printf("DDR0: Address of uncorrectable ECC event %p\n", val);
+ printf("DDR0: Address of uncorrectable ECC event %lx\n", val);
mfsdram(DDR0_35, val);
if (val && uncorr_ecc)
- printf("DDR0: Address of uncorrectable ECC event %p\n", val);
+ printf("DDR0: Address of uncorrectable ECC event %lx\n", val);
mfsdram(DDR0_36, val);
if (val && uncorr_ecc)
- printf("DDR0: Data of uncorrectable ECC event 0x%08x\n", val);
+ printf("DDR0: Data of uncorrectable ECC event 0x%08lx\n", val);
mfsdram(DDR0_37, val);
if (val && uncorr_ecc)
- printf("DDR0: Data of uncorrectable ECC event 0x%08x\n", val);
+ printf("DDR0: Data of uncorrectable ECC event 0x%08lx\n", val);
mfsdram(DDR0_38, val);
if (val && corr_ecc)
- printf("DDR0: Address of correctable ECC event %p\n", val);
+ printf("DDR0: Address of correctable ECC event %lx\n", val);
mfsdram(DDR0_39, val);
if (val && corr_ecc)
- printf("DDR0: Address of correctable ECC event %p\n", val);
+ printf("DDR0: Address of correctable ECC event %lx\n", val);
mfsdram(DDR0_40, val);
if (val && corr_ecc)
- printf("DDR0: Data of correctable ECC event 0x%08x\n", val);
+ printf("DDR0: Data of correctable ECC event 0x%08lx\n", val);
mfsdram(DDR0_41, val);
if (val && corr_ecc)
- printf("DDR0: Data of correctable ECC event 0x%08x\n", val);
+ printf("DDR0: Data of correctable ECC event 0x%08lx\n", val);
#endif /* CONFIG_440EPX */
#endif /* CONFIG_440 */
show_regs(regs);
generated by cgit (git 2.34.1) at 2024-12-28 05:40:44 +0000