diff options
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/at32ap/at32ap700x/gpio.c | 56 | ||||
| -rw-r--r-- | cpu/at32ap/pio.c | 56 |
2 files changed, 90 insertions, 22 deletions
diff --git a/cpu/at32ap/at32ap700x/gpio.c b/cpu/at32ap/at32ap700x/gpio.c index 3da35d4fe2..56ba2f90c6 100644 --- a/cpu/at32ap/at32ap700x/gpio.c +++ b/cpu/at32ap/at32ap700x/gpio.c @@ -149,24 +149,27 @@ void gpio_enable_mmci(void) #ifdef AT32AP700x_CHIP_HAS_SPI void gpio_enable_spi0(unsigned long cs_mask) { - u32 pa_mask = 0; - gpio_select_periph_A(GPIO_PIN_PA0, 0); /* MISO */ gpio_select_periph_A(GPIO_PIN_PA1, 0); /* MOSI */ gpio_select_periph_A(GPIO_PIN_PA2, 0); /* SCK */ - if (cs_mask & (1 << 0)) - pa_mask |= 1 << 3; /* NPCS0 */ - if (cs_mask & (1 << 1)) - pa_mask |= 1 << 4; /* NPCS1 */ - if (cs_mask & (1 << 2)) - pa_mask |= 1 << 5; /* NPCS2 */ - if (cs_mask & (1 << 3)) - pa_mask |= 1 << 20; /* NPCS3 */ - - __raw_writel(pa_mask, PIOA_BASE + 0x00); - __raw_writel(pa_mask, PIOA_BASE + 0x30); - __raw_writel(pa_mask, PIOA_BASE + 0x10); + /* Set up NPCSx as GPIO outputs, initially high */ + if (cs_mask & (1 << 0)) { + gpio_set_value(GPIO_PIN_PA3, 1); + gpio_select_pio(GPIO_PIN_PA3, GPIOF_OUTPUT); + } + if (cs_mask & (1 << 1)) { + gpio_set_value(GPIO_PIN_PA4, 1); + gpio_select_pio(GPIO_PIN_PA4, GPIOF_OUTPUT); + } + if (cs_mask & (1 << 2)) { + gpio_set_value(GPIO_PIN_PA5, 1); + gpio_select_pio(GPIO_PIN_PA5, GPIOF_OUTPUT); + } + if (cs_mask & (1 << 3)) { + gpio_set_value(GPIO_PIN_PA20, 1); + gpio_select_pio(GPIO_PIN_PA20, GPIOF_OUTPUT); + } } void gpio_enable_spi1(unsigned long cs_mask) @@ -175,13 +178,22 @@ void gpio_enable_spi1(unsigned long cs_mask) gpio_select_periph_B(GPIO_PIN_PB1, 0); /* MOSI */ gpio_select_periph_B(GPIO_PIN_PB5, 0); /* SCK */ - if (cs_mask & (1 << 0)) - gpio_select_periph_B(GPIO_PIN_PB2, 0); /* NPCS0 */ - if (cs_mask & (1 << 1)) - gpio_select_periph_B(GPIO_PIN_PB3, 0); /* NPCS1 */ - if (cs_mask & (1 << 2)) - gpio_select_periph_B(GPIO_PIN_PB4, 0); /* NPCS2 */ - if (cs_mask & (1 << 3)) - gpio_select_periph_A(GPIO_PIN_PA27, 0); /* NPCS3 */ + /* Set up NPCSx as GPIO outputs, initially high */ + if (cs_mask & (1 << 0)) { + gpio_set_value(GPIO_PIN_PB2, 1); + gpio_select_pio(GPIO_PIN_PB2, GPIOF_OUTPUT); + } + if (cs_mask & (1 << 1)) { + gpio_set_value(GPIO_PIN_PB3, 1); + gpio_select_pio(GPIO_PIN_PB3, GPIOF_OUTPUT); + } + if (cs_mask & (1 << 2)) { + gpio_set_value(GPIO_PIN_PB4, 1); + gpio_select_pio(GPIO_PIN_PB4, GPIOF_OUTPUT); + } + if (cs_mask & (1 << 3)) { + gpio_set_value(GPIO_PIN_PA27, 1); + gpio_select_pio(GPIO_PIN_PA27, GPIOF_OUTPUT); + } } #endif diff --git a/cpu/at32ap/pio.c b/cpu/at32ap/pio.c index 9ba0b8ea8b..f64004b659 100644 --- a/cpu/at32ap/pio.c +++ b/cpu/at32ap/pio.c @@ -58,3 +58,59 @@ void gpio_select_periph_B(unsigned int pin, int use_pullup) else pio2_writel(base, PUDR, mask); } + +void gpio_select_pio(unsigned int pin, unsigned long gpiof_flags) +{ + void *base = gpio_pin_to_addr(pin); + uint32_t mask = 1 << (pin & 0x1f); + + if (!base) + panic("Invalid GPIO pin %u\n", pin); + + if (gpiof_flags & GPIOF_OUTPUT) { + if (gpiof_flags & GPIOF_MULTIDRV) + pio2_writel(base, MDER, mask); + else + pio2_writel(base, MDDR, mask); + pio2_writel(base, PUDR, mask); + pio2_writel(base, OER, mask); + } else { + if (gpiof_flags & GPIOF_PULLUP) + pio2_writel(base, PUER, mask); + else + pio2_writel(base, PUDR, mask); + if (gpiof_flags & GPIOF_DEGLITCH) + pio2_writel(base, IFER, mask); + else + pio2_writel(base, IFDR, mask); + pio2_writel(base, ODR, mask); + } + + pio2_writel(base, PER, mask); +} + +void gpio_set_value(unsigned int pin, int value) +{ + void *base = gpio_pin_to_addr(pin); + uint32_t mask = 1 << (pin & 0x1f); + + if (!base) + panic("Invalid GPIO pin %u\n", pin); + + if (value) + pio2_writel(base, SODR, mask); + else + pio2_writel(base, CODR, mask); +} + +int gpio_get_value(unsigned int pin) +{ + void *base = gpio_pin_to_addr(pin); + int value; + + if (!base) + panic("Invalid GPIO pin %u\n", pin); + + value = pio2_readl(base, PDSR); + return (value >> (pin & 0x1f)) & 1; +} |