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-rw-r--r--doc/device-tree-bindings/spi/soft-spi.txt24
-rw-r--r--doc/device-tree-bindings/spi/spi-cadence.txt13
2 files changed, 22 insertions, 15 deletions
diff --git a/doc/device-tree-bindings/spi/soft-spi.txt b/doc/device-tree-bindings/spi/soft-spi.txt
index d09c1a5076..dfb5066473 100644
--- a/doc/device-tree-bindings/spi/soft-spi.txt
+++ b/doc/device-tree-bindings/spi/soft-spi.txt
@@ -6,11 +6,15 @@ performance will typically be much lower than a real SPI bus.
The soft SPI node requires the following properties:
-compatible: "u-boot,soft-spi"
-soft_spi_cs: GPIO number to use for SPI chip select (output)
-soft_spi_sclk: GPIO number to use for SPI clock (output)
-soft_spi_mosi: GPIO number to use for SPI MOSI line (output)
-soft_spi_miso GPIO number to use for SPI MISO line (input)
+Mandatory properties:
+compatible: "spi-gpio"
+cs-gpios: GPIOs to use for SPI chip select (output)
+gpio-sck: GPIO to use for SPI clock (output)
+And at least one of:
+gpio-mosi: GPIO to use for SPI MOSI line (output)
+gpio-miso: GPIO to use for SPI MISO line (input)
+
+Optional propertie:
spi-delay-us: Number of microseconds of delay between each CS transition
The GPIOs should be specified as required by the GPIO controller referenced.
@@ -21,11 +25,11 @@ typically holds the GPIO number.
Example:
soft-spi {
- compatible = "u-boot,soft-spi";
- cs-gpio = <&gpio 235 0>; /* Y43 */
- sclk-gpio = <&gpio 225 0>; /* Y31 */
- mosi-gpio = <&gpio 227 0>; /* Y33 */
- miso-gpio = <&gpio 224 0>; /* Y30 */
+ compatible = "spi-gpio";
+ cs-gpios = <&gpio 235 0>; /* Y43 */
+ gpio-sck = <&gpio 225 0>; /* Y31 */
+ gpio-mosi = <&gpio 227 0>; /* Y33 */
+ gpio-miso = <&gpio 224 0>; /* Y30 */
spi-delay-us = <1>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/doc/device-tree-bindings/spi/spi-cadence.txt b/doc/device-tree-bindings/spi/spi-cadence.txt
index c1e2233d7c..74c82080fc 100644
--- a/doc/device-tree-bindings/spi/spi-cadence.txt
+++ b/doc/device-tree-bindings/spi/spi-cadence.txt
@@ -6,7 +6,10 @@ Required properties:
- reg : 1.Physical base address and size of SPI registers map.
2. Physical base address & size of NOR Flash.
- clocks : Clock phandles (see clock bindings for details).
-- sram-size : spi controller sram size.
+- cdns,fifo-depth : Size of the data FIFO in words.
+- cdns,fifo-width : Bus width of the data FIFO in bytes.
+- cdns,trigger-address : 32-bit indirect AHB trigger address.
+- cdns,is-decoded-cs : Flag to indicate whether decoder is used or not.
- status : enable in requried dts.
connected flash properties
@@ -15,14 +18,14 @@ connected flash properties
- spi-max-frequency : Max supported spi frequency.
- page-size : Flash page size.
- block-size : Flash memory block size.
-- tshsl-ns : Added delay in master reference clocks (ref_clk) for
+- cdns,tshsl-ns : Added delay in master reference clocks (ref_clk) for
the length that the master mode chip select outputs
are de-asserted between transactions.
-- tsd2d-ns : Delay in master reference clocks (ref_clk) between one
+- cdns,tsd2d-ns : Delay in master reference clocks (ref_clk) between one
chip select being de-activated and the activation of
another.
-- tchsh-ns : Delay in master reference clocks between last bit of
+- cdns,tchsh-ns : Delay in master reference clocks between last bit of
current transaction and de-asserting the device chip
select (n_ss_out).
-- tslch-ns : Delay in master reference clocks between setting
+- cdns,tslch-ns : Delay in master reference clocks between setting
n_ss_out low and first bit transfer