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path: root/drivers/crypto/fsl/desc_constr.h
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Diffstat (limited to 'drivers/crypto/fsl/desc_constr.h')
-rw-r--r--drivers/crypto/fsl/desc_constr.h26
1 files changed, 26 insertions, 0 deletions
diff --git a/drivers/crypto/fsl/desc_constr.h b/drivers/crypto/fsl/desc_constr.h
index f9cae9144a..2559ccda8c 100644
--- a/drivers/crypto/fsl/desc_constr.h
+++ b/drivers/crypto/fsl/desc_constr.h
@@ -36,6 +36,23 @@
LDST_SRCDST_WORD_DECOCTRL | \
(LDOFF_ENABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT))
+#ifdef CONFIG_PHYS_64BIT
+union ptr_addr_t {
+ u64 m_whole;
+ struct {
+#ifdef CONFIG_SYS_FSL_SEC_LE
+ u32 low;
+ u32 high;
+#elif defined(CONFIG_SYS_FSL_SEC_BE)
+ u32 high;
+ u32 low;
+#else
+#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
+#endif
+ } m_halfs;
+};
+#endif
+
static inline int desc_len(u32 *desc)
{
return *desc & HDR_DESCLEN_MASK;
@@ -65,7 +82,16 @@ static inline void append_ptr(u32 *desc, dma_addr_t ptr)
{
dma_addr_t *offset = (dma_addr_t *)desc_end(desc);
+#ifdef CONFIG_PHYS_64BIT
+ /* The Position of low and high part of 64 bit address
+ * will depend on the endianness of CAAM Block */
+ union ptr_addr_t ptr_addr;
+ ptr_addr.m_halfs.high = (u32)(ptr >> 32);
+ ptr_addr.m_halfs.low = (u32)ptr;
+ *offset = ptr_addr.m_whole;
+#else
*offset = ptr;
+#endif
(*desc) += CAAM_PTR_SZ / CAAM_CMD_SZ;
}