diff options
Diffstat (limited to 'drivers/ddr/marvell/a38x')
| -rw-r--r-- | drivers/ddr/marvell/a38x/ddr3_a38x.c | 51 | ||||
| -rw-r--r-- | drivers/ddr/marvell/a38x/ddr3_a38x_mc_static.h | 225 | ||||
| -rw-r--r-- | drivers/ddr/marvell/a38x/ddr3_debug.c | 9 | ||||
| -rw-r--r-- | drivers/ddr/marvell/a38x/ddr3_init.c | 29 | ||||
| -rw-r--r-- | drivers/ddr/marvell/a38x/ddr3_init.h | 1 | ||||
| -rw-r--r-- | drivers/ddr/marvell/a38x/ddr3_training.c | 41 | ||||
| -rw-r--r-- | drivers/ddr/marvell/a38x/ddr3_training_static.c | 438 |
7 files changed, 0 insertions, 794 deletions
diff --git a/drivers/ddr/marvell/a38x/ddr3_a38x.c b/drivers/ddr/marvell/a38x/ddr3_a38x.c index e152e842ae..c356d09008 100644 --- a/drivers/ddr/marvell/a38x/ddr3_a38x.c +++ b/drivers/ddr/marvell/a38x/ddr3_a38x.c @@ -76,41 +76,6 @@ struct trip_delay_element a38x_board_round_trip_delay_array[] = { { 4282, 6160 } /* ECC PUP */ }; -#ifdef STATIC_ALGO_SUPPORT -/* package trace */ -static struct trip_delay_element a38x_package_round_trip_delay_array[] = { - /* IF BUS DQ_DELAY CK_DELAY */ - { 0, 0 }, - { 0, 0 }, - { 0, 0 }, - { 0, 0 }, - { 0, 0 }, - { 0, 0 }, - { 0, 0 }, - { 0, 0 }, - { 0, 0 }, - { 0, 0 }, - { 0, 0 }, - { 0, 0 }, - { 0, 0 }, - { 0, 0 }, - { 0, 0 }, - { 0, 0 }, - { 0, 0 }, - { 0, 0 }, - { 0, 0 }, - { 0, 0 } -}; - -static int a38x_silicon_delay_offset[] = { - /* board 0 */ - 0, - /* board 1 */ - 0, - /* board 2 */ - 0 -}; -#endif static u8 a38x_bw_per_freq[DDR_FREQ_LIMIT] = { 0x3, /* DDR_FREQ_100 */ @@ -367,22 +332,6 @@ static int ddr3_tip_init_a38x_silicon(u32 dev_num, u32 board_id) ddr3_tip_register_dq_table(dev_num, dq_bit_map_2_phy_pin); -#ifdef STATIC_ALGO_SUPPORT - { - struct hws_tip_static_config_info static_config; - u32 board_offset = - board_id * A38X_NUMBER_OF_INTERFACES * - tm->num_of_bus_per_interface; - - static_config.silicon_delay = - a38x_silicon_delay_offset[board_id]; - static_config.package_trace_arr = - a38x_package_round_trip_delay_array; - static_config.board_trace_arr = - &a38x_board_round_trip_delay_array[board_offset]; - ddr3_tip_init_static_config_db(dev_num, &static_config); - } -#endif status = ddr3_tip_a38x_get_init_freq(dev_num, &ddr_freq); if (MV_OK != status) { DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR, diff --git a/drivers/ddr/marvell/a38x/ddr3_a38x_mc_static.h b/drivers/ddr/marvell/a38x/ddr3_a38x_mc_static.h deleted file mode 100644 index a5b4f70458..0000000000 --- a/drivers/ddr/marvell/a38x/ddr3_a38x_mc_static.h +++ /dev/null @@ -1,225 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) Marvell International Ltd. and its affiliates - */ - -#ifndef _DDR3_A38X_MC_STATIC_H -#define _DDR3_A38X_MC_STATIC_H - -#include "ddr3_a38x.h" - -#ifdef SUPPORT_STATIC_DUNIT_CONFIG - -#ifdef CONFIG_CUSTOMER_BOARD_SUPPORT -static struct reg_data ddr3_customer_800[] = { - /* parameters for customer board (based on 800MHZ) */ - {0x1400, 0x7b00cc30, 0xffffffff}, - {0x1404, 0x36301820, 0xffffffff}, - {0x1408, 0x5415baab, 0xffffffff}, - {0x140c, 0x38411def, 0xffffffff}, - {0x1410, 0x18300000, 0xffffffff}, - {0x1414, 0x00000700, 0xffffffff}, - {0x1424, 0x0060f3ff, 0xffffffff}, - {0x1428, 0x0011a940, 0xffffffff}, - {0x142c, 0x28c5134, 0xffffffff}, - {0x1474, 0x00000000, 0xffffffff}, - {0x147c, 0x0000d771, 0xffffffff}, - {0x1494, 0x00030000, 0xffffffff}, - {0x149c, 0x00000300, 0xffffffff}, - {0x14a8, 0x00000000, 0xffffffff}, - {0x14cc, 0xbd09000d, 0xffffffff}, - {0x1504, 0xfffffff1, 0xffffffff}, - {0x150c, 0xffffffe5, 0xffffffff}, - {0x1514, 0x00000000, 0xffffffff}, - {0x151c, 0x00000000, 0xffffffff}, - {0x1538, 0x00000b0b, 0xffffffff}, - {0x153c, 0x00000c0c, 0xffffffff}, - {0x15d0, 0x00000670, 0xffffffff}, - {0x15d4, 0x00000046, 0xffffffff}, - {0x15d8, 0x00000010, 0xffffffff}, - {0x15dc, 0x00000000, 0xffffffff}, - {0x15e0, 0x00000023, 0xffffffff}, - {0x15e4, 0x00203c18, 0xffffffff}, - {0x15ec, 0xf8000019, 0xffffffff}, - {0x16a0, 0xcc000006, 0xffffffff}, /* Clock Delay */ - {0xe4124, 0x08008073, 0xffffffff}, /* AVS BG default */ - {0, 0, 0} -}; - -#else /* CONFIG_CUSTOMER_BOARD_SUPPORT */ - -struct reg_data ddr3_a38x_933[MV_MAX_DDR3_STATIC_SIZE] = { - /* parameters for 933MHZ */ - {0x1400, 0x7b00ce3a, 0xffffffff}, - {0x1404, 0x36301820, 0xffffffff}, - {0x1408, 0x7417eccf, 0xffffffff}, - {0x140c, 0x3e421f98, 0xffffffff}, - {0x1410, 0x1a300000, 0xffffffff}, - {0x1414, 0x00000700, 0xffffffff}, - {0x1424, 0x0060f3ff, 0xffffffff}, - {0x1428, 0x0013ca50, 0xffffffff}, - {0x142c, 0x028c5165, 0xffffffff}, - {0x1474, 0x00000000, 0xffffffff}, - {0x147c, 0x0000e871, 0xffffffff}, - {0x1494, 0x00010000, 0xffffffff}, - {0x149c, 0x00000001, 0xffffffff}, - {0x14a8, 0x00000000, 0xffffffff}, - {0x14cc, 0xbd09000d, 0xffffffff}, - {0x1504, 0xffffffe1, 0xffffffff}, - {0x150c, 0xffffffe5, 0xffffffff}, - {0x1514, 0x00000000, 0xffffffff}, - {0x151c, 0x00000000, 0xffffffff}, - {0x1538, 0x00000d0d, 0xffffffff}, - {0x153c, 0x00000d0d, 0xffffffff}, - {0x15d0, 0x00000608, 0xffffffff}, - {0x15d4, 0x00000044, 0xffffffff}, - {0x15d8, 0x00000020, 0xffffffff}, - {0x15dc, 0x00000000, 0xffffffff}, - {0x15e0, 0x00000021, 0xffffffff}, - {0x15e4, 0x00203c18, 0xffffffff}, - {0x15ec, 0xf8000019, 0xffffffff}, - {0x16a0, 0xcc000006, 0xffffffff}, /* Clock Delay */ - {0xe4124, 0x08008073, 0xffffffff}, /* AVS BG default */ - {0, 0, 0} -}; - -static struct reg_data ddr3_a38x_800[] = { - /* parameters for 800MHZ */ - {0x1400, 0x7b00cc30, 0xffffffff}, - {0x1404, 0x36301820, 0xffffffff}, - {0x1408, 0x5415baab, 0xffffffff}, - {0x140c, 0x38411def, 0xffffffff}, - {0x1410, 0x18300000, 0xffffffff}, - {0x1414, 0x00000700, 0xffffffff}, - {0x1424, 0x0060f3ff, 0xffffffff}, - {0x1428, 0x0011a940, 0xffffffff}, - {0x142c, 0x28c5134, 0xffffffff}, - {0x1474, 0x00000000, 0xffffffff}, - {0x147c, 0x0000d771, 0xffffffff}, - {0x1494, 0x00030000, 0xffffffff}, - {0x149c, 0x00000300, 0xffffffff}, - {0x14a8, 0x00000000, 0xffffffff}, - {0x14cc, 0xbd09000d, 0xffffffff}, - {0x1504, 0xfffffff1, 0xffffffff}, - {0x150c, 0xffffffe5, 0xffffffff}, - {0x1514, 0x00000000, 0xffffffff}, - {0x151c, 0x00000000, 0xffffffff}, - {0x1538, 0x00000b0b, 0xffffffff}, - {0x153c, 0x00000c0c, 0xffffffff}, - {0x15d0, 0x00000670, 0xffffffff}, - {0x15d4, 0x00000046, 0xffffffff}, - {0x15d8, 0x00000010, 0xffffffff}, - {0x15dc, 0x00000000, 0xffffffff}, - {0x15e0, 0x00000023, 0xffffffff}, - {0x15e4, 0x00203c18, 0xffffffff}, - {0x15ec, 0xf8000019, 0xffffffff}, - {0x16a0, 0xcc000006, 0xffffffff}, /* Clock Delay */ - {0xe4124, 0x08008073, 0xffffffff}, /* AVS BG default */ - {0, 0, 0} -}; - -static struct reg_data ddr3_a38x_667[] = { - /* parameters for 667MHZ */ - /* DDR SDRAM Configuration Register */ - {0x1400, 0x7b00ca28, 0xffffffff}, - /* Dunit Control Low Register - kw28 bit12 low (disable CLK1) */ - {0x1404, 0x36301820, 0xffffffff}, - /* DDR SDRAM Timing (Low) Register */ - {0x1408, 0x43149997, 0xffffffff}, - /* DDR SDRAM Timing (High) Register */ - {0x140c, 0x38411bc7, 0xffffffff}, - /* DDR SDRAM Address Control Register */ - {0x1410, 0x14330000, 0xffffffff}, - /* DDR SDRAM Open Pages Control Register */ - {0x1414, 0x00000700, 0xffffffff}, - /* Dunit Control High Register (2 :1 - bits 15:12 = 0xd) */ - {0x1424, 0x0060f3ff, 0xffffffff}, - /* Dunit Control High Register */ - {0x1428, 0x000f8830, 0xffffffff}, - /* Dunit Control High Register (2:1 - bit 29 = '1') */ - {0x142c, 0x28c50f8, 0xffffffff}, - {0x147c, 0x0000c671, 0xffffffff}, - /* DDR SDRAM ODT Control (Low) Register */ - {0x1494, 0x00030000, 0xffffffff}, - /* DDR SDRAM ODT Control (High) Register, will be configured at WL */ - {0x1498, 0x00000000, 0xffffffff}, - /* DDR Dunit ODT Control Register */ - {0x149c, 0x00000300, 0xffffffff}, - {0x14a8, 0x00000000, 0xffffffff}, /* */ - {0x14cc, 0xbd09000d, 0xffffffff}, /* */ - {0x1474, 0x00000000, 0xffffffff}, - /* Read Data Sample Delays Register */ - {0x1538, 0x00000009, 0xffffffff}, - /* Read Data Ready Delay Register */ - {0x153c, 0x0000000c, 0xffffffff}, - {0x1504, 0xfffffff1, 0xffffffff}, /* */ - {0x150c, 0xffffffe5, 0xffffffff}, /* */ - {0x1514, 0x00000000, 0xffffffff}, /* */ - {0x151c, 0x0, 0xffffffff}, /* */ - {0x15d0, 0x00000650, 0xffffffff}, /* MR0 */ - {0x15d4, 0x00000046, 0xffffffff}, /* MR1 */ - {0x15d8, 0x00000010, 0xffffffff}, /* MR2 */ - {0x15dc, 0x00000000, 0xffffffff}, /* MR3 */ - {0x15e0, 0x23, 0xffffffff}, /* */ - {0x15e4, 0x00203c18, 0xffffffff}, /* ZQC Configuration Register */ - {0x15ec, 0xf8000019, 0xffffffff}, /* DDR PHY */ - {0x16a0, 0xcc000006, 0xffffffff}, /* Clock Delay */ - {0xe4124, 0x08008073, 0xffffffff}, /* AVS BG default */ - {0, 0, 0} -}; - -static struct reg_data ddr3_a38x_533[] = { - /* parameters for 533MHZ */ - /* DDR SDRAM Configuration Register */ - {0x1400, 0x7b00d040, 0xffffffff}, - /* Dunit Control Low Register - kw28 bit12 low (disable CLK1) */ - {0x1404, 0x36301820, 0xffffffff}, - /* DDR SDRAM Timing (Low) Register */ - {0x1408, 0x33137772, 0xffffffff}, - /* DDR SDRAM Timing (High) Register */ - {0x140c, 0x3841199f, 0xffffffff}, - /* DDR SDRAM Address Control Register */ - {0x1410, 0x10330000, 0xffffffff}, - /* DDR SDRAM Open Pages Control Register */ - {0x1414, 0x00000700, 0xffffffff}, - /* Dunit Control High Register (2 :1 - bits 15:12 = 0xd) */ - {0x1424, 0x0060f3ff, 0xffffffff}, - /* Dunit Control High Register */ - {0x1428, 0x000d6720, 0xffffffff}, - /* Dunit Control High Register (2:1 - bit 29 = '1') */ - {0x142c, 0x028c50c3, 0xffffffff}, - {0x147c, 0x0000b571, 0xffffffff}, - /* DDR SDRAM ODT Control (Low) Register */ - {0x1494, 0x00030000, 0xffffffff}, - /* DDR SDRAM ODT Control (High) Register, will be configured at WL */ - {0x1498, 0x00000000, 0xffffffff}, - /* DDR Dunit ODT Control Register */ - {0x149c, 0x00000003, 0xffffffff}, - {0x14a8, 0x00000000, 0xffffffff}, /* */ - {0x14cc, 0xbd09000d, 0xffffffff}, /* */ - {0x1474, 0x00000000, 0xffffffff}, - /* Read Data Sample Delays Register */ - {0x1538, 0x00000707, 0xffffffff}, - /* Read Data Ready Delay Register */ - {0x153c, 0x00000707, 0xffffffff}, - {0x1504, 0xffffffe1, 0xffffffff}, /* */ - {0x150c, 0xffffffe5, 0xffffffff}, /* */ - {0x1514, 0x00000000, 0xffffffff}, /* */ - {0x151c, 0x00000000, 0xffffffff}, /* */ - {0x15d0, 0x00000630, 0xffffffff}, /* MR0 */ - {0x15d4, 0x00000046, 0xffffffff}, /* MR1 */ - {0x15d8, 0x00000008, 0xffffffff}, /* MR2 */ - {0x15dc, 0x00000000, 0xffffffff}, /* MR3 */ - {0x15e0, 0x00000023, 0xffffffff}, /* */ - {0x15e4, 0x00203c18, 0xffffffff}, /* ZQC Configuration Register */ - {0x15ec, 0xf8000019, 0xffffffff}, /* DDR PHY */ - {0x16a0, 0xcc000006, 0xffffffff}, /* Clock Delay */ - {0xe4124, 0x08008073, 0xffffffff}, /* AVS BG default */ - {0, 0, 0} -}; - -#endif /* CONFIG_CUSTOMER_BOARD_SUPPORT */ - -#endif /* SUPPORT_STATIC_DUNIT_CONFIG */ - -#endif /* _DDR3_A38X_MC_STATIC_H */ diff --git a/drivers/ddr/marvell/a38x/ddr3_debug.c b/drivers/ddr/marvell/a38x/ddr3_debug.c index 68ab9476cc..c14400840e 100644 --- a/drivers/ddr/marvell/a38x/ddr3_debug.c +++ b/drivers/ddr/marvell/a38x/ddr3_debug.c @@ -867,15 +867,6 @@ static int ddr3_tip_access_atr(u32 dev_num, u32 flag_id, u32 value, u32 **ptr) case 0x25: *ptr = (u32 *)&is_adll_calib_before_init; break; -#ifdef STATIC_ALGO_SUPPORT - case 0x26: - *ptr = (u32 *)&(silicon_delay[0]); - break; - - case 0x27: - *ptr = (u32 *)&wl_debug_delay; - break; -#endif case 0x28: *ptr = (u32 *)&is_tune_result; break; diff --git a/drivers/ddr/marvell/a38x/ddr3_init.c b/drivers/ddr/marvell/a38x/ddr3_init.c index 1c5b1f75ca..73d984ba66 100644 --- a/drivers/ddr/marvell/a38x/ddr3_init.c +++ b/drivers/ddr/marvell/a38x/ddr3_init.c @@ -59,20 +59,6 @@ struct dram_modes { }; struct dram_modes ddr_modes[] = { -#ifdef SUPPORT_STATIC_DUNIT_CONFIG - /* Conf name, CPUFreq, Fab_freq, Chip ID, Chip/Board, MC regs*/ -#ifdef CONFIG_CUSTOMER_BOARD_SUPPORT - {"a38x_customer_0_800", DDR_FREQ_800, 0, 0x0, A38X_CUSTOMER_BOARD_ID0, - ddr3_customer_800}, - {"a38x_customer_1_800", DDR_FREQ_800, 0, 0x0, A38X_CUSTOMER_BOARD_ID1, - ddr3_customer_800}, -#else - {"a38x_533", DDR_FREQ_533, 0, 0x0, MARVELL_BOARD, ddr3_a38x_533}, - {"a38x_667", DDR_FREQ_667, 0, 0x0, MARVELL_BOARD, ddr3_a38x_667}, - {"a38x_800", DDR_FREQ_800, 0, 0x0, MARVELL_BOARD, ddr3_a38x_800}, - {"a38x_933", DDR_FREQ_933, 0, 0x0, MARVELL_BOARD, ddr3_a38x_933}, -#endif -#endif }; #endif /* defined(CONFIG_ARMADA_38X) */ @@ -91,9 +77,6 @@ static char *ddr_type = "DDR3"; */ u8 generic_init_controller = 1; -#ifdef SUPPORT_STATIC_DUNIT_CONFIG -static u32 ddr3_get_static_ddr_mode(void); -#endif static int ddr3_hws_tune_training_params(u8 dev_num); /* device revision */ @@ -342,18 +325,6 @@ int ddr3_init(void) /* Set X-BAR windows for the training sequence */ ddr3_save_and_set_training_windows(win); -#ifdef SUPPORT_STATIC_DUNIT_CONFIG - /* - * Load static controller configuration (in case dynamic/generic init - * is not enabled - */ - if (generic_init_controller == 0) { - ddr3_tip_init_specific_reg_config(0, - ddr_modes - [ddr3_get_static_ddr_mode - ()].regs); - } -#endif /* Tune training algo paramteres */ status = ddr3_hws_tune_training_params(0); diff --git a/drivers/ddr/marvell/a38x/ddr3_init.h b/drivers/ddr/marvell/a38x/ddr3_init.h index 05ff62b041..8cb645ffb5 100644 --- a/drivers/ddr/marvell/a38x/ddr3_init.h +++ b/drivers/ddr/marvell/a38x/ddr3_init.h @@ -8,7 +8,6 @@ #if defined(CONFIG_ARMADA_38X) #include "ddr3_a38x.h" -#include "ddr3_a38x_mc_static.h" #include "ddr3_a38x_topology.h" #endif #include "ddr3_hws_hw_training.h" diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c index c4a150ea74..fee589b746 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training.c +++ b/drivers/ddr/marvell/a38x/ddr3_training.c @@ -635,12 +635,6 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_ MASK_ALL_BITS)); } } else { -#ifdef STATIC_ALGO_SUPPORT - CHECK_STATUS(ddr3_tip_static_init_controller(dev_num)); -#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X) - CHECK_STATUS(ddr3_tip_static_phy_init_controller(dev_num)); -#endif -#endif /* STATIC_ALGO_SUPPORT */ } for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { @@ -814,25 +808,6 @@ int hws_ddr3_tip_run_alg(u32 dev_num, enum hws_algo_type algo_type) if (algo_type == ALGO_TYPE_DYNAMIC) { ret = ddr3_tip_ddr3_auto_tune(dev_num); } else { -#ifdef STATIC_ALGO_SUPPORT - { - enum hws_ddr_freq freq; - freq = init_freq; - - /* add to mask */ - if (is_adll_calib_before_init != 0) { - printf("with adll calib before init\n"); - adll_calibration(dev_num, ACCESS_TYPE_MULTICAST, - 0, freq); - } - /* - * Frequency per interface is not relevant, - * only interface 0 - */ - ret = ddr3_tip_run_static_alg(dev_num, - freq); - } -#endif } if (ret != MV_OK) { @@ -2027,22 +2002,6 @@ static int ddr3_tip_ddr3_training_main_flow(u32 dev_num) } } -#ifdef STATIC_ALGO_SUPPORT - if (mask_tune_func & STATIC_LEVELING_MASK_BIT) { - training_stage = STATIC_LEVELING; - DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, - ("STATIC_LEVELING_MASK_BIT\n")); - ret = ddr3_tip_run_static_alg(dev_num, freq); - if (is_reg_dump != 0) - ddr3_tip_reg_dump(dev_num); - if (ret != MV_OK) { - DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR, - ("ddr3_tip_run_static_alg failure\n")); - if (debug_mode == 0) - return MV_FAIL; - } - } -#endif if (mask_tune_func & SET_LOW_FREQ_MASK_BIT) { training_stage = SET_LOW_FREQ; diff --git a/drivers/ddr/marvell/a38x/ddr3_training_static.c b/drivers/ddr/marvell/a38x/ddr3_training_static.c index dddbfe17b0..1b4bfb2e02 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_static.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_static.c @@ -25,444 +25,6 @@ u32 g_odt_config_1cs = 0x10000; u32 g_rtt_nom = 0x44; u32 g_dic = 0x2; -#ifdef STATIC_ALGO_SUPPORT - -#define PARAM_NOT_CARE 0 -#define MAX_STATIC_SEQ 48 - -u32 silicon_delay[HWS_MAX_DEVICE_NUM]; -struct hws_tip_static_config_info static_config[HWS_MAX_DEVICE_NUM]; -static reg_data *static_init_controller_config[HWS_MAX_DEVICE_NUM]; - -/* debug delay in write leveling */ -int wl_debug_delay = 0; -/* pup register #3 for functional board */ -int function_reg_value = 8; -u32 silicon; - -u32 read_ready_delay_phase_offset[] = { 4, 4, 4, 4, 6, 6, 6, 6 }; - -static struct cs_element chip_select_map[] = { - /* CS Value (single only) Num_CS */ - {0, 0}, - {0, 1}, - {1, 1}, - {0, 2}, - {2, 1}, - {0, 2}, - {0, 2}, - {0, 3}, - {3, 1}, - {0, 2}, - {0, 2}, - {0, 3}, - {0, 2}, - {0, 3}, - {0, 3}, - {0, 4} -}; - -/* - * Register static init controller DB - */ -int ddr3_tip_init_specific_reg_config(u32 dev_num, reg_data *reg_config_arr) -{ - static_init_controller_config[dev_num] = reg_config_arr; - return MV_OK; -} - -/* - * Register static info DB - */ -int ddr3_tip_init_static_config_db( - u32 dev_num, struct hws_tip_static_config_info *static_config_info) -{ - static_config[dev_num].board_trace_arr = - static_config_info->board_trace_arr; - static_config[dev_num].package_trace_arr = - static_config_info->package_trace_arr; - silicon_delay[dev_num] = static_config_info->silicon_delay; - - return MV_OK; -} - -/* - * Static round trip flow - Calculates the total round trip delay. - */ -int ddr3_tip_static_round_trip_arr_build(u32 dev_num, - struct trip_delay_element *table_ptr, - int is_wl, u32 *round_trip_delay_arr) -{ - u32 bus_index, global_bus; - u32 if_id; - u32 bus_per_interface; - int sign; - u32 temp; - u32 board_trace; - struct trip_delay_element *pkg_delay_ptr; - struct hws_topology_map *tm = ddr3_get_topology_map(); - - /* - * In WL we calc the diff between Clock to DQs in RL we sum the round - * trip of Clock and DQs - */ - sign = (is_wl) ? -1 : 1; - - bus_per_interface = GET_TOPOLOGY_NUM_OF_BUSES(); - - for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { - VALIDATE_ACTIVE(tm->if_act_mask, if_id); - for (bus_index = 0; bus_index < bus_per_interface; - bus_index++) { - VALIDATE_ACTIVE(tm->bus_act_mask, bus_index); - global_bus = (if_id * bus_per_interface) + bus_index; - - /* calculate total trip delay (package and board) */ - board_trace = (table_ptr[global_bus].dqs_delay * sign) + - table_ptr[global_bus].ck_delay; - temp = (board_trace * 163) / 1000; - - /* Convert the length to delay in psec units */ - pkg_delay_ptr = - static_config[dev_num].package_trace_arr; - round_trip_delay_arr[global_bus] = temp + - (int)(pkg_delay_ptr[global_bus].dqs_delay * - sign) + - (int)pkg_delay_ptr[global_bus].ck_delay + - (int)((is_wl == 1) ? wl_debug_delay : - (int)silicon_delay[dev_num]); - DEBUG_TRAINING_STATIC_IP( - DEBUG_LEVEL_TRACE, - ("Round Trip Build round_trip_delay_arr[0x%x]: 0x%x temp 0x%x\n", - global_bus, round_trip_delay_arr[global_bus], - temp)); - } - } - - return MV_OK; -} - -/* - * Write leveling for static flow - calculating the round trip delay of the - * DQS signal. - */ -int ddr3_tip_write_leveling_static_config(u32 dev_num, u32 if_id, - enum hws_ddr_freq frequency, - u32 *round_trip_delay_arr) -{ - u32 bus_index; /* index to the bus loop */ - u32 bus_start_index; - u32 bus_per_interface; - u32 phase = 0; - u32 adll = 0, adll_cen, adll_inv, adll_final; - u32 adll_period = MEGA / freq_val[frequency] / 64; - - DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE, - ("ddr3_tip_write_leveling_static_config\n")); - DEBUG_TRAINING_STATIC_IP( - DEBUG_LEVEL_TRACE, - ("dev_num 0x%x IF 0x%x freq %d (adll_period 0x%x)\n", - dev_num, if_id, frequency, adll_period)); - - bus_per_interface = GET_TOPOLOGY_NUM_OF_BUSES(); - bus_start_index = if_id * bus_per_interface; - for (bus_index = bus_start_index; - bus_index < (bus_start_index + bus_per_interface); bus_index++) { - VALIDATE_ACTIVE(tm->bus_act_mask, bus_index); - phase = round_trip_delay_arr[bus_index] / (32 * adll_period); - adll = (round_trip_delay_arr[bus_index] - - (phase * 32 * adll_period)) / adll_period; - adll = (adll > 31) ? 31 : adll; - adll_cen = 16 + adll; - adll_inv = adll_cen / 32; - adll_final = adll_cen - (adll_inv * 32); - adll_final = (adll_final > 31) ? 31 : adll_final; - - DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE, - ("\t%d - phase 0x%x adll 0x%x\n", - bus_index, phase, adll)); - /* - * Writing to all 4 phy of Interface number, - * bit 0 \96 4 \96 ADLL, bit 6-8 phase - */ - CHECK_STATUS(ddr3_tip_bus_read_modify_write - (dev_num, ACCESS_TYPE_UNICAST, if_id, - (bus_index % 4), DDR_PHY_DATA, - PHY_WRITE_DELAY(cs), - ((phase << 6) + (adll & 0x1f)), 0x1df)); - CHECK_STATUS(ddr3_tip_bus_write - (dev_num, ACCESS_TYPE_UNICAST, if_id, - ACCESS_TYPE_UNICAST, (bus_index % 4), - DDR_PHY_DATA, WRITE_CENTRALIZATION_PHY_REG, - ((adll_inv & 0x1) << 5) + adll_final)); - } - - return MV_OK; -} - -/* - * Read leveling for static flow - */ -int ddr3_tip_read_leveling_static_config(u32 dev_num, - u32 if_id, - enum hws_ddr_freq frequency, - u32 *total_round_trip_delay_arr) -{ - u32 cs, data0, data1, data3 = 0; - u32 bus_index; /* index to the bus loop */ - u32 bus_start_index; - u32 phase0, phase1, max_phase; - u32 adll0, adll1; - u32 cl_value; - u32 min_delay; - u32 sdr_period = MEGA / freq_val[frequency]; - u32 ddr_period = MEGA / freq_val[frequency] / 2; - u32 adll_period = MEGA / freq_val[frequency] / 64; - enum hws_speed_bin speed_bin_index; - u32 rd_sample_dly[MAX_CS_NUM] = { 0 }; - u32 rd_ready_del[MAX_CS_NUM] = { 0 }; - u32 bus_per_interface = GET_TOPOLOGY_NUM_OF_BUSES(); - struct hws_topology_map *tm = ddr3_get_topology_map(); - - DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE, - ("ddr3_tip_read_leveling_static_config\n")); - DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE, - ("dev_num 0x%x ifc 0x%x freq %d\n", dev_num, - if_id, frequency)); - DEBUG_TRAINING_STATIC_IP( - DEBUG_LEVEL_TRACE, - ("Sdr_period 0x%x Ddr_period 0x%x adll_period 0x%x\n", - sdr_period, ddr_period, adll_period)); - - if (tm->interface_params[first_active_if].memory_freq == - frequency) { - cl_value = tm->interface_params[first_active_if].cas_l; - DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE, - ("cl_value 0x%x\n", cl_value)); - } else { - speed_bin_index = tm->interface_params[if_id].speed_bin_index; - cl_value = cas_latency_table[speed_bin_index].cl_val[frequency]; - DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE, - ("cl_value 0x%x speed_bin_index %d\n", - cl_value, speed_bin_index)); - } - - bus_start_index = if_id * bus_per_interface; - - for (bus_index = bus_start_index; - bus_index < (bus_start_index + bus_per_interface); - bus_index += 2) { - VALIDATE_ACTIVE(tm->bus_act_mask, bus_index); - cs = chip_select_map[ - tm->interface_params[if_id].as_bus_params[ - (bus_index % 4)].cs_bitmask].cs_num; - - /* read sample delay calculation */ - min_delay = (total_round_trip_delay_arr[bus_index] < - total_round_trip_delay_arr[bus_index + 1]) ? - total_round_trip_delay_arr[bus_index] : - total_round_trip_delay_arr[bus_index + 1]; - /* round down */ - rd_sample_dly[cs] = 2 * (min_delay / (sdr_period * 2)); - DEBUG_TRAINING_STATIC_IP( - DEBUG_LEVEL_TRACE, - ("\t%d - min_delay 0x%x cs 0x%x rd_sample_dly[cs] 0x%x\n", - bus_index, min_delay, cs, rd_sample_dly[cs])); - - /* phase calculation */ - phase0 = (total_round_trip_delay_arr[bus_index] - - (sdr_period * rd_sample_dly[cs])) / (ddr_period); - phase1 = (total_round_trip_delay_arr[bus_index + 1] - - (sdr_period * rd_sample_dly[cs])) / (ddr_period); - max_phase = (phase0 > phase1) ? phase0 : phase1; - DEBUG_TRAINING_STATIC_IP( - DEBUG_LEVEL_TRACE, - ("\tphase0 0x%x phase1 0x%x max_phase 0x%x\n", - phase0, phase1, max_phase)); - - /* ADLL calculation */ - adll0 = (u32)((total_round_trip_delay_arr[bus_index] - - (sdr_period * rd_sample_dly[cs]) - - (ddr_period * phase0)) / adll_period); - adll0 = (adll0 > 31) ? 31 : adll0; - adll1 = (u32)((total_round_trip_delay_arr[bus_index + 1] - - (sdr_period * rd_sample_dly[cs]) - - (ddr_period * phase1)) / adll_period); - adll1 = (adll1 > 31) ? 31 : adll1; - - /* The Read delay close the Read FIFO */ - rd_ready_del[cs] = rd_sample_dly[cs] + - read_ready_delay_phase_offset[max_phase]; - DEBUG_TRAINING_STATIC_IP( - DEBUG_LEVEL_TRACE, - ("\tadll0 0x%x adll1 0x%x rd_ready_del[cs] 0x%x\n", - adll0, adll1, rd_ready_del[cs])); - - /* - * Write to the phy of Interface (bit 0 \96 4 \96 ADLL, - * bit 6-8 phase) - */ - data0 = ((phase0 << 6) + (adll0 & 0x1f)); - data1 = ((phase1 << 6) + (adll1 & 0x1f)); - - CHECK_STATUS(ddr3_tip_bus_read_modify_write - (dev_num, ACCESS_TYPE_UNICAST, if_id, - (bus_index % 4), DDR_PHY_DATA, PHY_READ_DELAY(cs), - data0, 0x1df)); - CHECK_STATUS(ddr3_tip_bus_read_modify_write - (dev_num, ACCESS_TYPE_UNICAST, if_id, - ((bus_index + 1) % 4), DDR_PHY_DATA, - PHY_READ_DELAY(cs), data1, 0x1df)); - } - - for (bus_index = 0; bus_index < bus_per_interface; bus_index++) { - VALIDATE_ACTIVE(tm->bus_act_mask, bus_index); - CHECK_STATUS(ddr3_tip_bus_read_modify_write - (dev_num, ACCESS_TYPE_UNICAST, if_id, - bus_index, DDR_PHY_DATA, 0x3, data3, 0x1f)); - } - CHECK_STATUS(ddr3_tip_if_write - (dev_num, ACCESS_TYPE_UNICAST, if_id, - READ_DATA_SAMPLE_DELAY, - (rd_sample_dly[0] + cl_value) + (rd_sample_dly[1] << 8), - MASK_ALL_BITS)); - - /* Read_ready_del0 bit 0-4 , CS bits 8-12 */ - CHECK_STATUS(ddr3_tip_if_write - (dev_num, ACCESS_TYPE_UNICAST, if_id, - READ_DATA_READY_DELAY, - rd_ready_del[0] + (rd_ready_del[1] << 8) + cl_value, - MASK_ALL_BITS)); - - return MV_OK; -} - -/* - * DDR3 Static flow - */ -int ddr3_tip_run_static_alg(u32 dev_num, enum hws_ddr_freq freq) -{ - u32 if_id = 0; - struct trip_delay_element *table_ptr; - u32 wl_total_round_trip_delay_arr[MAX_TOTAL_BUS_NUM]; - u32 rl_total_round_trip_delay_arr[MAX_TOTAL_BUS_NUM]; - struct init_cntr_param init_cntr_prm; - int ret; - struct hws_topology_map *tm = ddr3_get_topology_map(); - - DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE, - ("ddr3_tip_run_static_alg")); - - init_cntr_prm.do_mrs_phy = 1; - init_cntr_prm.is_ctrl64_bit = 0; - init_cntr_prm.init_phy = 1; - ret = hws_ddr3_tip_init_controller(dev_num, &init_cntr_prm); - if (ret != MV_OK) { - DEBUG_TRAINING_STATIC_IP( - DEBUG_LEVEL_ERROR, - ("hws_ddr3_tip_init_controller failure\n")); - } - - /* calculate the round trip delay for Write Leveling */ - table_ptr = static_config[dev_num].board_trace_arr; - CHECK_STATUS(ddr3_tip_static_round_trip_arr_build - (dev_num, table_ptr, 1, - wl_total_round_trip_delay_arr)); - /* calculate the round trip delay for Read Leveling */ - CHECK_STATUS(ddr3_tip_static_round_trip_arr_build - (dev_num, table_ptr, 0, - rl_total_round_trip_delay_arr)); - - for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { - /* check if the interface is enabled */ - VALIDATE_ACTIVE(tm->if_act_mask, if_id); - /* - * Static frequency is defined according to init-frequency - * (not target) - */ - DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE, - ("Static IF %d freq %d\n", - if_id, freq)); - CHECK_STATUS(ddr3_tip_write_leveling_static_config - (dev_num, if_id, freq, - wl_total_round_trip_delay_arr)); - CHECK_STATUS(ddr3_tip_read_leveling_static_config - (dev_num, if_id, freq, - rl_total_round_trip_delay_arr)); - } - - return MV_OK; -} - -/* - * Init controller for static flow - */ -int ddr3_tip_static_init_controller(u32 dev_num) -{ - u32 index_cnt = 0; - - DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE, - ("ddr3_tip_static_init_controller\n")); - while (static_init_controller_config[dev_num][index_cnt].reg_addr != - 0) { - CHECK_STATUS(ddr3_tip_if_write - (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, - static_init_controller_config[dev_num][index_cnt]. - reg_addr, - static_init_controller_config[dev_num][index_cnt]. - reg_data, - static_init_controller_config[dev_num][index_cnt]. - reg_mask)); - - DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE, - ("Init_controller index_cnt %d\n", - index_cnt)); - index_cnt++; - } - - return MV_OK; -} - -int ddr3_tip_static_phy_init_controller(u32 dev_num) -{ - DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE, - ("Phy Init Controller 2\n")); - CHECK_STATUS(ddr3_tip_bus_write - (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, - ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA, 0xa4, - 0x3dfe)); - - DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE, - ("Phy Init Controller 3\n")); - CHECK_STATUS(ddr3_tip_bus_write - (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, - ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA, 0xa6, - 0xcb2)); - - DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE, - ("Phy Init Controller 4\n")); - CHECK_STATUS(ddr3_tip_bus_write - (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, - ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA, 0xa9, - 0)); - - DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE, - ("Static Receiver Calibration\n")); - CHECK_STATUS(ddr3_tip_bus_write - (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, - ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA, 0xd0, - 0x1f)); - - DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE, - ("Static V-REF Calibration\n")); - CHECK_STATUS(ddr3_tip_bus_write - (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, - ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA, 0xa8, - 0x434)); - - return MV_OK; -} -#endif /* * Configure phy (called by static init controller) for static flow |