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-rw-r--r--drivers/i2c/Makefile9
-rw-r--r--drivers/i2c/designware_i2c.c15
-rw-r--r--drivers/i2c/mxs_i2c.c15
-rw-r--r--drivers/i2c/omap1510_i2c.c277
-rw-r--r--drivers/i2c/omap24xx_i2c.c172
-rw-r--r--drivers/i2c/sh_i2c.c294
-rw-r--r--drivers/i2c/zynq_i2c.c29
7 files changed, 283 insertions, 528 deletions
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 5280bb3fe3..553b519cca 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -11,21 +11,20 @@ obj-$(CONFIG_DW_I2C) += designware_i2c.o
obj-$(CONFIG_I2C_MVTWSI) += mvtwsi.o
obj-$(CONFIG_I2C_MV) += mv_i2c.o
obj-$(CONFIG_I2C_MXS) += mxs_i2c.o
-obj-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o
-obj-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o
-obj-$(CONFIG_DRIVER_OMAP34XX_I2C) += omap24xx_i2c.o
obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
obj-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o
obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
obj-$(CONFIG_U8500_I2C) += u8500_i2c.o
-obj-$(CONFIG_SH_I2C) += sh_i2c.o
obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
obj-$(CONFIG_SYS_I2C) += i2c_core.o
obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
+obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
+obj-$(CONFIG_SYS_I2C_OMAP34XX) += omap24xx_i2c.o
obj-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o
obj-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o
+obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
-obj-$(CONFIG_ZYNQ_I2C) += zynq_i2c.o
+obj-$(CONFIG_SYS_I2C_ZYNQ) += zynq_i2c.o
diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index c2f06627d3..cb2ac04b60 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -151,7 +151,19 @@ void i2c_init(int speed, int slaveadd)
*/
static void i2c_setaddress(unsigned int i2c_addr)
{
+ unsigned int enbl;
+
+ /* Disable i2c */
+ enbl = readl(&i2c_regs_p->ic_enable);
+ enbl &= ~IC_ENABLE_0B;
+ writel(enbl, &i2c_regs_p->ic_enable);
+
writel(i2c_addr, &i2c_regs_p->ic_tar);
+
+ /* Enable i2c */
+ enbl = readl(&i2c_regs_p->ic_enable);
+ enbl |= IC_ENABLE_0B;
+ writel(enbl, &i2c_regs_p->ic_enable);
}
/*
@@ -237,9 +249,6 @@ static int i2c_xfer_finish(void)
i2c_flush_rxfifo();
- /* Wait for read/write operation to complete on actual memory */
- udelay(10000);
-
return 0;
}
diff --git a/drivers/i2c/mxs_i2c.c b/drivers/i2c/mxs_i2c.c
index 46106b7712..a298c95e14 100644
--- a/drivers/i2c/mxs_i2c.c
+++ b/drivers/i2c/mxs_i2c.c
@@ -150,6 +150,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
{
struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
uint32_t tmp = 0;
+ int timeout = MXS_I2C_MAX_TIMEOUT;
int ret;
int i;
@@ -169,9 +170,17 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
for (i = 0; i < len; i++) {
if (!(i & 3)) {
- while (readl(&i2c_regs->hw_i2c_queuestat) &
- I2C_QUEUESTAT_RD_QUEUE_EMPTY)
- ;
+ while (--timeout) {
+ tmp = readl(&i2c_regs->hw_i2c_queuestat);
+ if (!(tmp & I2C_QUEUESTAT_RD_QUEUE_EMPTY))
+ break;
+ }
+
+ if (!timeout) {
+ debug("MXS I2C: Failed receiving data!\n");
+ return -ETIMEDOUT;
+ }
+
tmp = readl(&i2c_regs->hw_i2c_queuedata);
}
buffer[i] = tmp & 0xff;
diff --git a/drivers/i2c/omap1510_i2c.c b/drivers/i2c/omap1510_i2c.c
deleted file mode 100644
index f91ee8884a..0000000000
--- a/drivers/i2c/omap1510_i2c.c
+++ /dev/null
@@ -1,277 +0,0 @@
-/*
- * Basic I2C functions
- *
- * Copyright (c) 2003 Texas Instruments
- *
- * This package is free software; you can redistribute it and/or
- * modify it under the terms of the license found in the file
- * named COPYING that should have accompanied this file.
- *
- * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- *
- * Author: Jian Zhang jzhang@ti.com, Texas Instruments
- *
- * Copyright (c) 2003 Wolfgang Denk, wd@denx.de
- * Rewritten to fit into the current U-Boot framework
- *
- */
-
-#include <common.h>
-
-static void wait_for_bb (void);
-static u16 wait_for_pin (void);
-
-void i2c_init (int speed, int slaveadd)
-{
- u16 scl;
-
- if (inw (I2C_CON) & I2C_CON_EN) {
- outw (0, I2C_CON);
- udelay (5000);
- }
-
- /* 12MHz I2C module clock */
- outw (0, I2C_PSC);
- outw (I2C_CON_EN, I2C_CON);
- outw (0, I2C_SYSTEST);
- /* have to enable intrrupts or OMAP i2c module doesn't work */
- outw (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
- I2C_IE_NACK_IE | I2C_IE_AL_IE, I2C_IE);
- scl = (12000000 / 2) / speed - 6;
- outw (scl, I2C_SCLL);
- outw (scl, I2C_SCLH);
- /* own address */
- outw (slaveadd, I2C_OA);
- outw (0, I2C_CNT);
- udelay (1000);
-}
-
-static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
-{
- int i2c_error = 0;
- u16 status;
-
- /* wait until bus not busy */
- wait_for_bb ();
-
- /* one byte only */
- outw (1, I2C_CNT);
- /* set slave address */
- outw (devaddr, I2C_SA);
- /* no stop bit needed here */
- outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON);
-
- status = wait_for_pin ();
-
- if (status & I2C_STAT_XRDY) {
- /* Important: have to use byte access */
- *(volatile u8 *) (I2C_DATA) = regoffset;
- udelay (20000);
- if (inw (I2C_STAT) & I2C_STAT_NACK) {
- i2c_error = 1;
- }
- } else {
- i2c_error = 1;
- }
-
- if (!i2c_error) {
- /* free bus, otherwise we can't use a combined transction */
- outw (0, I2C_CON);
- while (inw (I2C_STAT) || (inw (I2C_CON) & I2C_CON_MST)) {
- udelay (10000);
- /* Have to clear pending interrupt to clear I2C_STAT */
- inw (I2C_IV);
- }
-
- wait_for_bb ();
- /* set slave address */
- outw (devaddr, I2C_SA);
- /* read one byte from slave */
- outw (1, I2C_CNT);
- /* need stop bit here */
- outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP,
- I2C_CON);
-
- status = wait_for_pin ();
- if (status & I2C_STAT_RRDY) {
- *value = inw (I2C_DATA);
- udelay (20000);
- } else {
- i2c_error = 1;
- }
-
- if (!i2c_error) {
- outw (I2C_CON_EN, I2C_CON);
- while (inw (I2C_STAT)
- || (inw (I2C_CON) & I2C_CON_MST)) {
- udelay (10000);
- inw (I2C_IV);
- }
- }
- }
-
- return i2c_error;
-}
-
-static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value)
-{
- int i2c_error = 0;
- u16 status;
-
- /* wait until bus not busy */
- wait_for_bb ();
-
- /* two bytes */
- outw (2, I2C_CNT);
- /* set slave address */
- outw (devaddr, I2C_SA);
- /* stop bit needed here */
- outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
- I2C_CON_STP, I2C_CON);
-
- /* wait until state change */
- status = wait_for_pin ();
-
- if (status & I2C_STAT_XRDY) {
- /* send out two bytes */
- outw ((value << 8) + regoffset, I2C_DATA);
- /* must have enough delay to allow BB bit to go low */
- udelay (30000);
- if (inw (I2C_STAT) & I2C_STAT_NACK) {
- i2c_error = 1;
- }
- } else {
- i2c_error = 1;
- }
-
- if (!i2c_error) {
- outw (I2C_CON_EN, I2C_CON);
- while (inw (I2C_STAT) || (inw (I2C_CON) & I2C_CON_MST)) {
- udelay (1000);
- /* have to read to clear intrrupt */
- inw (I2C_IV);
- }
- }
-
- return i2c_error;
-}
-
-int i2c_probe (uchar chip)
-{
- int res = 1;
-
- if (chip == inw (I2C_OA)) {
- return res;
- }
-
- /* wait until bus not busy */
- wait_for_bb ();
-
- /* try to read one byte */
- outw (1, I2C_CNT);
- /* set slave address */
- outw (chip, I2C_SA);
- /* stop bit needed here */
- outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON);
- /* enough delay for the NACK bit set */
- udelay (2000);
- if (!(inw (I2C_STAT) & I2C_STAT_NACK)) {
- res = 0;
- } else {
- outw (inw (I2C_CON) | I2C_CON_STP, I2C_CON);
- udelay (20);
- wait_for_bb ();
- }
-
- return res;
-}
-
-int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
-{
- int i;
-
- if (alen > 1) {
- printf ("I2C read: addr len %d not supported\n", alen);
- return 1;
- }
-
- if (addr + len > 256) {
- printf ("I2C read: address out of range\n");
- return 1;
- }
-
- for (i = 0; i < len; i++) {
- if (i2c_read_byte (chip, addr + i, &buffer[i])) {
- printf ("I2C read: I/O error\n");
- i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
- return 1;
- }
- }
-
- return 0;
-}
-
-int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
-{
- int i;
-
- if (alen > 1) {
- printf ("I2C read: addr len %d not supported\n", alen);
- return 1;
- }
-
- if (addr + len > 256) {
- printf ("I2C read: address out of range\n");
- return 1;
- }
-
- for (i = 0; i < len; i++) {
- if (i2c_write_byte (chip, addr + i, buffer[i])) {
- printf ("I2C read: I/O error\n");
- i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
- return 1;
- }
- }
-
- return 0;
-}
-
-static void wait_for_bb (void)
-{
- int timeout = 10;
-
- while ((inw (I2C_STAT) & I2C_STAT_BB) && timeout--) {
- inw (I2C_IV);
- udelay (1000);
- }
-
- if (timeout <= 0) {
- printf ("timed out in wait_for_bb: I2C_STAT=%x\n",
- inw (I2C_STAT));
- }
-}
-
-static u16 wait_for_pin (void)
-{
- u16 status, iv;
- int timeout = 10;
-
- do {
- udelay (1000);
- status = inw (I2C_STAT);
- iv = inw (I2C_IV);
- } while (!iv &&
- !(status &
- (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
- I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
- I2C_STAT_AL)) && timeout--);
-
- if (timeout <= 0) {
- printf ("timed out in wait_for_pin: I2C_STAT=%x\n",
- inw (I2C_STAT));
- }
-
- return status;
-}
diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index ef38d71725..3d38c035b6 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -35,6 +35,7 @@
*/
#include <common.h>
+#include <i2c.h>
#include <asm/arch/i2c.h>
#include <asm/io.h>
@@ -48,22 +49,14 @@ DECLARE_GLOBAL_DATA_PTR;
/* Absolutely safe for status update at 100 kHz I2C: */
#define I2C_WAIT 200
-static int wait_for_bb(void);
-static u16 wait_for_event(void);
-static void flush_fifo(void);
+static int wait_for_bb(struct i2c_adapter *adap);
+static struct i2c *omap24_get_base(struct i2c_adapter *adap);
+static u16 wait_for_event(struct i2c_adapter *adap);
+static void flush_fifo(struct i2c_adapter *adap);
-/*
- * For SPL boot some boards need i2c before SDRAM is initialised so force
- * variables to live in SRAM
- */
-static struct i2c __attribute__((section (".data"))) *i2c_base =
- (struct i2c *)I2C_DEFAULT_BASE;
-static unsigned int __attribute__((section (".data"))) bus_initialized[I2C_BUS_MAX] =
- { [0 ... (I2C_BUS_MAX-1)] = 0 };
-static unsigned int __attribute__((section (".data"))) current_bus = 0;
-
-void i2c_init(int speed, int slaveadd)
+static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
{
+ struct i2c *i2c_base = omap24_get_base(adap);
int psc, fsscll, fssclh;
int hsscll = 0, hssclh = 0;
u32 scll, sclh;
@@ -163,16 +156,15 @@ void i2c_init(int speed, int slaveadd)
I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
#endif
udelay(1000);
- flush_fifo();
+ flush_fifo(adap);
writew(0xFFFF, &i2c_base->stat);
writew(0, &i2c_base->cnt);
-
- if (gd->flags & GD_FLG_RELOC)
- bus_initialized[current_bus] = 1;
}
-static void flush_fifo(void)
-{ u16 stat;
+static void flush_fifo(struct i2c_adapter *adap)
+{
+ struct i2c *i2c_base = omap24_get_base(adap);
+ u16 stat;
/* note: if you try and read data when its not there or ready
* you get a bus error
@@ -192,8 +184,9 @@ static void flush_fifo(void)
* i2c_probe: Use write access. Allows to identify addresses that are
* write-only (like the config register of dual-port EEPROMs)
*/
-int i2c_probe(uchar chip)
+static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
{
+ struct i2c *i2c_base = omap24_get_base(adap);
u16 status;
int res = 1; /* default = fail */
@@ -201,7 +194,7 @@ int i2c_probe(uchar chip)
return res;
/* Wait until bus is free */
- if (wait_for_bb())
+ if (wait_for_bb(adap))
return res;
/* No data transfer, slave addr only */
@@ -212,7 +205,7 @@ int i2c_probe(uchar chip)
writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
I2C_CON_STP, &i2c_base->con);
- status = wait_for_event();
+ status = wait_for_event(adap);
if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) {
/*
@@ -223,7 +216,7 @@ int i2c_probe(uchar chip)
*/
if (status == I2C_STAT_XRDY)
printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n",
- current_bus, status);
+ adap->hwadapnr, status);
goto pr_exit;
}
@@ -239,7 +232,7 @@ int i2c_probe(uchar chip)
I2C_CON_STP, &i2c_base->con); /* STP */
}
pr_exit:
- flush_fifo();
+ flush_fifo(adap);
writew(0xFFFF, &i2c_base->stat);
writew(0, &i2c_base->cnt);
return res;
@@ -258,8 +251,10 @@ pr_exit:
* or that do not need a register address at all (such as some clock
* distributors).
*/
-int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
+static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
+ int alen, uchar *buffer, int len)
{
+ struct i2c *i2c_base = omap24_get_base(adap);
int i2c_error = 0;
u16 status;
@@ -287,7 +282,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
}
/* Wait until bus not busy */
- if (wait_for_bb())
+ if (wait_for_bb(adap))
return 1;
/* Zero, one or two bytes reg address (offset) */
@@ -308,12 +303,12 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
#endif
/* Send register offset */
while (1) {
- status = wait_for_event();
+ status = wait_for_event(adap);
/* Try to identify bus that is not padconf'd for I2C */
if (status == I2C_STAT_XRDY) {
i2c_error = 2;
printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n",
- current_bus, status);
+ adap->hwadapnr, status);
goto rd_exit;
}
if (status == 0 || status & I2C_STAT_NACK) {
@@ -348,7 +343,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
/* Receive data */
while (1) {
- status = wait_for_event();
+ status = wait_for_event(adap);
/*
* Try to identify bus that is not padconf'd for I2C. This
* state could be left over from previous transactions if
@@ -357,7 +352,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
if (status == I2C_STAT_XRDY) {
i2c_error = 2;
printf("i2c_read (data phase): pads on bus %d probably not configured (status=0x%x)\n",
- current_bus, status);
+ adap->hwadapnr, status);
goto rd_exit;
}
if (status == 0 || status & I2C_STAT_NACK) {
@@ -375,15 +370,17 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
}
rd_exit:
- flush_fifo();
+ flush_fifo(adap);
writew(0xFFFF, &i2c_base->stat);
writew(0, &i2c_base->cnt);
return i2c_error;
}
/* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */
-int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
+static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
+ int alen, uchar *buffer, int len)
{
+ struct i2c *i2c_base = omap24_get_base(adap);
int i;
u16 status;
int i2c_error = 0;
@@ -415,7 +412,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
}
/* Wait until bus not busy */
- if (wait_for_bb())
+ if (wait_for_bb(adap))
return 1;
/* Start address phase - will write regoffset + len bytes data */
@@ -428,12 +425,12 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
while (alen) {
/* Must write reg offset (one or two bytes) */
- status = wait_for_event();
+ status = wait_for_event(adap);
/* Try to identify bus that is not padconf'd for I2C */
if (status == I2C_STAT_XRDY) {
i2c_error = 2;
printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n",
- current_bus, status);
+ adap->hwadapnr, status);
goto wr_exit;
}
if (status == 0 || status & I2C_STAT_NACK) {
@@ -455,7 +452,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
}
/* Address phase is over, now write data */
for (i = 0; i < len; i++) {
- status = wait_for_event();
+ status = wait_for_event(adap);
if (status == 0 || status & I2C_STAT_NACK) {
i2c_error = 1;
printf("i2c_write: error waiting for data ACK (status=0x%x)\n",
@@ -474,7 +471,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
}
wr_exit:
- flush_fifo();
+ flush_fifo(adap);
writew(0xFFFF, &i2c_base->stat);
writew(0, &i2c_base->cnt);
return i2c_error;
@@ -484,8 +481,9 @@ wr_exit:
* Wait for the bus to be free by checking the Bus Busy (BB)
* bit to become clear
*/
-static int wait_for_bb(void)
+static int wait_for_bb(struct i2c_adapter *adap)
{
+ struct i2c *i2c_base = omap24_get_base(adap);
int timeout = I2C_TIMEOUT;
u16 stat;
@@ -514,8 +512,9 @@ static int wait_for_bb(void)
* Wait for the I2C controller to complete current action
* and update status
*/
-static u16 wait_for_event(void)
+static u16 wait_for_event(struct i2c_adapter *adap)
{
+ struct i2c *i2c_base = omap24_get_base(adap);
u16 status;
int timeout = I2C_TIMEOUT;
@@ -540,7 +539,7 @@ static u16 wait_for_event(void)
* not been configured for I2C, and/or pull-ups are missing.
*/
printf("Check if pads/pull-ups of bus %d are properly configured\n",
- current_bus);
+ adap->hwadapnr);
writew(0xFFFF, &i2c_base->stat);
status = 0;
}
@@ -548,48 +547,93 @@ static u16 wait_for_event(void)
return status;
}
-int i2c_set_bus_num(unsigned int bus)
+static struct i2c *omap24_get_base(struct i2c_adapter *adap)
{
- if (bus >= I2C_BUS_MAX) {
- printf("Bad bus: %x\n", bus);
- return -1;
- }
-
- switch (bus) {
- default:
- bus = 0; /* Fall through */
+ switch (adap->hwadapnr) {
case 0:
- i2c_base = (struct i2c *)I2C_BASE1;
+ return (struct i2c *)I2C_BASE1;
break;
case 1:
- i2c_base = (struct i2c *)I2C_BASE2;
+ return (struct i2c *)I2C_BASE2;
break;
#if (I2C_BUS_MAX > 2)
case 2:
- i2c_base = (struct i2c *)I2C_BASE3;
+ return (struct i2c *)I2C_BASE3;
break;
#if (I2C_BUS_MAX > 3)
case 3:
- i2c_base = (struct i2c *)I2C_BASE4;
+ return (struct i2c *)I2C_BASE4;
break;
#if (I2C_BUS_MAX > 4)
case 4:
- i2c_base = (struct i2c *)I2C_BASE5;
+ return (struct i2c *)I2C_BASE5;
break;
#endif
#endif
#endif
+ default:
+ printf("wrong hwadapnr: %d\n", adap->hwadapnr);
+ break;
}
+ return NULL;
+}
- current_bus = bus;
+#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1)
+#define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED
+#endif
+#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1)
+#define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE
+#endif
- if (!bus_initialized[current_bus])
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe,
+ omap24_i2c_read, omap24_i2c_write, NULL,
+ CONFIG_SYS_OMAP24_I2C_SPEED,
+ CONFIG_SYS_OMAP24_I2C_SLAVE,
+ 0)
+U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe,
+ omap24_i2c_read, omap24_i2c_write, NULL,
+ CONFIG_SYS_OMAP24_I2C_SPEED1,
+ CONFIG_SYS_OMAP24_I2C_SLAVE1,
+ 1)
+#if (I2C_BUS_MAX > 2)
+#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2)
+#define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED
+#endif
+#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2)
+#define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE
+#endif
- return 0;
-}
+U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe,
+ omap24_i2c_read, omap24_i2c_write, NULL,
+ CONFIG_SYS_OMAP24_I2C_SPEED2,
+ CONFIG_SYS_OMAP24_I2C_SLAVE2,
+ 2)
+#if (I2C_BUS_MAX > 3)
+#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3)
+#define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED
+#endif
+#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3)
+#define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE
+#endif
-int i2c_get_bus_num(void)
-{
- return (int) current_bus;
-}
+U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe,
+ omap24_i2c_read, omap24_i2c_write, NULL,
+ CONFIG_SYS_OMAP24_I2C_SPEED3,
+ CONFIG_SYS_OMAP24_I2C_SLAVE3,
+ 3)
+#if (I2C_BUS_MAX > 4)
+#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4)
+#define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED
+#endif
+#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4)
+#define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE
+#endif
+
+U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe,
+ omap24_i2c_read, omap24_i2c_write, NULL,
+ CONFIG_SYS_OMAP24_I2C_SPEED4,
+ CONFIG_SYS_OMAP24_I2C_SLAVE4,
+ 4)
+#endif
+#endif
+#endif
diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c
index 808202c299..cc19100750 100644
--- a/drivers/i2c/sh_i2c.c
+++ b/drivers/i2c/sh_i2c.c
@@ -6,6 +6,7 @@
*/
#include <common.h>
+#include <i2c.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -22,8 +23,6 @@ struct sh_i2c {
};
#undef ureg
-static struct sh_i2c *base;
-
/* ICCR */
#define SH_I2C_ICCR_ICE (1 << 7)
#define SH_I2C_ICCR_RACK (1 << 6)
@@ -43,202 +42,165 @@ static struct sh_i2c *base;
#define SH_I2C_ICIC_ICCHB8 (1 << 6)
#endif
+static const struct sh_i2c *i2c_dev[CONFIG_SYS_I2C_SH_NUM_CONTROLLERS] = {
+ (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE0,
+#ifdef CONFIG_SYS_I2C_SH_BASE1
+ (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE1,
+#endif
+#ifdef CONFIG_SYS_I2C_SH_BASE2
+ (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE2,
+#endif
+#ifdef CONFIG_SYS_I2C_SH_BASE3
+ (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE3,
+#endif
+#ifdef CONFIG_SYS_I2C_SH_BASE4
+ (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE4,
+#endif
+};
+
static u16 iccl, icch;
#define IRQ_WAIT 1000
-static void irq_dte(struct sh_i2c *base)
+static void sh_irq_dte(struct sh_i2c *dev)
{
int i;
- for (i = 0 ; i < IRQ_WAIT ; i++) {
- if (SH_IC_DTE & readb(&base->icsr))
+ for (i = 0; i < IRQ_WAIT; i++) {
+ if (SH_IC_DTE & readb(&dev->icsr))
break;
udelay(10);
}
}
-static int irq_dte_with_tack(struct sh_i2c *base)
+static int sh_irq_dte_with_tack(struct sh_i2c *dev)
{
int i;
- for (i = 0 ; i < IRQ_WAIT ; i++) {
- if (SH_IC_DTE & readb(&base->icsr))
+ for (i = 0; i < IRQ_WAIT; i++) {
+ if (SH_IC_DTE & readb(&dev->icsr))
break;
- if (SH_IC_TACK & readb(&base->icsr))
+ if (SH_IC_TACK & readb(&dev->icsr))
return -1;
udelay(10);
}
return 0;
}
-static void irq_busy(struct sh_i2c *base)
+static void sh_irq_busy(struct sh_i2c *dev)
{
int i;
- for (i = 0 ; i < IRQ_WAIT ; i++) {
- if (!(SH_IC_BUSY & readb(&base->icsr)))
+ for (i = 0; i < IRQ_WAIT; i++) {
+ if (!(SH_IC_BUSY & readb(&dev->icsr)))
break;
udelay(10);
}
}
-static int i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop)
+static int sh_i2c_set_addr(struct sh_i2c *dev, u8 chip, u8 addr, int stop)
{
u8 icic = SH_IC_TACK;
- clrbits_8(&base->iccr, SH_I2C_ICCR_ICE);
- setbits_8(&base->iccr, SH_I2C_ICCR_ICE);
+ debug("%s: chip: %x, addr: %x iccl: %x, icch %x\n",
+ __func__, chip, addr, iccl, icch);
+ clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
+ setbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
- writeb(iccl & 0xff, &base->iccl);
- writeb(icch & 0xff, &base->icch);
+ writeb(iccl & 0xff, &dev->iccl);
+ writeb(icch & 0xff, &dev->icch);
#ifdef CONFIG_SH_I2C_8BIT
if (iccl > 0xff)
icic |= SH_I2C_ICIC_ICCLB8;
if (icch > 0xff)
icic |= SH_I2C_ICIC_ICCHB8;
#endif
- writeb(icic, &base->icic);
+ writeb(icic, &dev->icic);
- writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr);
- irq_dte(base);
+ writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr);
+ sh_irq_dte(dev);
- clrbits_8(&base->icsr, SH_IC_TACK);
- writeb(id << 1, &base->icdr);
- if (irq_dte_with_tack(base) != 0)
+ clrbits_8(&dev->icsr, SH_IC_TACK);
+ writeb(chip << 1, &dev->icdr);
+ if (sh_irq_dte_with_tack(dev) != 0)
return -1;
- writeb(reg, &base->icdr);
+ writeb(addr, &dev->icdr);
if (stop)
- writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &base->iccr);
+ writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &dev->iccr);
- if (irq_dte_with_tack(base) != 0)
+ if (sh_irq_dte_with_tack(dev) != 0)
return -1;
return 0;
}
-static void i2c_finish(struct sh_i2c *base)
+static void sh_i2c_finish(struct sh_i2c *dev)
{
- writeb(0, &base->icsr);
- clrbits_8(&base->iccr, SH_I2C_ICCR_ICE);
+ writeb(0, &dev->icsr);
+ clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
}
-static int i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 val)
+static int
+sh_i2c_raw_write(struct sh_i2c *dev, u8 chip, uint addr, u8 val)
{
int ret = -1;
- if (i2c_set_addr(base, id, reg, 0) != 0)
+ if (sh_i2c_set_addr(dev, chip, addr, 0) != 0)
goto exit0;
udelay(10);
- writeb(val, &base->icdr);
- if (irq_dte_with_tack(base) != 0)
+ writeb(val, &dev->icdr);
+ if (sh_irq_dte_with_tack(dev) != 0)
goto exit0;
- writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &base->iccr);
- if (irq_dte_with_tack(base) != 0)
+ writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &dev->iccr);
+ if (sh_irq_dte_with_tack(dev) != 0)
goto exit0;
- irq_busy(base);
+ sh_irq_busy(dev);
ret = 0;
+
exit0:
- i2c_finish(base);
+ sh_i2c_finish(dev);
return ret;
}
-static int i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg)
+static int sh_i2c_raw_read(struct sh_i2c *dev, u8 chip, u8 addr)
{
int ret = -1;
#if defined(CONFIG_SH73A0)
- if (i2c_set_addr(base, id, reg, 0) != 0)
+ if (sh_i2c_set_addr(dev, chip, addr, 0) != 0)
goto exit0;
#else
- if (i2c_set_addr(base, id, reg, 1) != 0)
+ if (sh_i2c_set_addr(dev, chip, addr, 1) != 0)
goto exit0;
udelay(100);
#endif
- writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr);
- irq_dte(base);
+ writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr);
+ sh_irq_dte(dev);
- writeb(id << 1 | 0x01, &base->icdr);
- if (irq_dte_with_tack(base) != 0)
+ writeb(chip << 1 | 0x01, &dev->icdr);
+ if (sh_irq_dte_with_tack(dev) != 0)
goto exit0;
- writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &base->iccr);
- if (irq_dte_with_tack(base) != 0)
+ writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &dev->iccr);
+ if (sh_irq_dte_with_tack(dev) != 0)
goto exit0;
- ret = readb(&base->icdr) & 0xff;
+ ret = readb(&dev->icdr) & 0xff;
+
+ writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &dev->iccr);
+ readb(&dev->icdr); /* Dummy read */
+ sh_irq_busy(dev);
- writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &base->iccr);
- readb(&base->icdr); /* Dummy read */
- irq_busy(base);
exit0:
- i2c_finish(base);
+ sh_i2c_finish(dev);
return ret;
}
-#ifdef CONFIG_I2C_MULTI_BUS
-static unsigned int current_bus;
-
-/**
- * i2c_set_bus_num - change active I2C bus
- * @bus: bus index, zero based
- * @returns: 0 on success, non-0 on failure
- */
-int i2c_set_bus_num(unsigned int bus)
-{
- if ((bus < 0) || (bus >= CONFIG_SYS_MAX_I2C_BUS)) {
- printf("Bad bus: %d\n", bus);
- return -1;
- }
-
- switch (bus) {
- case 0:
- base = (void *)CONFIG_SH_I2C_BASE0;
- break;
- case 1:
- base = (void *)CONFIG_SH_I2C_BASE1;
- break;
-#ifdef CONFIG_SH_I2C_BASE2
- case 2:
- base = (void *)CONFIG_SH_I2C_BASE2;
- break;
-#endif
-#ifdef CONFIG_SH_I2C_BASE3
- case 3:
- base = (void *)CONFIG_SH_I2C_BASE3;
- break;
-#endif
-#ifdef CONFIG_SH_I2C_BASE4
- case 4:
- base = (void *)CONFIG_SH_I2C_BASE4;
- break;
-#endif
- default:
- return -1;
- }
- current_bus = bus;
-
- return 0;
-}
-
-/**
- * i2c_get_bus_num - returns index of active I2C bus
- */
-unsigned int i2c_get_bus_num(void)
-{
- return current_bus;
-}
-#endif
-
-#define SH_I2C_ICCL_CALC(clk, date, t_low, t_high) \
- ((clk / rate) * (t_low / t_low + t_high))
-#define SH_I2C_ICCH_CALC(clk, date, t_low, t_high) \
- ((clk / rate) * (t_high / t_low + t_high))
-
-void i2c_init(int speed, int slaveaddr)
+static void
+sh_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
{
int num, denom, tmp;
@@ -246,11 +208,6 @@ void i2c_init(int speed, int slaveaddr)
if (!(gd->flags & GD_FLG_RELOC))
return;
-#ifdef CONFIG_I2C_MULTI_BUS
- current_bus = 0;
-#endif
- base = (struct sh_i2c *)CONFIG_SH_I2C_BASE0;
-
/*
* Calculate the value for iccl. From the data sheet:
* iccl = (p-clock / transfer-rate) * (L / (L + H))
@@ -272,67 +229,78 @@ void i2c_init(int speed, int slaveaddr)
icch = (u16)((num/denom) + 1);
else
icch = (u16)(num/denom);
+
+ debug("clock: %d, speed %d, iccl: %x, icch: %x\n",
+ CONFIG_SH_I2C_CLOCK, speed, iccl, icch);
}
-/*
- * i2c_read: - Read multiple bytes from an i2c device
- *
- * The higher level routines take into account that this function is only
- * called with len < page length of the device (see configuration file)
- *
- * @chip: address of the chip which is to be read
- * @addr: i2c data address within the chip
- * @alen: length of the i2c data address (1..2 bytes)
- * @buffer: where to write the data
- * @len: how much byte do we want to read
- * @return: 0 in case of success
- */
-int i2c_read(u8 chip, u32 addr, int alen, u8 *buffer, int len)
+static int sh_i2c_read(struct i2c_adapter *adap, uint8_t chip,
+ uint addr, int alen, u8 *data, int len)
{
- int ret;
- int i = 0;
- for (i = 0 ; i < len ; i++) {
- ret = i2c_raw_read(base, chip, addr + i);
+ int ret, i;
+ struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
+
+ for (i = 0; i < len; i++) {
+ ret = sh_i2c_raw_read(dev, chip, addr + i);
if (ret < 0)
return -1;
- buffer[i] = ret & 0xff;
+
+ data[i] = ret & 0xff;
+ debug("%s: data[%d]: %02x\n", __func__, i, data[i]);
}
+
return 0;
}
-/*
- * i2c_write: - Write multiple bytes to an i2c device
- *
- * The higher level routines take into account that this function is only
- * called with len < page length of the device (see configuration file)
- *
- * @chip: address of the chip which is to be written
- * @addr: i2c data address within the chip
- * @alen: length of the i2c data address (1..2 bytes)
- * @buffer: where to find the data to be written
- * @len: how much byte do we want to read
- * @return: 0 in case of success
- */
-int i2c_write(u8 chip, u32 addr, int alen, u8 *buffer, int len)
+static int sh_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr,
+ int alen, u8 *data, int len)
{
- int i = 0;
- for (i = 0; i < len ; i++)
- if (i2c_raw_write(base, chip, addr + i, buffer[i]) != 0)
+ struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
+ int i;
+
+ for (i = 0; i < len; i++) {
+ debug("%s: data[%d]: %02x\n", __func__, i, data[i]);
+ if (sh_i2c_raw_write(dev, chip, addr + i, data[i]) != 0)
return -1;
+ }
return 0;
}
-/*
- * i2c_probe: - Test if a chip answers for a given i2c address
- *
- * @chip: address of the chip which is searched for
- * @return: 0 if a chip was found, -1 otherwhise
- */
-int i2c_probe(u8 chip)
+static int
+sh_i2c_probe(struct i2c_adapter *adap, u8 dev)
{
- int ret;
+ return sh_i2c_read(adap, dev, 0, 0, NULL, 0);
+}
- ret = i2c_set_addr(base, chip, 0, 1);
- i2c_finish(base);
- return ret;
+static unsigned int sh_i2c_set_bus_speed(struct i2c_adapter *adap,
+ unsigned int speed)
+{
+ struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
+
+ sh_i2c_finish(dev);
+ sh_i2c_init(adap, speed, 0);
+
+ return 0;
}
+
+/*
+ * Register RCAR i2c adapters
+ */
+U_BOOT_I2C_ADAP_COMPLETE(sh_0, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
+ sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED0, 0, 0)
+#ifdef CONFIG_SYS_I2C_SH_BASE1
+U_BOOT_I2C_ADAP_COMPLETE(sh_1, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
+ sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED1, 0, 1)
+#endif
+#ifdef CONFIG_SYS_I2C_SH_BASE2
+U_BOOT_I2C_ADAP_COMPLETE(sh_2, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
+ sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED2, 0, 2)
+#endif
+#ifdef CONFIG_SYS_I2C_SH_BASE3
+U_BOOT_I2C_ADAP_COMPLETE(sh_3, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
+ sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED3, 0, 3)
+#endif
+#ifdef CONFIG_SYS_I2C_SH_BASE4
+U_BOOT_I2C_ADAP_COMPLETE(sh_4, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
+ sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED4, 0, 4)
+#endif
diff --git a/drivers/i2c/zynq_i2c.c b/drivers/i2c/zynq_i2c.c
index ce2d23f725..70a9aeafd5 100644
--- a/drivers/i2c/zynq_i2c.c
+++ b/drivers/i2c/zynq_i2c.c
@@ -74,7 +74,8 @@ static struct zynq_i2c_registers *zynq_i2c =
(struct zynq_i2c_registers *)ZYNQ_I2C_BASE;
/* I2C init called by cmd_i2c when doing 'i2c reset'. */
-void i2c_init(int requested_speed, int slaveadd)
+static void zynq_i2c_init(struct i2c_adapter *adap, int requested_speed,
+ int slaveadd)
{
/* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */
writel((16 << ZYNQ_I2C_CONTROL_DIV_B_SHIFT) |
@@ -151,7 +152,7 @@ static u32 zynq_i2c_wait(u32 mask)
* I2C probe called by cmd_i2c when doing 'i2c probe'.
* Begin read, nak data byte, end.
*/
-int i2c_probe(u8 dev)
+static int zynq_i2c_probe(struct i2c_adapter *adap, u8 dev)
{
/* Attempt to read a byte */
setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
@@ -170,7 +171,8 @@ int i2c_probe(u8 dev)
* I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
* Begin write, send address byte(s), begin read, receive data bytes, end.
*/
-int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
+static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
+ int alen, u8 *data, int length)
{
u32 status;
u32 i = 0;
@@ -235,7 +237,8 @@ int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
* I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
* Begin write, send address byte(s), send data bytes, end.
*/
-int i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
+static int zynq_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
+ int alen, u8 *data, int length)
{
u8 *cur_data = data;
@@ -275,16 +278,16 @@ int i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
return 0;
}
-int i2c_set_bus_num(unsigned int bus)
+static unsigned int zynq_i2c_set_bus_speed(struct i2c_adapter *adap,
+ unsigned int speed)
{
- /* Only support bus 0 */
- if (bus > 0)
- return -1;
- return 0;
-}
+ if (speed != 1000000)
+ return -EINVAL;
-unsigned int i2c_get_bus_num(void)
-{
- /* Only support bus 0 */
return 0;
}
+
+U_BOOT_I2C_ADAP_COMPLETE(zynq_0, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read,
+ zynq_i2c_write, zynq_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE,
+ 0)
generated by cgit (git 2.34.1) at 2024-12-24 16:12:27 +0000