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-rw-r--r--drivers/net/ag7xxx.c16
-rw-r--r--drivers/net/dwc_eth_qos.c17
-rw-r--r--drivers/net/ethoc.c8
-rw-r--r--drivers/net/pic32_eth.c12
-rw-r--r--drivers/net/pic32_mdio.c28
-rw-r--r--drivers/net/ravb.c4
-rw-r--r--drivers/net/xilinx_axi_emac.c4
-rw-r--r--drivers/net/zynq_gem.c12
8 files changed, 51 insertions, 50 deletions
diff --git a/drivers/net/ag7xxx.c b/drivers/net/ag7xxx.c
index 00e6806892..f28187058e 100644
--- a/drivers/net/ag7xxx.c
+++ b/drivers/net/ag7xxx.c
@@ -164,8 +164,8 @@ static int ag7xxx_switch_read(struct mii_dev *bus, int addr, int reg, u16 *val)
writel(AG7XXX_ETH_MII_MGMT_CMD_READ,
regs + AG7XXX_ETH_MII_MGMT_CMD);
- ret = wait_for_bit("ag7xxx", regs + AG7XXX_ETH_MII_MGMT_IND,
- AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
+ ret = wait_for_bit_le32(regs + AG7XXX_ETH_MII_MGMT_IND,
+ AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
if (ret)
return ret;
@@ -185,8 +185,8 @@ static int ag7xxx_switch_write(struct mii_dev *bus, int addr, int reg, u16 val)
regs + AG7XXX_ETH_MII_MGMT_ADDRESS);
writel(val, regs + AG7XXX_ETH_MII_MGMT_CTRL);
- ret = wait_for_bit("ag7xxx", regs + AG7XXX_ETH_MII_MGMT_IND,
- AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
+ ret = wait_for_bit_le32(regs + AG7XXX_ETH_MII_MGMT_IND,
+ AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
return ret;
}
@@ -510,13 +510,13 @@ static void ag7xxx_eth_stop(struct udevice *dev)
/* Stop the TX DMA. */
writel(0, priv->regs + AG7XXX_ETH_DMA_TX_CTRL);
- wait_for_bit("ag7xxx", priv->regs + AG7XXX_ETH_DMA_TX_CTRL, ~0, 0,
- 1000, 0);
+ wait_for_bit_le32(priv->regs + AG7XXX_ETH_DMA_TX_CTRL, ~0, 0,
+ 1000, 0);
/* Stop the RX DMA. */
writel(0, priv->regs + AG7XXX_ETH_DMA_RX_CTRL);
- wait_for_bit("ag7xxx", priv->regs + AG7XXX_ETH_DMA_RX_CTRL, ~0, 0,
- 1000, 0);
+ wait_for_bit_le32(priv->regs + AG7XXX_ETH_DMA_RX_CTRL, ~0, 0,
+ 1000, 0);
}
/*
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 00076cffbe..232e8034df 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -361,8 +361,9 @@ static void eqos_flush_buffer(void *buf, size_t size)
static int eqos_mdio_wait_idle(struct eqos_priv *eqos)
{
- return wait_for_bit(__func__, &eqos->mac_regs->mdio_address,
- EQOS_MAC_MDIO_ADDRESS_GB, false, 1000000, true);
+ return wait_for_bit_le32(&eqos->mac_regs->mdio_address,
+ EQOS_MAC_MDIO_ADDRESS_GB, false,
+ 1000000, true);
}
static int eqos_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad,
@@ -588,15 +589,15 @@ static int eqos_calibrate_pads_tegra186(struct udevice *dev)
setbits_le32(&eqos->tegra186_regs->auto_cal_config,
EQOS_AUTO_CAL_CONFIG_START | EQOS_AUTO_CAL_CONFIG_ENABLE);
- ret = wait_for_bit(__func__, &eqos->tegra186_regs->auto_cal_status,
- EQOS_AUTO_CAL_STATUS_ACTIVE, true, 10, false);
+ ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
+ EQOS_AUTO_CAL_STATUS_ACTIVE, true, 10, false);
if (ret) {
pr_err("calibrate didn't start");
goto failed;
}
- ret = wait_for_bit(__func__, &eqos->tegra186_regs->auto_cal_status,
- EQOS_AUTO_CAL_STATUS_ACTIVE, false, 10, false);
+ ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
+ EQOS_AUTO_CAL_STATUS_ACTIVE, false, 10, false);
if (ret) {
pr_err("calibrate didn't finish");
goto failed;
@@ -862,8 +863,8 @@ static int eqos_start(struct udevice *dev)
eqos->reg_access_ok = true;
- ret = wait_for_bit(__func__, &eqos->dma_regs->mode,
- EQOS_DMA_MODE_SWR, false, 10, false);
+ ret = wait_for_bit_le32(&eqos->dma_regs->mode,
+ EQOS_DMA_MODE_SWR, false, 10, false);
if (ret) {
pr_err("EQOS_DMA_MODE_SWR stuck");
goto err_stop_resets;
diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c
index a6df950081..51a6c97550 100644
--- a/drivers/net/ethoc.c
+++ b/drivers/net/ethoc.c
@@ -548,8 +548,8 @@ static int ethoc_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(addr, reg));
ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ);
- rc = wait_for_bit(__func__, ethoc_reg(priv, MIISTATUS),
- MIISTATUS_BUSY, false, CONFIG_SYS_HZ, false);
+ rc = wait_for_bit_le32(ethoc_reg(priv, MIISTATUS),
+ MIISTATUS_BUSY, false, CONFIG_SYS_HZ, false);
if (rc == 0) {
u32 data = ethoc_read(priv, MIIRX_DATA);
@@ -571,8 +571,8 @@ static int ethoc_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
ethoc_write(priv, MIITX_DATA, val);
ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE);
- rc = wait_for_bit(__func__, ethoc_reg(priv, MIISTATUS),
- MIISTATUS_BUSY, false, CONFIG_SYS_HZ, false);
+ rc = wait_for_bit_le32(ethoc_reg(priv, MIISTATUS),
+ MIISTATUS_BUSY, false, CONFIG_SYS_HZ, false);
if (rc == 0) {
/* reset MII command register */
diff --git a/drivers/net/pic32_eth.c b/drivers/net/pic32_eth.c
index 0b89911f04..7129372790 100644
--- a/drivers/net/pic32_eth.c
+++ b/drivers/net/pic32_eth.c
@@ -64,8 +64,8 @@ static int pic32_mii_init(struct pic32eth_dev *priv)
writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
/* wait till busy */
- wait_for_bit(__func__, &ectl_p->stat.raw, ETHSTAT_BUSY, false,
- CONFIG_SYS_HZ, false);
+ wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
+ CONFIG_SYS_HZ, false);
/* turn controller ON to access PHY over MII */
writel(ETHCON_ON, &ectl_p->con1.set);
@@ -239,8 +239,8 @@ static void pic32_ctrl_reset(struct pic32eth_dev *priv)
writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
/* wait till busy */
- wait_for_bit(__func__, &ectl_p->stat.raw, ETHSTAT_BUSY, false,
- CONFIG_SYS_HZ, false);
+ wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
+ CONFIG_SYS_HZ, false);
/* decrement received buffcnt to zero. */
while (readl(&ectl_p->stat.raw) & ETHSTAT_BUFCNT)
writel(ETHCON_BUFCDEC, &ectl_p->con1.set);
@@ -375,8 +375,8 @@ static void pic32_eth_stop(struct udevice *dev)
mdelay(10);
/* wait until everything is down */
- wait_for_bit(__func__, &ectl_p->stat.raw, ETHSTAT_BUSY, false,
- 2 * CONFIG_SYS_HZ, false);
+ wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
+ 2 * CONFIG_SYS_HZ, false);
/* clear any existing interrupt event */
writel(0xffffffff, &ectl_p->irq.clr);
diff --git a/drivers/net/pic32_mdio.c b/drivers/net/pic32_mdio.c
index 578fc96905..6ae5c40fa3 100644
--- a/drivers/net/pic32_mdio.c
+++ b/drivers/net/pic32_mdio.c
@@ -22,8 +22,8 @@ static int pic32_mdio_write(struct mii_dev *bus,
struct pic32_mii_regs *mii_regs = bus->priv;
/* Wait for the previous operation to finish */
- wait_for_bit(__func__, &mii_regs->mind.raw, MIIMIND_BUSY,
- false, CONFIG_SYS_HZ, true);
+ wait_for_bit_le32(&mii_regs->mind.raw, MIIMIND_BUSY,
+ false, CONFIG_SYS_HZ, true);
/* Put phyaddr and regaddr into MIIMADD */
v = (addr << MIIMADD_PHYADDR_SHIFT) | (reg & MIIMADD_REGADDR);
@@ -36,8 +36,8 @@ static int pic32_mdio_write(struct mii_dev *bus,
udelay(12);
/* Wait for write to complete */
- wait_for_bit(__func__, &mii_regs->mind.raw, MIIMIND_BUSY,
- false, CONFIG_SYS_HZ, true);
+ wait_for_bit_le32(&mii_regs->mind.raw, MIIMIND_BUSY,
+ false, CONFIG_SYS_HZ, true);
return 0;
}
@@ -48,8 +48,8 @@ static int pic32_mdio_read(struct mii_dev *bus, int addr, int devaddr, int reg)
struct pic32_mii_regs *mii_regs = bus->priv;
/* Wait for the previous operation to finish */
- wait_for_bit(__func__, &mii_regs->mind.raw, MIIMIND_BUSY,
- false, CONFIG_SYS_HZ, true);
+ wait_for_bit_le32(&mii_regs->mind.raw, MIIMIND_BUSY,
+ false, CONFIG_SYS_HZ, true);
/* Put phyaddr and regaddr into MIIMADD */
v = (addr << MIIMADD_PHYADDR_SHIFT) | (reg & MIIMADD_REGADDR);
@@ -62,9 +62,9 @@ static int pic32_mdio_read(struct mii_dev *bus, int addr, int devaddr, int reg)
udelay(12);
/* Wait for read to complete */
- wait_for_bit(__func__, &mii_regs->mind.raw,
- MIIMIND_NOTVALID | MIIMIND_BUSY,
- false, CONFIG_SYS_HZ, false);
+ wait_for_bit_le32(&mii_regs->mind.raw,
+ MIIMIND_NOTVALID | MIIMIND_BUSY,
+ false, CONFIG_SYS_HZ, false);
/* Clear the command register */
writel(0, &mii_regs->mcmd.raw);
@@ -82,22 +82,22 @@ static int pic32_mdio_reset(struct mii_dev *bus)
writel(MIIMCFG_RSTMGMT, &mii_regs->mcfg.raw);
/* Wait for the operation to finish */
- wait_for_bit(__func__, &mii_regs->mind.raw, MIIMIND_BUSY,
+ wait_for_bit_le32(&mii_regs->mind.raw, MIIMIND_BUSY,
false, CONFIG_SYS_HZ, true);
/* Clear reset bit */
writel(0, &mii_regs->mcfg);
/* Wait for the operation to finish */
- wait_for_bit(__func__, &mii_regs->mind.raw, MIIMIND_BUSY,
- false, CONFIG_SYS_HZ, true);
+ wait_for_bit_le32(&mii_regs->mind.raw, MIIMIND_BUSY,
+ false, CONFIG_SYS_HZ, true);
/* Set the MII Management Clock (MDC) - no faster than 2.5 MHz */
writel(MIIMCFG_CLKSEL_DIV40, &mii_regs->mcfg.raw);
/* Wait for the operation to finish */
- wait_for_bit(__func__, &mii_regs->mind.raw, MIIMIND_BUSY,
- false, CONFIG_SYS_HZ, true);
+ wait_for_bit_le32(&mii_regs->mind.raw, MIIMIND_BUSY,
+ false, CONFIG_SYS_HZ, true);
return 0;
}
diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c
index dc743e113d..26bd915291 100644
--- a/drivers/net/ravb.c
+++ b/drivers/net/ravb.c
@@ -222,8 +222,8 @@ static int ravb_reset(struct udevice *dev)
writel(CCC_OPC_CONFIG, eth->iobase + RAVB_REG_CCC);
/* Check the operating mode is changed to the config mode. */
- return wait_for_bit(dev->name, (void *)eth->iobase + RAVB_REG_CSR,
- CSR_OPS_CONFIG, true, 100, true);
+ return wait_for_bit_le32(eth->iobase + RAVB_REG_CSR,
+ CSR_OPS_CONFIG, true, 100, true);
}
static void ravb_base_desc_init(struct ravb_priv *eth)
diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index 9a2a578ff9..70a2e95a8e 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -366,8 +366,8 @@ static int axi_ethernet_init(struct axidma_priv *priv)
* processor mode and hence bypass in this mode
*/
if (!priv->eth_hasnobuf) {
- err = wait_for_bit(__func__, (const u32 *)&regs->is,
- XAE_INT_MGTRDY_MASK, true, 200, false);
+ err = wait_for_bit_le32(&regs->is, XAE_INT_MGTRDY_MASK,
+ true, 200, false);
if (err) {
printf("%s: Timeout\n", __func__);
return 1;
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 1dfd631e1a..2cc49bca92 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -192,8 +192,8 @@ static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
struct zynq_gem_regs *regs = priv->iobase;
int err;
- err = wait_for_bit(__func__, &regs->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
- true, 20000, false);
+ err = wait_for_bit_le32(&regs->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
+ true, 20000, false);
if (err)
return err;
@@ -205,8 +205,8 @@ static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
/* Write mgtcr and wait for completion */
writel(mgtcr, &regs->phymntnc);
- err = wait_for_bit(__func__, &regs->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
- true, 20000, false);
+ err = wait_for_bit_le32(&regs->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
+ true, 20000, false);
if (err)
return err;
@@ -514,8 +514,8 @@ static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
printf("TX buffers exhausted in mid frame\n");
- return wait_for_bit(__func__, &regs->txsr, ZYNQ_GEM_TSR_DONE,
- true, 20000, true);
+ return wait_for_bit_le32(&regs->txsr, ZYNQ_GEM_TSR_DONE,
+ true, 20000, true);
}
/* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
generated by cgit (git 2.34.1) at 2024-12-25 10:06:09 +0000