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-rw-r--r--drivers/video/Kconfig10
-rw-r--r--drivers/video/rockchip/Kconfig50
-rw-r--r--drivers/video/rockchip/Makefile8
-rw-r--r--drivers/video/rockchip/rk_mipi.c491
-rw-r--r--drivers/video/rockchip/rk_vop.c30
5 files changed, 573 insertions, 16 deletions
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index e29c3fcfc6..446cca90d4 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -425,15 +425,7 @@ config VIDEO_FSL_DCU_MAX_FB_SIZE_MB
Set maximum framebuffer size to be used for Freescale Display
Controller Unit (DCU4).
-config VIDEO_ROCKCHIP
- bool "Enable Rockchip video support"
- depends on DM_VIDEO
- help
- Rockchip SoCs provide video output capabilities for High-Definition
- Multimedia Interface (HDMI), Low-voltage Differential Signalling
- (LVDS), embedded DisplayPort (eDP) and Display Serial Interface
- (DSI). This driver supports the on-chip video output device, and
- targets the Rockchip RK3288.
+source "drivers/video/rockchip/Kconfig"
config VIDEO_SANDBOX_SDL
bool "Enable sandbox video console using SDL"
diff --git a/drivers/video/rockchip/Kconfig b/drivers/video/rockchip/Kconfig
new file mode 100644
index 0000000000..9267b28781
--- /dev/null
+++ b/drivers/video/rockchip/Kconfig
@@ -0,0 +1,50 @@
+#
+# Video drivers selection for rockchip soc. These configs only impact the
+# compile process. You can surely check all the options. In this case, all the
+# display driver will be compiled, but which drivers finally will be used is
+# decided by device tree configuration. What's more, enable needed power for
+# display by configure the device tree, and the vop driver will do the rest.
+#
+# Author: Eric Gao <eric.gao@rock-chips.com>
+#
+
+menuconfig VIDEO_ROCKCHIP
+ bool "Enable Rockchip Video Support"
+ depends on DM_VIDEO
+ help
+ Rockchip SoCs provide video output capabilities for High-Definition
+ Multimedia Interface (HDMI), Low-voltage Differential Signalling
+ (LVDS), embedded DisplayPort (eDP) and Display Serial Interface
+ (DSI). This driver supports the on-chip video output device, and
+ targets the Rockchip RK3288 and RK3399.
+
+if VIDEO_ROCKCHIP
+
+config DISPLAY_ROCKCHIP_EDP
+ bool "EDP Port"
+ depends on VIDEO_ROCKCHIP
+ help
+ This enables Embedded DisplayPort(EDP) display support.
+
+config DISPLAY_ROCKCHIP_LVDS
+ bool "LVDS Port"
+ depends on VIDEO_ROCKCHIP
+ help
+ This enables Low-voltage Differential Signaling(LVDS) display
+ support.
+
+config DISPLAY_ROCKCHIP_HDMI
+ bool "HDMI port"
+ depends on VIDEO_ROCKCHIP
+ help
+ This enables High-Definition Multimedia Interface display support.
+
+config DISPLAY_ROCKCHIP_MIPI
+ bool "MIPI Port"
+ depends on VIDEO_ROCKCHIP
+ help
+ This enables Mobile Industry Processor Interface(MIPI) display
+ support. The mipi controller and dphy on rk3288& rk3399 support
+ 16,18, 24 bits per pixel with upto 2k resolution ratio.
+
+endif
diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/Makefile
index 755350b934..c742902ddb 100644
--- a/drivers/video/rockchip/Makefile
+++ b/drivers/video/rockchip/Makefile
@@ -5,4 +5,10 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += rk_edp.o rk_hdmi.o rk_vop.o rk_lvds.o ../dw_hdmi.o
+ifdef CONFIG_VIDEO_ROCKCHIP
+obj-y += rk_vop.o
+obj-$(CONFIG_DISPLAY_ROCKCHIP_EDP) += rk_edp.o
+obj-$(CONFIG_DISPLAY_ROCKCHIP_LVDS) += rk_lvds.o
+obj-$(CONFIG_DISPLAY_ROCKCHIP_HDMI) += rk_hdmi.o ../dw_hdmi.o
+obj-$(CONFIG_DISPLAY_ROCKCHIP_MIPI) += rk_mipi.o
+endif
diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c
new file mode 100644
index 0000000000..4d9d12e1d7
--- /dev/null
+++ b/drivers/video/rockchip/rk_mipi.c
@@ -0,0 +1,491 @@
+/*
+ * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
+ * Author: Eric Gao <eric.gao@rock-chips.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <display.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <panel.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/gpio.h>
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <dm/uclass-internal.h>
+#include <linux/kernel.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3399.h>
+#include <asm/arch/grf_rk3399.h>
+#include <asm/arch/rockchip_mipi_dsi.h>
+#include <dt-bindings/clock/rk3288-cru.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Private information for rk mipi
+ *
+ * @regs: mipi controller address
+ * @grf: GRF register
+ * @panel: panel assined by device tree
+ * @ref_clk: reference clock for mipi dsi pll
+ * @sysclk: config clock for mipi dsi register
+ * @pix_clk: pixel clock for vop->dsi data transmission
+ * @phy_clk: mipi dphy output clock
+ * @txbyte_clk: clock for dsi->dphy high speed data transmission
+ * @txesc_clk: clock for tx esc mode
+ */
+struct rk_mipi_priv {
+ void __iomem *regs;
+ struct rk3399_grf_regs *grf;
+ struct udevice *panel;
+ struct mipi_dsi *dsi;
+ u32 ref_clk;
+ u32 sys_clk;
+ u32 pix_clk;
+ u32 phy_clk;
+ u32 txbyte_clk;
+ u32 txesc_clk;
+};
+
+static int rk_mipi_read_timing(struct udevice *dev,
+ struct display_timing *timing)
+{
+ int ret;
+
+ ret = fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(dev),
+ 0, timing);
+ if (ret) {
+ debug("%s: Failed to decode display timing (ret=%d)\n",
+ __func__, ret);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/*
+ * Register write function used only for mipi dsi controller.
+ * Parameter:
+ * @regs: mipi controller address
+ * @reg: combination of regaddr(16bit)|bitswidth(8bit)|offset(8bit) you can
+ * use define in rk_mipi.h directly for this parameter
+ * @val: value that will be write to specified bits of register
+ */
+static void rk_mipi_dsi_write(u32 regs, u32 reg, u32 val)
+{
+ u32 dat;
+ u32 mask;
+ u32 offset = (reg >> OFFSET_SHIFT) & 0xff;
+ u32 bits = (reg >> BITS_SHIFT) & 0xff;
+ u64 addr = (reg >> ADDR_SHIFT) + regs;
+
+ /* Mask for specifiled bits,the corresponding bits will be clear */
+ mask = ~((0xffffffff << offset) & (0xffffffff >> (32 - offset - bits)));
+
+ /* Make sure val in the available range */
+ val &= ~(0xffffffff << bits);
+
+ /* Get register's original val */
+ dat = readl(addr);
+
+ /* Clear specified bits */
+ dat &= mask;
+
+ /* Fill specified bits */
+ dat |= val << offset;
+
+ writel(dat, addr);
+}
+
+static int rk_mipi_dsi_enable(struct udevice *dev,
+ const struct display_timing *timing)
+{
+ int node, timing_node;
+ int val;
+ struct rk_mipi_priv *priv = dev_get_priv(dev);
+ u64 regs = (u64)priv->regs;
+ struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev);
+ u32 txbyte_clk = priv->txbyte_clk;
+ u32 txesc_clk = priv->txesc_clk;
+
+ txesc_clk = txbyte_clk/(txbyte_clk/txesc_clk + 1);
+
+ /* Select the video source */
+ switch (disp_uc_plat->source_id) {
+ case VOP_B:
+ rk_clrsetreg(&priv->grf->soc_con20, GRF_DSI0_VOP_SEL_MASK,
+ GRF_DSI0_VOP_SEL_B << GRF_DSI0_VOP_SEL_SHIFT);
+ break;
+ case VOP_L:
+ rk_clrsetreg(&priv->grf->soc_con20, GRF_DSI0_VOP_SEL_MASK,
+ GRF_DSI0_VOP_SEL_L << GRF_DSI0_VOP_SEL_SHIFT);
+ break;
+ default:
+ debug("%s: Invalid VOP id\n", __func__);
+ return -EINVAL;
+ }
+
+ /* Set Controller as TX mode */
+ val = GRF_DPHY_TX0_RXMODE_DIS << GRF_DPHY_TX0_RXMODE_SHIFT;
+ rk_clrsetreg(&priv->grf->soc_con22, GRF_DPHY_TX0_RXMODE_MASK, val);
+
+ /* Exit tx stop mode */
+ val |= GRF_DPHY_TX0_TXSTOPMODE_DIS << GRF_DPHY_TX0_TXSTOPMODE_SHIFT;
+ rk_clrsetreg(&priv->grf->soc_con22, GRF_DPHY_TX0_TXSTOPMODE_MASK, val);
+
+ /* Disable turnequest */
+ val |= GRF_DPHY_TX0_TURNREQUEST_DIS << GRF_DPHY_TX0_TURNREQUEST_SHIFT;
+ rk_clrsetreg(&priv->grf->soc_con22, GRF_DPHY_TX0_TURNREQUEST_MASK, val);
+
+ /* Set Display timing parameter */
+ rk_mipi_dsi_write(regs, VID_HSA_TIME, timing->hsync_len.typ);
+ rk_mipi_dsi_write(regs, VID_HBP_TIME, timing->hback_porch.typ);
+ rk_mipi_dsi_write(regs, VID_HLINE_TIME, (timing->hsync_len.typ
+ + timing->hback_porch.typ + timing->hactive.typ
+ + timing->hfront_porch.typ));
+ rk_mipi_dsi_write(regs, VID_VSA_LINES, timing->vsync_len.typ);
+ rk_mipi_dsi_write(regs, VID_VBP_LINES, timing->vback_porch.typ);
+ rk_mipi_dsi_write(regs, VID_VFP_LINES, timing->vfront_porch.typ);
+ rk_mipi_dsi_write(regs, VID_ACTIVE_LINES, timing->vactive.typ);
+
+ /* Set Signal Polarity */
+ val = (timing->flags & DISPLAY_FLAGS_HSYNC_LOW) ? 1 : 0;
+ rk_mipi_dsi_write(regs, HSYNC_ACTIVE_LOW, val);
+
+ val = (timing->flags & DISPLAY_FLAGS_VSYNC_LOW) ? 1 : 0;
+ rk_mipi_dsi_write(regs, VSYNC_ACTIVE_LOW, val);
+
+ val = (timing->flags & DISPLAY_FLAGS_DE_LOW) ? 1 : 0;
+ rk_mipi_dsi_write(regs, DISPLAY_FLAGS_DE_LOW, val);
+
+ val = (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) ? 1 : 0;
+ rk_mipi_dsi_write(regs, COLORM_ACTIVE_LOW, val);
+
+ /* Set video mode */
+ rk_mipi_dsi_write(regs, CMD_VIDEO_MODE, VIDEO_MODE);
+
+ /* Set video mode transmission type as burst mode */
+ rk_mipi_dsi_write(regs, VID_MODE_TYPE, BURST_MODE);
+
+ /* Set pix num in a video package */
+ rk_mipi_dsi_write(regs, VID_PKT_SIZE, 0x4b0);
+
+ /* Set dpi color coding depth 24 bit */
+ timing_node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(dev),
+ "display-timings");
+ node = fdt_first_subnode(gd->fdt_blob, timing_node);
+ val = fdtdec_get_int(gd->fdt_blob, node, "bits-per-pixel", -1);
+ switch (val) {
+ case 16:
+ rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_16BIT_CFG_1);
+ break;
+ case 24:
+ rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_24BIT);
+ break;
+ case 30:
+ rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_30BIT);
+ break;
+ default:
+ rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_24BIT);
+ }
+ /* Enable low power mode */
+ rk_mipi_dsi_write(regs, LP_CMD_EN, 1);
+ rk_mipi_dsi_write(regs, LP_HFP_EN, 1);
+ rk_mipi_dsi_write(regs, LP_VACT_EN, 1);
+ rk_mipi_dsi_write(regs, LP_VFP_EN, 1);
+ rk_mipi_dsi_write(regs, LP_VBP_EN, 1);
+ rk_mipi_dsi_write(regs, LP_VSA_EN, 1);
+
+ /* Division for timeout counter clk */
+ rk_mipi_dsi_write(regs, TO_CLK_DIVISION, 0x0a);
+
+ /* Tx esc clk division from txbyte clk */
+ rk_mipi_dsi_write(regs, TX_ESC_CLK_DIVISION, txbyte_clk/txesc_clk);
+
+ /* Timeout count for hs<->lp transation between Line period */
+ rk_mipi_dsi_write(regs, HSTX_TO_CNT, 0x3e8);
+
+ /* Phy State transfer timing */
+ rk_mipi_dsi_write(regs, PHY_STOP_WAIT_TIME, 32);
+ rk_mipi_dsi_write(regs, PHY_TXREQUESTCLKHS, 1);
+ rk_mipi_dsi_write(regs, PHY_HS2LP_TIME, 0x14);
+ rk_mipi_dsi_write(regs, PHY_LP2HS_TIME, 0x10);
+ rk_mipi_dsi_write(regs, MAX_RD_TIME, 0x2710);
+
+ /* Power on */
+ rk_mipi_dsi_write(regs, SHUTDOWNZ, 1);
+
+ return 0;
+}
+
+/* rk mipi dphy write function. It is used to write test data to dphy */
+static void rk_mipi_phy_write(u32 regs, unsigned char test_code,
+ unsigned char *test_data, unsigned char size)
+{
+ int i = 0;
+
+ /* Write Test code */
+ rk_mipi_dsi_write(regs, PHY_TESTCLK, 1);
+ rk_mipi_dsi_write(regs, PHY_TESTDIN, test_code);
+ rk_mipi_dsi_write(regs, PHY_TESTEN, 1);
+ rk_mipi_dsi_write(regs, PHY_TESTCLK, 0);
+ rk_mipi_dsi_write(regs, PHY_TESTEN, 0);
+
+ /* Write Test data */
+ for (i = 0; i < size; i++) {
+ rk_mipi_dsi_write(regs, PHY_TESTCLK, 0);
+ rk_mipi_dsi_write(regs, PHY_TESTDIN, test_data[i]);
+ rk_mipi_dsi_write(regs, PHY_TESTCLK, 1);
+ }
+}
+
+/*
+ * Mipi dphy config function. Calculate the suitable prediv, feedback div,
+ * fsfreqrang value ,cap ,lpf and so on according to the given pix clk rate,
+ * and then enable phy.
+ */
+static int rk_mipi_phy_enable(struct udevice *dev)
+{
+ int i;
+ struct rk_mipi_priv *priv = dev_get_priv(dev);
+ u64 regs = (u64)priv->regs;
+ u64 fbdiv;
+ u64 prediv = 1;
+ u32 max_fbdiv = 512;
+ u32 max_prediv, min_prediv;
+ u64 ddr_clk = priv->phy_clk;
+ u32 refclk = priv->ref_clk;
+ u32 remain = refclk;
+ unsigned char test_data[2] = {0};
+
+ int freq_rang[][2] = {
+ {90, 0x01}, {100, 0x10}, {110, 0x20}, {130, 0x01},
+ {140, 0x11}, {150, 0x21}, {170, 0x02}, {180, 0x12},
+ {200, 0x22}, {220, 0x03}, {240, 0x13}, {250, 0x23},
+ {270, 0x04}, {300, 0x14}, {330, 0x05}, {360, 0x15},
+ {400, 0x25}, {450, 0x06}, {500, 0x16}, {550, 0x07},
+ {600, 0x17}, {650, 0x08}, {700, 0x18}, {750, 0x09},
+ {800, 0x19}, {850, 0x29}, {900, 0x39}, {950, 0x0a},
+ {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
+ {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
+ {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
+ };
+
+ /* Shutdown mode */
+ rk_mipi_dsi_write(regs, PHY_SHUTDOWNZ, 0);
+ rk_mipi_dsi_write(regs, PHY_RSTZ, 0);
+ rk_mipi_dsi_write(regs, PHY_TESTCLR, 1);
+
+ /* Pll locking */
+ rk_mipi_dsi_write(regs, PHY_TESTCLR, 0);
+
+ /* config cp and lfp */
+ test_data[0] = 0x80 | (ddr_clk / (200 * MHz)) << 3 | 0x3;
+ rk_mipi_phy_write(regs, CODE_PLL_VCORANGE_VCOCAP, test_data, 1);
+
+ test_data[0] = 0x8;
+ rk_mipi_phy_write(regs, CODE_PLL_CPCTRL, test_data, 1);
+
+ test_data[0] = 0x80 | 0x40;
+ rk_mipi_phy_write(regs, CODE_PLL_LPF_CP, test_data, 1);
+
+ /* select the suitable value for fsfreqrang reg */
+ for (i = 0; i < ARRAY_SIZE(freq_rang); i++) {
+ if (ddr_clk / (MHz) >= freq_rang[i][0])
+ break;
+ }
+ if (i == ARRAY_SIZE(freq_rang)) {
+ debug("%s: Dphy freq out of range!\n", __func__);
+ return -EINVAL;
+ }
+ test_data[0] = freq_rang[i][1] << 1;
+ rk_mipi_phy_write(regs, CODE_HS_RX_LANE0, test_data, 1);
+
+ /*
+ * Calculate the best ddrclk and it's corresponding div value. If the
+ * given pixelclock is great than 250M, ddrclk will be fix 1500M.
+ * Otherwise,
+ * it's equal to ddr_clk= pixclk * 6. 40MHz >= refclk / prediv >= 5MHz
+ * according to spec.
+ */
+ max_prediv = (refclk / (5 * MHz));
+ min_prediv = ((refclk / (40 * MHz)) ? (refclk / (40 * MHz) + 1) : 1);
+
+ debug("%s: DEBUG: max_prediv=%u, min_prediv=%u\n", __func__, max_prediv,
+ min_prediv);
+
+ if (max_prediv < min_prediv) {
+ debug("%s: Invalid refclk value\n", __func__);
+ return -EINVAL;
+ }
+
+ /* Calculate the best refclk and feedback division value for dphy pll */
+ for (i = min_prediv; i < max_prediv; i++) {
+ if ((ddr_clk * i % refclk < remain) &&
+ (ddr_clk * i / refclk) < max_fbdiv) {
+ prediv = i;
+ remain = ddr_clk * i % refclk;
+ }
+ }
+ fbdiv = ddr_clk * prediv / refclk;
+ ddr_clk = refclk * fbdiv / prediv;
+ priv->phy_clk = ddr_clk;
+
+ debug("%s: DEBUG: refclk=%u, refclk=%llu, fbdiv=%llu, phyclk=%llu\n",
+ __func__, refclk, prediv, fbdiv, ddr_clk);
+
+ /* config prediv and feedback reg */
+ test_data[0] = prediv - 1;
+ rk_mipi_phy_write(regs, CODE_PLL_INPUT_DIV_RAT, test_data, 1);
+ test_data[0] = (fbdiv - 1) & 0x1f;
+ rk_mipi_phy_write(regs, CODE_PLL_LOOP_DIV_RAT, test_data, 1);
+ test_data[0] = (fbdiv - 1) >> 5 | 0x80;
+ rk_mipi_phy_write(regs, CODE_PLL_LOOP_DIV_RAT, test_data, 1);
+ test_data[0] = 0x30;
+ rk_mipi_phy_write(regs, CODE_PLL_INPUT_LOOP_DIV_RAT, test_data, 1);
+
+ /* rest config */
+ test_data[0] = 0x4d;
+ rk_mipi_phy_write(regs, CODE_BANDGAP_BIAS_CTRL, test_data, 1);
+
+ test_data[0] = 0x3d;
+ rk_mipi_phy_write(regs, CODE_TERMINATION_CTRL, test_data, 1);
+
+ test_data[0] = 0xdf;
+ rk_mipi_phy_write(regs, CODE_TERMINATION_CTRL, test_data, 1);
+
+ test_data[0] = 0x7;
+ rk_mipi_phy_write(regs, CODE_AFE_BIAS_BANDGAP_ANOLOG, test_data, 1);
+
+ test_data[0] = 0x80 | 0x7;
+ rk_mipi_phy_write(regs, CODE_AFE_BIAS_BANDGAP_ANOLOG, test_data, 1);
+
+ test_data[0] = 0x80 | 15;
+ rk_mipi_phy_write(regs, CODE_HSTXDATALANEREQUSETSTATETIME,
+ test_data, 1);
+ test_data[0] = 0x80 | 85;
+ rk_mipi_phy_write(regs, CODE_HSTXDATALANEPREPARESTATETIME,
+ test_data, 1);
+ test_data[0] = 0x40 | 10;
+ rk_mipi_phy_write(regs, CODE_HSTXDATALANEHSZEROSTATETIME,
+ test_data, 1);
+
+ /* enter into stop mode */
+ rk_mipi_dsi_write(regs, N_LANES, 0x03);
+ rk_mipi_dsi_write(regs, PHY_ENABLECLK, 1);
+ rk_mipi_dsi_write(regs, PHY_FORCEPLL, 1);
+ rk_mipi_dsi_write(regs, PHY_SHUTDOWNZ, 1);
+ rk_mipi_dsi_write(regs, PHY_RSTZ, 1);
+
+ return 0;
+}
+
+/*
+ * This function is called by rk_display_init() using rk_mipi_dsi_enable() and
+ * rk_mipi_phy_enable() to initialize mipi controller and dphy. If success,
+ * enable backlight.
+ */
+static int rk_display_enable(struct udevice *dev, int panel_bpp,
+ const struct display_timing *timing)
+{
+ int ret;
+ struct rk_mipi_priv *priv = dev_get_priv(dev);
+
+ /* Fill the mipi controller parameter */
+ priv->ref_clk = 24 * MHz;
+ priv->sys_clk = priv->ref_clk;
+ priv->pix_clk = timing->pixelclock.typ;
+ priv->phy_clk = priv->pix_clk * 6;
+ priv->txbyte_clk = priv->phy_clk / 8;
+ priv->txesc_clk = 20 * MHz;
+
+ /* Config and enable mipi dsi according to timing */
+ ret = rk_mipi_dsi_enable(dev, timing);
+ if (ret) {
+ debug("%s: rk_mipi_dsi_enable() failed (err=%d)\n",
+ __func__, ret);
+ return ret;
+ }
+
+ /* Config and enable mipi phy */
+ ret = rk_mipi_phy_enable(dev);
+ if (ret) {
+ debug("%s: rk_mipi_phy_enable() failed (err=%d)\n",
+ __func__, ret);
+ return ret;
+ }
+
+ /* Enable backlight */
+ ret = panel_enable_backlight(priv->panel);
+ if (ret) {
+ debug("%s: panel_enable_backlight() failed (err=%d)\n",
+ __func__, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int rk_mipi_ofdata_to_platdata(struct udevice *dev)
+{
+ struct rk_mipi_priv *priv = dev_get_priv(dev);
+
+ priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ if (priv->grf <= 0) {
+ debug("%s: Get syscon grf failed (ret=%llu)\n",
+ __func__, (u64)priv->grf);
+ return -ENXIO;
+ }
+ priv->regs = (void *)dev_get_addr(dev);
+ if (priv->regs <= 0) {
+ debug("%s: Get MIPI dsi address failed (ret=%llu)\n", __func__,
+ (u64)priv->regs);
+ return -ENXIO;
+ }
+
+ return 0;
+}
+
+/*
+ * Probe function: check panel existence and readingit's timing. Then config
+ * mipi dsi controller and enable it according to the timing parameter.
+ */
+static int rk_mipi_probe(struct udevice *dev)
+{
+ int ret;
+ struct rk_mipi_priv *priv = dev_get_priv(dev);
+
+ ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel",
+ &priv->panel);
+ if (ret) {
+ debug("%s: Can not find panel (err=%d)\n", __func__, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct dm_display_ops rk_mipi_dsi_ops = {
+ .read_timing = rk_mipi_read_timing,
+ .enable = rk_display_enable,
+};
+
+static const struct udevice_id rk_mipi_dsi_ids[] = {
+ { .compatible = "rockchip,rk3399_mipi_dsi" },
+ { }
+};
+
+U_BOOT_DRIVER(rk_mipi_dsi) = {
+ .name = "rk_mipi_dsi",
+ .id = UCLASS_DISPLAY,
+ .of_match = rk_mipi_dsi_ids,
+ .ofdata_to_platdata = rk_mipi_ofdata_to_platdata,
+ .probe = rk_mipi_probe,
+ .ops = &rk_mipi_dsi_ops,
+ .priv_auto_alloc_size = sizeof(struct rk_mipi_priv),
+};
diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index bc02f800dc..aa6ca8c859 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -117,6 +117,10 @@ void rkvop_mode_set(struct rk3288_vop *regs,
clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
V_RGB_OUT_EN(1));
break;
+ case VOP_MODE_MIPI:
+ clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
+ V_MIPI_OUT_EN(1));
+ break;
}
if (mode == VOP_MODE_HDMI || mode == VOP_MODE_EDP)
@@ -177,13 +181,11 @@ void rkvop_mode_set(struct rk3288_vop *regs,
*
* @dev: VOP device that we want to connect to the display
* @fbbase: Frame buffer address
- * @l2bpp Log2 of bits-per-pixels for the display
* @ep_node: Device tree node to process - this is the offset of an endpoint
* node within the VOP's 'port' list.
* @return 0 if OK, -ve if something went wrong
*/
-int rk_display_init(struct udevice *dev, ulong fbbase,
- enum video_log2_bpp l2bpp, int ep_node)
+int rk_display_init(struct udevice *dev, ulong fbbase, int ep_node)
{
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
const void *blob = gd->fdt_blob;
@@ -195,6 +197,7 @@ int rk_display_init(struct udevice *dev, ulong fbbase,
int ret, remote, i, offset;
struct display_plat *disp_uc_plat;
struct clk clk;
+ enum video_log2_bpp l2bpp;
vop_id = fdtdec_get_int(blob, ep_node, "reg", -1);
debug("vop_id=%d\n", vop_id);
@@ -244,11 +247,24 @@ int rk_display_init(struct udevice *dev, ulong fbbase,
ret = clk_get_by_index(dev, 1, &clk);
if (!ret)
ret = clk_set_rate(&clk, timing.pixelclock.typ);
- if (ret) {
+ if (IS_ERR_VALUE(ret)) {
debug("%s: Failed to set pixel clock: ret=%d\n", __func__, ret);
return ret;
}
+ /* Set bitwidth for vop display according to vop mode */
+ switch (vop_id) {
+ case VOP_MODE_EDP:
+ case VOP_MODE_HDMI:
+ case VOP_MODE_LVDS:
+ l2bpp = VIDEO_BPP16;
+ break;
+ case VOP_MODE_MIPI:
+ l2bpp = VIDEO_BPP32;
+ break;
+ default:
+ l2bpp = VIDEO_BPP16;
+ }
rkvop_mode_set(regs, &timing, vop_id);
rkvop_enable(regs, fbbase, 1 << l2bpp, &timing);
@@ -326,7 +342,7 @@ static int rk_vop_probe(struct udevice *dev)
for (node = fdt_first_subnode(blob, port);
node > 0;
node = fdt_next_subnode(blob, node)) {
- ret = rk_display_init(dev, plat->base, VIDEO_BPP16, node);
+ ret = rk_display_init(dev, plat->base, node);
if (ret)
debug("Device failed: ret=%d\n", ret);
if (!ret)
@@ -341,7 +357,7 @@ static int rk_vop_bind(struct udevice *dev)
{
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
- plat->size = 1920 * 1080 * 2;
+ plat->size = 1920 * 1200 * 4;
return 0;
}
@@ -350,6 +366,8 @@ static const struct video_ops rk_vop_ops = {
};
static const struct udevice_id rk_vop_ids[] = {
+ { .compatible = "rockchip,rk3399-vop-big" },
+ { .compatible = "rockchip,rk3399-vop-lit" },
{ .compatible = "rockchip,rk3288-vop" },
{ }
};
generated by cgit (git 2.34.1) at 2024-12-26 12:57:48 +0000