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-rw-r--r--drivers/block/blk-uclass.c4
-rw-r--r--drivers/clk/Makefile20
-rw-r--r--drivers/clk/clk-hsdk-cgu.c177
-rw-r--r--drivers/clk/clk-uclass.c22
-rw-r--r--drivers/clk/clk_fixed_rate.c6
-rw-r--r--drivers/clk/clk_stm32f.c7
-rw-r--r--drivers/core/device.c7
-rw-r--r--drivers/core/ofnode.c35
-rw-r--r--drivers/core/read.c26
-rw-r--r--drivers/core/root.c11
-rw-r--r--drivers/crypto/fsl/fsl_hash.c20
-rw-r--r--drivers/ddr/fsl/fsl_ddr_gen4.c4
-rw-r--r--drivers/ddr/marvell/a38x/ddr3_init.h3
-rw-r--r--drivers/ddr/marvell/a38x/ddr3_topology_def.h3
-rw-r--r--drivers/ddr/marvell/a38x/ddr3_training.c50
-rw-r--r--drivers/ddr/marvell/a38x/ddr3_training_db.c19
-rw-r--r--drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c22
-rw-r--r--drivers/ddr/marvell/a38x/ddr3_training_static.c3
-rw-r--r--drivers/dma/ti-edma3.c55
-rw-r--r--drivers/gpio/Makefile1
-rw-r--r--drivers/gpio/pca953x.c6
-rw-r--r--drivers/gpio/pm8916_gpio.c7
-rw-r--r--drivers/gpio/stm32_gpio.c182
-rw-r--r--drivers/gpio/tca642x.c6
-rw-r--r--drivers/i2c/imx_lpi2c.c8
-rw-r--r--drivers/i2c/mxc_i2c.c6
-rw-r--r--drivers/misc/Makefile1
-rw-r--r--drivers/misc/fsl_portals.c305
-rw-r--r--drivers/misc/mxc_ocotp.c17
-rw-r--r--drivers/mmc/Kconfig81
-rw-r--r--drivers/mmc/Makefile4
-rw-r--r--drivers/mmc/exynos_dw_mmc.c3
-rw-r--r--drivers/mmc/fsl_esdhc.c18
-rw-r--r--drivers/mmc/gen_atmel_mci.c42
-rw-r--r--drivers/mmc/meson_gx_mmc.c2
-rw-r--r--drivers/mmc/mmc-uclass.c98
-rw-r--r--drivers/mmc/mmc.c1628
-rw-r--r--drivers/mmc/mmc_private.h4
-rw-r--r--drivers/mmc/omap_hsmmc.c257
-rw-r--r--drivers/mmc/sandbox_mmc.c5
-rw-r--r--drivers/mmc/sdhci-cadence.c114
-rw-r--r--drivers/mmc/sdhci.c13
-rw-r--r--drivers/net/Kconfig43
-rw-r--r--drivers/net/designware.c48
-rw-r--r--drivers/net/designware.h4
-rw-r--r--drivers/net/macb.c91
-rw-r--r--drivers/net/macb.h1
-rw-r--r--drivers/net/mvneta.c6
-rw-r--r--drivers/net/netconsole.c7
-rw-r--r--drivers/net/phy/Kconfig17
-rw-r--r--drivers/net/phy/Makefile1
-rw-r--r--drivers/net/phy/atheros.c1
-rw-r--r--drivers/net/phy/b53.c768
-rw-r--r--drivers/net/phy/marvell.c29
-rw-r--r--drivers/net/phy/miiphybb.c2
-rw-r--r--drivers/net/phy/phy.c3
-rw-r--r--drivers/net/sh_eth.c155
-rw-r--r--drivers/net/sh_eth.h76
-rw-r--r--drivers/pci/Makefile1
-rw-r--r--drivers/pci/pcie_imx.c15
-rw-r--r--drivers/pci/tsi108_pci.c167
-rw-r--r--drivers/pinctrl/mvebu/Kconfig4
-rw-r--r--drivers/pinctrl/pinctrl_stm32.c2
-rw-r--r--drivers/power/pmic/s2mps11.c28
-rw-r--r--drivers/power/power_core.c61
-rw-r--r--drivers/power/regulator/Kconfig8
-rw-r--r--drivers/power/regulator/Makefile1
-rw-r--r--drivers/power/regulator/s2mps11_regulator.c597
-rw-r--r--drivers/ram/stm32_sdram.c25
-rw-r--r--drivers/serial/Kconfig2
-rw-r--r--drivers/serial/Makefile2
-rw-r--r--drivers/serial/serial_lpuart.c18
-rw-r--r--drivers/serial/serial_stm32.c150
-rw-r--r--drivers/serial/serial_stm32.h (renamed from drivers/serial/serial_stm32x7.h)4
-rw-r--r--drivers/serial/serial_stm32x7.c159
-rw-r--r--drivers/spi/Kconfig6
-rw-r--r--drivers/spi/fsl_qspi.c18
-rw-r--r--drivers/spmi/spmi-msm.c12
-rw-r--r--drivers/sysreset/Makefile2
-rw-r--r--drivers/sysreset/sysreset_snapdragon.c40
-rw-r--r--drivers/usb/Kconfig4
-rw-r--r--drivers/usb/gadget/Kconfig8
-rw-r--r--drivers/usb/gadget/Makefile1
-rw-r--r--drivers/usb/gadget/f_rockusb.c718
-rw-r--r--drivers/usb/host/Kconfig6
-rw-r--r--drivers/usb/host/ehci-fsl.c8
-rw-r--r--drivers/usb/musb-new/Kconfig17
-rw-r--r--drivers/usb/musb-new/sunxi.c9
-rw-r--r--drivers/usb/musb/Kconfig29
-rw-r--r--drivers/usb/phy/Kconfig17
-rw-r--r--drivers/video/am335x-fb.c64
-rw-r--r--drivers/video/am335x-fb.h6
92 files changed, 5344 insertions, 1419 deletions
diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c
index 010ed32d3a..bfda2211f0 100644
--- a/drivers/block/blk-uclass.c
+++ b/drivers/block/blk-uclass.c
@@ -24,6 +24,7 @@ static const char *if_typename_str[IF_TYPE_COUNT] = {
[IF_TYPE_HOST] = "host",
[IF_TYPE_SYSTEMACE] = "ace",
[IF_TYPE_NVME] = "nvme",
+ [IF_TYPE_EFI] = "efi",
};
static enum uclass_id if_type_uclass_id[IF_TYPE_COUNT] = {
@@ -36,8 +37,9 @@ static enum uclass_id if_type_uclass_id[IF_TYPE_COUNT] = {
[IF_TYPE_SD] = UCLASS_INVALID,
[IF_TYPE_SATA] = UCLASS_AHCI,
[IF_TYPE_HOST] = UCLASS_ROOT,
- [IF_TYPE_NVME] = UCLASS_NVME,
[IF_TYPE_SYSTEMACE] = UCLASS_INVALID,
+ [IF_TYPE_NVME] = UCLASS_NVME,
+ [IF_TYPE_EFI] = UCLASS_EFI,
};
static enum if_type if_typename_to_iftype(const char *if_typename)
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 876c2b816f..dab106ab7f 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -6,21 +6,21 @@
#
obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o clk_fixed_rate.o
-obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
-obj-$(CONFIG_SANDBOX) += clk_sandbox.o
-obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
-obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
-obj-$(CONFIG_CLK_RENESAS) += renesas/
-obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o
-obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o
obj-y += tegra/
-obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
-obj-$(CONFIG_CLK_EXYNOS) += exynos/
+obj-$(CONFIG_ARCH_ASPEED) += aspeed/
+obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_CLK_AT91) += at91/
obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
+obj-$(CONFIG_CLK_EXYNOS) += exynos/
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
-obj-$(CONFIG_ARCH_ASPEED) += aspeed/
+obj-$(CONFIG_CLK_RENESAS) += renesas/
obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
+obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
+obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o
+obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o
+obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
+obj-$(CONFIG_SANDBOX) += clk_sandbox.o
+obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
obj-$(CONFIG_STM32H7) += clk_stm32h7.o
diff --git a/drivers/clk/clk-hsdk-cgu.c b/drivers/clk/clk-hsdk-cgu.c
index c80f90ec2f..4362d583cb 100644
--- a/drivers/clk/clk-hsdk-cgu.c
+++ b/drivers/clk/clk-hsdk-cgu.c
@@ -42,7 +42,9 @@
* |-->| TUNNEL PLL |
* | --------------
* | |
- * | |-->|CGU_TUN_IDIV|----------->
+ * | |-->|CGU_TUN_IDIV_TUN|----------->
+ * | |-->|CGU_TUN_IDIV_ROM|----------->
+ * | |-->|CGU_TUN_IDIV_PWM|----------->
* |
* | ------------
* |-->| HDMI PLL |
@@ -60,7 +62,9 @@
DECLARE_GLOBAL_DATA_PTR;
#define CGU_ARC_IDIV 0x080
-#define CGU_TUN_IDIV 0x380
+#define CGU_TUN_IDIV_TUN 0x380
+#define CGU_TUN_IDIV_ROM 0x390
+#define CGU_TUN_IDIV_PWM 0x3A0
#define CGU_HDMI_IDIV_APB 0x480
#define CGU_SYS_IDIV_APB 0x180
#define CGU_SYS_IDIV_AXI 0x190
@@ -114,8 +118,68 @@ DECLARE_GLOBAL_DATA_PTR;
#define CREG_CORE_IF_CLK_DIV_1 0x0
#define CREG_CORE_IF_CLK_DIV_2 0x1
+#define MIN_PLL_RATE 100000000 /* 100 MHz */
#define PARENT_RATE 33333333 /* fixed clock - xtal */
-#define CGU_MAX_CLOCKS 24
+#define CGU_MAX_CLOCKS 26
+
+#define CGU_SYS_CLOCKS 16
+#define MAX_AXI_CLOCKS 4
+
+#define CGU_TUN_CLOCKS 3
+#define MAX_TUN_CLOCKS 6
+
+struct hsdk_tun_idiv_cfg {
+ u32 oft;
+ u8 val[MAX_TUN_CLOCKS];
+};
+
+struct hsdk_tun_clk_cfg {
+ const u32 clk_rate[MAX_TUN_CLOCKS];
+ const u32 pll_rate[MAX_TUN_CLOCKS];
+ const struct hsdk_tun_idiv_cfg idiv[CGU_TUN_CLOCKS];
+};
+
+static const struct hsdk_tun_clk_cfg tun_clk_cfg = {
+ { 25000000, 50000000, 75000000, 100000000, 125000000, 150000000 },
+ { 600000000, 600000000, 600000000, 600000000, 700000000, 600000000 }, {
+ { CGU_TUN_IDIV_TUN, { 24, 12, 8, 6, 6, 4 } },
+ { CGU_TUN_IDIV_ROM, { 4, 4, 4, 4, 5, 4 } },
+ { CGU_TUN_IDIV_PWM, { 8, 8, 8, 8, 10, 8 } }
+ }
+};
+
+struct hsdk_sys_idiv_cfg {
+ u32 oft;
+ u8 val[MAX_AXI_CLOCKS];
+};
+
+struct hsdk_axi_clk_cfg {
+ const u32 clk_rate[MAX_AXI_CLOCKS];
+ const u32 pll_rate[MAX_AXI_CLOCKS];
+ const struct hsdk_sys_idiv_cfg idiv[CGU_SYS_CLOCKS];
+};
+
+static const struct hsdk_axi_clk_cfg axi_clk_cfg = {
+ { 200000000, 400000000, 600000000, 800000000 },
+ { 800000000, 800000000, 600000000, 800000000 }, {
+ { CGU_SYS_IDIV_APB, { 4, 4, 3, 4 } }, /* APB */
+ { CGU_SYS_IDIV_AXI, { 4, 2, 1, 1 } }, /* AXI */
+ { CGU_SYS_IDIV_ETH, { 2, 2, 2, 2 } }, /* ETH */
+ { CGU_SYS_IDIV_USB, { 2, 2, 2, 2 } }, /* USB */
+ { CGU_SYS_IDIV_SDIO, { 2, 2, 2, 2 } }, /* SDIO */
+ { CGU_SYS_IDIV_HDMI, { 2, 2, 2, 2 } }, /* HDMI */
+ { CGU_SYS_IDIV_GFX_CORE, { 1, 1, 1, 1 } }, /* GPU-CORE */
+ { CGU_SYS_IDIV_GFX_DMA, { 2, 2, 2, 2 } }, /* GPU-DMA */
+ { CGU_SYS_IDIV_GFX_CFG, { 4, 4, 3, 4 } }, /* GPU-CFG */
+ { CGU_SYS_IDIV_DMAC_CORE,{ 2, 2, 2, 2 } }, /* DMAC-CORE */
+ { CGU_SYS_IDIV_DMAC_CFG, { 4, 4, 3, 4 } }, /* DMAC-CFG */
+ { CGU_SYS_IDIV_SDIO_REF, { 8, 8, 6, 8 } }, /* SDIO-REF */
+ { CGU_SYS_IDIV_SPI_REF, { 24, 24, 18, 24 } }, /* SPI-REF */
+ { CGU_SYS_IDIV_I2C_REF, { 4, 4, 3, 4 } }, /* I2C-REF */
+ { CGU_SYS_IDIV_UART_REF, { 24, 24, 18, 24 } }, /* UART-REF */
+ { CGU_SYS_IDIV_EBI_REF, { 16, 16, 12, 16 } } /* EBI-REF */
+ }
+};
struct hsdk_pll_cfg {
u32 rate;
@@ -201,6 +265,9 @@ static const struct hsdk_pll_devdata hdmi_pll_dat = {
};
static ulong idiv_set(struct clk *, ulong);
+static ulong cpu_clk_set(struct clk *, ulong);
+static ulong axi_clk_set(struct clk *, ulong);
+static ulong tun_clk_set(struct clk *, ulong);
static ulong idiv_get(struct clk *);
static int idiv_off(struct clk *);
static ulong pll_set(struct clk *, ulong);
@@ -218,11 +285,11 @@ struct hsdk_cgu_clock_map {
static const struct hsdk_cgu_clock_map clock_map[] = {
{ CGU_ARC_PLL, 0, 0, &core_pll_dat, pll_get, pll_set, NULL },
- { CGU_ARC_PLL, 0, CGU_ARC_IDIV, &core_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_ARC_PLL, 0, CGU_ARC_IDIV, &core_pll_dat, idiv_get, cpu_clk_set, idiv_off },
{ CGU_DDR_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
{ CGU_SYS_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_APB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
- { CGU_SYS_PLL, 0, CGU_SYS_IDIV_AXI, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_SYS_PLL, 0, CGU_SYS_IDIV_AXI, &sdt_pll_dat, idiv_get, axi_clk_set, idiv_off },
{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_ETH, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_USB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_SDIO, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
@@ -238,7 +305,9 @@ static const struct hsdk_cgu_clock_map clock_map[] = {
{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_UART_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_EBI_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
{ CGU_TUN_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
- { CGU_TUN_PLL, 0, CGU_TUN_IDIV, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_TUN_PLL, 0, CGU_TUN_IDIV_TUN, &sdt_pll_dat, idiv_get, tun_clk_set, idiv_off },
+ { CGU_TUN_PLL, 0, CGU_TUN_IDIV_ROM, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_TUN_PLL, 0, CGU_TUN_IDIV_PWM, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
{ CGU_HDMI_PLL, 0, 0, &hdmi_pll_dat, pll_get, pll_set, NULL },
{ CGU_HDMI_PLL, 0, CGU_HDMI_IDIV_APB, &hdmi_pll_dat, idiv_get, idiv_set, idiv_off }
};
@@ -423,7 +492,7 @@ static ulong pll_set(struct clk *sclk, ulong rate)
}
}
- pr_err("invalid rate=%ld, parent_rate=%d\n", best_rate, PARENT_RATE);
+ pr_err("invalid rate=%ld Hz, parent_rate=%d Hz\n", best_rate, PARENT_RATE);
return -EINVAL;
}
@@ -453,6 +522,94 @@ static ulong idiv_get(struct clk *sclk)
return parent_rate / div_factor;
}
+/* Special behavior: wen we set this clock we set both idiv and pll */
+static ulong cpu_clk_set(struct clk *sclk, ulong rate)
+{
+ ulong ret;
+
+ ret = pll_set(sclk, rate);
+ idiv_set(sclk, rate);
+
+ return ret;
+}
+
+/* Special behavior: wen we set this clock we set both idiv and pll and all pll dividers */
+static ulong axi_clk_set(struct clk *sclk, ulong rate)
+{
+ struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
+ ulong pll_rate;
+ int i, freq_idx = -1;
+ ulong ret = 0;
+
+ pll_rate = pll_get(sclk);
+
+ for (i = 0; i < MAX_AXI_CLOCKS; i++) {
+ if (axi_clk_cfg.clk_rate[i] == rate) {
+ freq_idx = i;
+ break;
+ }
+ }
+
+ if (freq_idx < 0) {
+ pr_err("axi clk: invalid rate=%ld Hz\n", rate);
+ return -EINVAL;
+ }
+
+ /* configure PLL before dividers */
+ if (axi_clk_cfg.pll_rate[freq_idx] < pll_rate)
+ ret = pll_set(sclk, axi_clk_cfg.pll_rate[freq_idx]);
+
+ /* configure SYS dividers */
+ for (i = 0; i < CGU_SYS_CLOCKS; i++) {
+ clk->idiv_regs = clk->cgu_regs + axi_clk_cfg.idiv[i].oft;
+ hsdk_idiv_write(clk, axi_clk_cfg.idiv[i].val[freq_idx]);
+ }
+
+ /* configure PLL after dividers */
+ if (axi_clk_cfg.pll_rate[freq_idx] >= pll_rate)
+ ret = pll_set(sclk, axi_clk_cfg.pll_rate[freq_idx]);
+
+ return ret;
+}
+
+static ulong tun_clk_set(struct clk *sclk, ulong rate)
+{
+ struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
+ ulong pll_rate;
+ int i, freq_idx = -1;
+ ulong ret = 0;
+
+ pll_rate = pll_get(sclk);
+
+ for (i = 0; i < MAX_TUN_CLOCKS; i++) {
+ if (tun_clk_cfg.clk_rate[i] == rate) {
+ freq_idx = i;
+ break;
+ }
+ }
+
+ if (freq_idx < 0) {
+ pr_err("tun clk: invalid rate=%ld Hz\n", rate);
+ return -EINVAL;
+ }
+
+ /* configure PLL before dividers */
+ if (tun_clk_cfg.pll_rate[freq_idx] < pll_rate)
+ ret = pll_set(sclk, tun_clk_cfg.pll_rate[freq_idx]);
+
+ /* configure SYS dividers */
+ for (i = 0; i < CGU_TUN_CLOCKS; i++) {
+ clk->idiv_regs = clk->cgu_regs + tun_clk_cfg.idiv[i].oft;
+ hsdk_idiv_write(clk, tun_clk_cfg.idiv[i].val[freq_idx]);
+ }
+
+ /* configure PLL after dividers */
+ if (tun_clk_cfg.pll_rate[freq_idx] >= pll_rate)
+ ret = pll_set(sclk, tun_clk_cfg.pll_rate[freq_idx]);
+
+ return ret;
+}
+
static ulong idiv_set(struct clk *sclk, ulong rate)
{
struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
@@ -466,14 +623,14 @@ static ulong idiv_set(struct clk *sclk, ulong rate)
}
if (div_factor & ~CGU_IDIV_MASK) {
- pr_err("invalid rate=%ld, parent_rate=%ld, div=%d: max divider valie is%d\n",
+ pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: max divider valie is%d\n",
rate, parent_rate, div_factor, CGU_IDIV_MASK);
div_factor = CGU_IDIV_MASK;
}
if (div_factor == 0) {
- pr_err("invalid rate=%ld, parent_rate=%ld, div=%d: min divider valie is 1\n",
+ pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: min divider valie is 1\n",
rate, parent_rate, div_factor);
div_factor = 1;
@@ -559,6 +716,6 @@ U_BOOT_DRIVER(hsdk_cgu_clk) = {
.id = UCLASS_CLK,
.of_match = hsdk_cgu_clk_id,
.probe = hsdk_cgu_clk_probe,
- .platdata_auto_alloc_size = sizeof(struct hsdk_cgu_clk),
+ .priv_auto_alloc_size = sizeof(struct hsdk_cgu_clk),
.ops = &hsdk_cgu_ops,
};
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 83ba13374c..fbea72091b 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -13,11 +13,9 @@
#include <dt-structs.h>
#include <errno.h>
-DECLARE_GLOBAL_DATA_PTR;
-
-static inline struct clk_ops *clk_dev_ops(struct udevice *dev)
+static inline const struct clk_ops *clk_dev_ops(struct udevice *dev)
{
- return (struct clk_ops *)dev->driver->ops;
+ return (const struct clk_ops *)dev->driver->ops;
}
#if CONFIG_IS_ENABLED(OF_CONTROL)
@@ -60,7 +58,7 @@ int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
int ret;
struct ofnode_phandle_args args;
struct udevice *dev_clk;
- struct clk_ops *ops;
+ const struct clk_ops *ops;
debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
@@ -68,7 +66,7 @@ int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
clk->dev = NULL;
ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
- index, &args);
+ index, &args);
if (ret) {
debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
__func__, ret);
@@ -142,7 +140,7 @@ int clk_release_all(struct clk *clk, int count)
int clk_request(struct udevice *dev, struct clk *clk)
{
- struct clk_ops *ops = clk_dev_ops(dev);
+ const struct clk_ops *ops = clk_dev_ops(dev);
debug("%s(dev=%p, clk=%p)\n", __func__, dev, clk);
@@ -156,7 +154,7 @@ int clk_request(struct udevice *dev, struct clk *clk)
int clk_free(struct clk *clk)
{
- struct clk_ops *ops = clk_dev_ops(clk->dev);
+ const struct clk_ops *ops = clk_dev_ops(clk->dev);
debug("%s(clk=%p)\n", __func__, clk);
@@ -168,7 +166,7 @@ int clk_free(struct clk *clk)
ulong clk_get_rate(struct clk *clk)
{
- struct clk_ops *ops = clk_dev_ops(clk->dev);
+ const struct clk_ops *ops = clk_dev_ops(clk->dev);
debug("%s(clk=%p)\n", __func__, clk);
@@ -180,7 +178,7 @@ ulong clk_get_rate(struct clk *clk)
ulong clk_set_rate(struct clk *clk, ulong rate)
{
- struct clk_ops *ops = clk_dev_ops(clk->dev);
+ const struct clk_ops *ops = clk_dev_ops(clk->dev);
debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
@@ -192,7 +190,7 @@ ulong clk_set_rate(struct clk *clk, ulong rate)
int clk_enable(struct clk *clk)
{
- struct clk_ops *ops = clk_dev_ops(clk->dev);
+ const struct clk_ops *ops = clk_dev_ops(clk->dev);
debug("%s(clk=%p)\n", __func__, clk);
@@ -204,7 +202,7 @@ int clk_enable(struct clk *clk)
int clk_disable(struct clk *clk)
{
- struct clk_ops *ops = clk_dev_ops(clk->dev);
+ const struct clk_ops *ops = clk_dev_ops(clk->dev);
debug("%s(clk=%p)\n", __func__, clk);
diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c
index 63565b6ed8..c9a9f0a20b 100644
--- a/drivers/clk/clk_fixed_rate.c
+++ b/drivers/clk/clk_fixed_rate.c
@@ -8,8 +8,6 @@
#include <clk-uclass.h>
#include <dm.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct clk_fixed_rate {
unsigned long fixed_rate;
};
@@ -31,8 +29,8 @@ const struct clk_ops clk_fixed_rate_ops = {
static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- to_clk_fixed_rate(dev)->fixed_rate = dev_read_u32_default(dev,
- "clock-frequency", 0);
+ to_clk_fixed_rate(dev)->fixed_rate =
+ dev_read_u32_default(dev, "clock-frequency", 0);
#endif
return 0;
diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c
index 634f0717c6..63116e0bac 100644
--- a/drivers/clk/clk_stm32f.c
+++ b/drivers/clk/clk_stm32f.c
@@ -12,7 +12,6 @@
#include <asm/io.h>
#include <asm/arch/stm32.h>
-#include <asm/arch/stm32_periph.h>
#include <asm/arch/stm32_pwr.h>
#include <dt-bindings/mfd/stm32f7-rcc.h>
@@ -88,6 +87,12 @@
*/
#define RCC_APB2ENR_SYSCFGEN BIT(14)
+enum periph_clock {
+ SYSCFG_CLOCK_CFG,
+ TIMER2_CLOCK_CFG,
+ STMMAC_CLOCK_CFG,
+};
+
struct stm32_clk_info stm32f4_clk_info = {
/* 180 MHz */
.sys_pll_psc = {
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 9a46a7bbe5..144ac2a991 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -17,6 +17,7 @@
#include <dm/device.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
+#include <dm/of_access.h>
#include <dm/pinctrl.h>
#include <dm/platdata.h>
#include <dm/read.h>
@@ -703,8 +704,12 @@ int device_set_name(struct udevice *dev, const char *name)
bool device_is_compatible(struct udevice *dev, const char *compat)
{
const void *fdt = gd->fdt_blob;
+ ofnode node = dev_ofnode(dev);
- return !fdt_node_check_compatible(fdt, dev_of_offset(dev), compat);
+ if (ofnode_is_np(node))
+ return of_device_is_compatible(ofnode_to_np(node), compat, NULL, NULL);
+ else
+ return !fdt_node_check_compatible(fdt, ofnode_to_offset(node), compat);
}
bool of_machine_is_compatible(const char *compat)
diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
index 0030ab962e..98f4b539ea 100644
--- a/drivers/core/ofnode.c
+++ b/drivers/core/ofnode.c
@@ -205,8 +205,13 @@ fdt_addr_t ofnode_get_addr_index(ofnode node, int index)
&flags);
if (!prop_val)
return FDT_ADDR_T_NONE;
- na = of_n_addr_cells(ofnode_to_np(node));
- return of_read_number(prop_val, na);
+
+ if (IS_ENABLED(CONFIG_OF_TRANSLATE)) {
+ return of_translate_address(ofnode_to_np(node), prop_val);
+ } else {
+ na = of_n_addr_cells(ofnode_to_np(node));
+ return of_read_number(prop_val, na);
+ }
} else {
return fdt_get_base_address(gd->fdt_blob,
ofnode_to_offset(node));
@@ -296,7 +301,8 @@ int ofnode_parse_phandle_with_args(ofnode node, const char *list_name,
int ret;
ret = of_parse_phandle_with_args(ofnode_to_np(node),
- list_name, cells_name, index, &args);
+ list_name, cells_name, index,
+ &args);
if (ret)
return ret;
ofnode_from_of_phandle_args(&args, out_args);
@@ -305,8 +311,9 @@ int ofnode_parse_phandle_with_args(ofnode node, const char *list_name,
int ret;
ret = fdtdec_parse_phandle_with_args(gd->fdt_blob,
- ofnode_to_offset(node), list_name, cells_name,
- cell_count, index, &args);
+ ofnode_to_offset(node),
+ list_name, cells_name,
+ cell_count, index, &args);
if (ret)
return ret;
ofnode_from_fdtdec_phandle_args(&args, out_args);
@@ -534,10 +541,10 @@ int ofnode_read_pci_addr(ofnode node, enum fdt_pci_space type,
addr->phys_mid = fdt32_to_cpu(cell[1]);
addr->phys_lo = fdt32_to_cpu(cell[1]);
break;
- } else {
- cell += (FDT_PCI_ADDR_CELLS +
- FDT_PCI_SIZE_CELLS);
}
+
+ cell += (FDT_PCI_ADDR_CELLS +
+ FDT_PCI_SIZE_CELLS);
}
if (i == num) {
@@ -546,10 +553,10 @@ int ofnode_read_pci_addr(ofnode node, enum fdt_pci_space type,
}
return 0;
- } else {
- ret = -EINVAL;
}
+ ret = -EINVAL;
+
fail:
debug("(not found)\n");
return ret;
@@ -642,3 +649,11 @@ int ofnode_read_resource_byname(ofnode node, const char *name,
return ofnode_read_resource(node, index, res);
}
+
+u64 ofnode_translate_address(ofnode node, const fdt32_t *in_addr)
+{
+ if (ofnode_is_np(node))
+ return of_translate_address(ofnode_to_np(node), in_addr);
+ else
+ return fdt_translate_address(gd->fdt_blob, ofnode_to_offset(node), in_addr);
+}
diff --git a/drivers/core/read.c b/drivers/core/read.c
index 5d440cee72..601d1322d6 100644
--- a/drivers/core/read.c
+++ b/drivers/core/read.c
@@ -10,6 +10,11 @@
#include <mapmem.h>
#include <dm/of_access.h>
+int dev_read_u32(struct udevice *dev, const char *propname, u32 *outp)
+{
+ return ofnode_read_u32(dev_ofnode(dev), propname, outp);
+}
+
int dev_read_u32_default(struct udevice *dev, const char *propname, int def)
{
return ofnode_read_u32_default(dev_ofnode(dev), propname, def);
@@ -66,7 +71,7 @@ void *dev_read_addr_ptr(struct udevice *dev)
}
fdt_addr_t dev_read_addr_size(struct udevice *dev, const char *property,
- fdt_size_t *sizep)
+ fdt_size_t *sizep)
{
return ofnode_get_addr_size(dev_ofnode(dev), property, sizep);
}
@@ -77,7 +82,7 @@ const char *dev_read_name(struct udevice *dev)
}
int dev_read_stringlist_search(struct udevice *dev, const char *property,
- const char *string)
+ const char *string)
{
return ofnode_stringlist_search(dev_ofnode(dev), property, string);
}
@@ -94,15 +99,21 @@ int dev_read_string_count(struct udevice *dev, const char *propname)
}
int dev_read_phandle_with_args(struct udevice *dev, const char *list_name,
- const char *cells_name, int cell_count,
- int index,
- struct ofnode_phandle_args *out_args)
+ const char *cells_name, int cell_count,
+ int index, struct ofnode_phandle_args *out_args)
{
return ofnode_parse_phandle_with_args(dev_ofnode(dev), list_name,
cells_name, cell_count, index,
out_args);
}
+int dev_count_phandle_with_args(struct udevice *dev, const char *list_name,
+ const char *cells_name)
+{
+ return ofnode_count_phandle_with_args(dev_ofnode(dev), list_name,
+ cells_name);
+}
+
int dev_read_addr_cells(struct udevice *dev)
{
return ofnode_read_addr_cells(dev_ofnode(dev));
@@ -189,3 +200,8 @@ int dev_read_resource_byname(struct udevice *dev, const char *name,
{
return ofnode_read_resource_byname(dev_ofnode(dev), name, res);
}
+
+u64 dev_translate_address(struct udevice *dev, const fdt32_t *in_addr)
+{
+ return ofnode_translate_address(dev_ofnode(dev), in_addr);
+}
diff --git a/drivers/core/root.c b/drivers/core/root.c
index 976e2c4fdd..36336b65b6 100644
--- a/drivers/core/root.c
+++ b/drivers/core/root.c
@@ -266,6 +266,17 @@ static int dm_scan_fdt_node(struct udevice *parent, const void *blob,
for (offset = fdt_first_subnode(blob, offset);
offset > 0;
offset = fdt_next_subnode(blob, offset)) {
+ /* "chosen" node isn't a device itself but may contain some: */
+ if (!strcmp(fdt_get_name(blob, offset, NULL), "chosen")) {
+ pr_debug("parsing subnodes of \"chosen\"\n");
+
+ err = dm_scan_fdt_node(parent, blob, offset,
+ pre_reloc_only);
+ if (err && !ret)
+ ret = err;
+ continue;
+ }
+
if (pre_reloc_only &&
!dm_fdt_pre_reloc(blob, offset))
continue;
diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c
index a63eba389d..9373a39931 100644
--- a/drivers/crypto/fsl/fsl_hash.c
+++ b/drivers/crypto/fsl/fsl_hash.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <malloc.h>
+#include <memalign.h>
#include "jobdesc.h"
#include "desc.h"
#include "jr.h"
@@ -163,20 +164,37 @@ int caam_hash(const unsigned char *pbuf, unsigned int buf_len,
{
int ret = 0;
uint32_t *desc;
+ unsigned int size;
- desc = malloc(sizeof(int) * MAX_CAAM_DESCSIZE);
+ desc = malloc_cache_aligned(sizeof(int) * MAX_CAAM_DESCSIZE);
if (!desc) {
debug("Not enough memory for descriptor allocation\n");
return -ENOMEM;
}
+ if (!IS_ALIGNED((uintptr_t)pbuf, ARCH_DMA_MINALIGN) ||
+ !IS_ALIGNED((uintptr_t)pout, ARCH_DMA_MINALIGN)) {
+ puts("Error: Address arguments are not aligned\n");
+ return -EINVAL;
+ }
+
+ size = ALIGN(buf_len, ARCH_DMA_MINALIGN);
+ flush_dcache_range((unsigned long)pbuf, (unsigned long)pbuf + size);
+
inline_cnstr_jobdesc_hash(desc, pbuf, buf_len, pout,
driver_hash[algo].alg_type,
driver_hash[algo].digestsize,
0);
+ size = ALIGN(sizeof(int) * MAX_CAAM_DESCSIZE, ARCH_DMA_MINALIGN);
+ flush_dcache_range((unsigned long)desc, (unsigned long)desc + size);
+
ret = run_descriptor_jr(desc);
+ size = ALIGN(driver_hash[algo].digestsize, ARCH_DMA_MINALIGN);
+ invalidate_dcache_range((unsigned long)pout,
+ (unsigned long)pout + size);
+
free(desc);
return ret;
}
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index 058c9b9da8..b3a27ec5a8 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -95,6 +95,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
if (step == 2)
goto step2;
+ /* Set cdr1 first in case 0.9v VDD is enabled for some SoCs*/
+ ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
+
if (regs->ddr_eor)
ddr_out32(&ddr->eor, regs->ddr_eor);
@@ -183,7 +186,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4);
ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5);
ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6);
- ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
#ifdef CONFIG_DEEP_SLEEP
if (is_warm_boot()) {
ddr_out32(&ddr->sdram_cfg_2,
diff --git a/drivers/ddr/marvell/a38x/ddr3_init.h b/drivers/ddr/marvell/a38x/ddr3_init.h
index 8cb08864c2..a4c75a9fa6 100644
--- a/drivers/ddr/marvell/a38x/ddr3_init.h
+++ b/drivers/ddr/marvell/a38x/ddr3_init.h
@@ -183,7 +183,8 @@ extern u32 g_znodt_data;
extern u32 g_zpodt_ctrl;
extern u32 g_znodt_ctrl;
extern u32 g_dic;
-extern u32 g_odt_config;
+extern u32 g_odt_config_2cs;
+extern u32 g_odt_config_1cs;
extern u32 g_rtt_nom;
extern u8 debug_training_access;
diff --git a/drivers/ddr/marvell/a38x/ddr3_topology_def.h b/drivers/ddr/marvell/a38x/ddr3_topology_def.h
index 64a0447dd1..a17eca0418 100644
--- a/drivers/ddr/marvell/a38x/ddr3_topology_def.h
+++ b/drivers/ddr/marvell/a38x/ddr3_topology_def.h
@@ -70,7 +70,8 @@ enum speed_bin_table_elements {
SPEED_BIN_TWTR,
SPEED_BIN_TRTP,
SPEED_BIN_TWR,
- SPEED_BIN_TMOD
+ SPEED_BIN_TMOD,
+ SPEED_BIN_TXPDLL
};
#endif /* _DDR3_TOPOLOGY_DEF_H */
diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c
index e70ca4b425..ef471e565e 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training.c
@@ -22,6 +22,8 @@
#define GET_CS_FROM_MASK(mask) (cs_mask2_num[mask])
#define CS_CBE_VALUE(cs_num) (cs_cbe_reg[cs_num])
+#define TIMES_9_TREFI_CYCLES 0x8
+
u32 window_mem_addr = 0;
u32 phy_reg0_val = 0;
u32 phy_reg1_val = 8;
@@ -315,6 +317,7 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_
enum hws_access_type access_type = ACCESS_TYPE_UNICAST;
u32 data_read[MAX_INTERFACE_NUM];
struct hws_topology_map *tm = ddr3_get_topology_map();
+ u32 odt_config = g_odt_config_2cs;
DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
("Init_controller, do_mrs_phy=%d, is_ctrl64_bit=%d\n",
@@ -507,7 +510,9 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_
DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
("cl_value 0x%x cwl_val 0x%x\n",
cl_value, cwl_val));
-
+ t_wr = TIME_2_CLOCK_CYCLES(speed_bin_table(speed_bin_index,
+ SPEED_BIN_TWR),
+ t_ckclk);
data_value =
((cl_mask_table[cl_value] & 0x1) << 2) |
((cl_mask_table[cl_value] & 0xe) << 3);
@@ -517,8 +522,9 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_
(0x7 << 4) | (1 << 2)));
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
- MR0_REG, twr_mask_table[t_wr + 1],
- 0xe00));
+ MR0_REG, twr_mask_table[t_wr + 1] << 9,
+ (0x7 << 9)));
+
/*
* MR1: Set RTT and DIC Design GL values
@@ -570,6 +576,9 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_
DUNIT_CONTROL_HIGH_REG,
(init_cntr_prm->msys_init << 7), (1 << 7)));
+ /* calculate number of CS (per interface) */
+ CHECK_STATUS(calc_cs_num
+ (dev_num, if_id, &cs_num));
timing = tm->interface_params[if_id].timing;
if (mode2_t != 0xff) {
@@ -578,9 +587,6 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_
/* Board topology map is forcing timing */
t2t = (timing == HWS_TIM_2T) ? 1 : 0;
} else {
- /* calculate number of CS (per interface) */
- CHECK_STATUS(calc_cs_num
- (dev_num, if_id, &cs_num));
t2t = (cs_num == 1) ? 0 : 1;
}
@@ -589,16 +595,15 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_
DDR_CONTROL_LOW_REG, t2t << 3,
0x3 << 3));
/* move the block to ddr3_tip_set_timing - start */
- t_pd = GET_MAX_VALUE(t_ckclk * 3,
- speed_bin_table(speed_bin_index,
- SPEED_BIN_TPD));
- t_pd = TIME_2_CLOCK_CYCLES(t_pd, t_ckclk);
- txpdll = GET_MAX_VALUE(t_ckclk * 10, 24);
+ t_pd = TIMES_9_TREFI_CYCLES;
+ txpdll = GET_MAX_VALUE(t_ckclk * 10,
+ speed_bin_table(speed_bin_index,
+ SPEED_BIN_TXPDLL));
txpdll = CEIL_DIVIDE((txpdll - 1), t_ckclk);
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
- DDR_TIMING_REG, txpdll << 4,
- 0x1f << 4));
+ DDR_TIMING_REG, txpdll << 4 | t_pd,
+ 0x1f << 4 | 0xf));
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
DDR_TIMING_REG, 0x28 << 9, 0x3f << 9));
@@ -623,9 +628,11 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_
(1 << 11)));
/* Set Active control for ODT write transactions */
+ if (cs_num == 1)
+ odt_config = g_odt_config_1cs;
CHECK_STATUS(ddr3_tip_if_write
(dev_num, ACCESS_TYPE_MULTICAST,
- PARAM_NOT_CARE, 0x1494, g_odt_config,
+ PARAM_NOT_CARE, 0x1494, odt_config,
MASK_ALL_BITS));
}
} else {
@@ -1224,6 +1231,7 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type,
u32 cl_value = 0, cwl_value = 0, mem_mask = 0, val = 0,
bus_cnt = 0, t_hclk = 0, t_wr = 0,
refresh_interval_cnt = 0, cnt_id;
+ u32 t_ckclk;
u32 t_refi = 0, end_if, start_if;
u32 bus_index = 0;
int is_dll_off = 0;
@@ -1372,7 +1380,7 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type,
/* adjust t_refi to new frequency */
t_refi = (tm->interface_params[if_id].interface_temp ==
- HWS_TEMP_HIGH) ? TREFI_LOW : TREFI_HIGH;
+ HWS_TEMP_HIGH) ? TREFI_HIGH : TREFI_LOW;
t_refi *= 1000; /*psec */
/* HCLK in[ps] */
@@ -1390,8 +1398,12 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type,
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id, DFS_REG,
(cwl_mask_table[cwl_value] << 12), 0x7000));
- t_wr = speed_bin_table(speed_bin_index, SPEED_BIN_TWR);
- t_wr = (t_wr / 1000);
+
+ t_ckclk = MEGA / freq_val[frequency];
+ t_wr = TIME_2_CLOCK_CYCLES(speed_bin_table(speed_bin_index,
+ SPEED_BIN_TWR),
+ t_ckclk);
+
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id, DFS_REG,
(twr_mask_table[t_wr + 1] << 16), 0x70000));
@@ -1539,7 +1551,7 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type,
CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
if_id, ODT_TIMING_LOW,
val, 0xffff0));
- val = 0x71 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12);
+ val = 0x91 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12);
CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
if_id, ODT_TIMING_HI_REG,
val, 0xffff));
@@ -1591,7 +1603,7 @@ static int ddr3_tip_write_odt(u32 dev_num, enum hws_access_type access_type,
CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
ODT_TIMING_LOW, val, 0xffff0));
- val = 0x71 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12);
+ val = 0x91 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12);
CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
ODT_TIMING_HI_REG, val, 0xffff));
if (odt_additional == 1) {
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_db.c b/drivers/ddr/marvell/a38x/ddr3_training_db.c
index 861dfb19c3..0e11b434ab 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_db.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_db.c
@@ -152,18 +152,18 @@ u8 twr_mask_table[] = {
10,
10,
10,
- 1, /*5 */
- 2, /*6 */
- 3, /*7 */
+ 1, /*5*/
+ 2, /*6*/
+ 3, /*7*/
+ 4, /*8*/
10,
+ 5, /*10*/
10,
- 5, /*10 */
+ 6, /*12*/
10,
- 6, /*12 */
+ 7, /*14*/
10,
- 7, /*14 */
- 10,
- 0 /*16 */
+ 0 /*16*/
};
u8 cl_mask_table[] = {
@@ -431,6 +431,9 @@ u32 speed_bin_table(u8 index, enum speed_bin_table_elements element)
case SPEED_BIN_TMOD:
result = 15000;
break;
+ case SPEED_BIN_TXPDLL:
+ result = 24000;
+ break;
default:
break;
}
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c
index 56fce174d4..1fc173b600 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c
@@ -17,7 +17,7 @@
#define VREF_MAX_INDEX 7
#define MAX_VALUE (1024 - 1)
#define MIN_VALUE (-MAX_VALUE)
-#define GET_RD_SAMPLE_DELAY(data, cs) ((data >> rd_sample_mask[cs]) & 0xf)
+#define GET_RD_SAMPLE_DELAY(data, cs) ((data >> rd_sample_mask[cs]) & 0x1f)
u32 ck_delay = (u32)-1, ck_delay_16 = (u32)-1;
u32 ca_delay;
@@ -49,7 +49,7 @@ static u32 rd_sample_mask[] = {
*/
int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id)
{
- u32 cs_num = 0, max_read_sample = 0, min_read_sample = 0;
+ u32 cs_num = 0, max_cs = 0, max_read_sample = 0, min_read_sample = 0x1f;
u32 data_read[MAX_INTERFACE_NUM] = { 0 };
u32 read_sample[MAX_CS_NUM];
u32 val;
@@ -66,15 +66,19 @@ int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id)
data_read, MASK_ALL_BITS));
val = data_read[if_id];
- for (cs_num = 0; cs_num < MAX_CS_NUM; cs_num++) {
+ max_cs = hws_ddr3_tip_max_cs_get();
+
+ for (cs_num = 0; cs_num < max_cs; cs_num++) {
read_sample[cs_num] = GET_RD_SAMPLE_DELAY(val, cs_num);
/* find maximum of read_samples */
if (read_sample[cs_num] >= max_read_sample) {
- if (read_sample[cs_num] == max_read_sample)
- max_phase = MIN_VALUE;
- else
+ if (read_sample[cs_num] == max_read_sample) {
+ /* search for max phase */;
+ } else {
max_read_sample = read_sample[cs_num];
+ max_phase = MIN_VALUE;
+ }
for (pup_index = 0;
pup_index < tm->num_of_bus_per_interface;
@@ -97,10 +101,12 @@ int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id)
min_read_sample = read_sample[cs_num];
}
+ if (min_read_sample <= tm->interface_params[if_id].cas_l) {
+ min_read_sample = (int)tm->interface_params[if_id].cas_l;
+ }
+
min_read_sample = min_read_sample - 1;
max_read_sample = max_read_sample + 4 + (max_phase + 1) / 2 + 1;
- if (min_read_sample >= 0xf)
- min_read_sample = 0xf;
if (max_read_sample >= 0x1f)
max_read_sample = 0x1f;
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_static.c b/drivers/ddr/marvell/a38x/ddr3_training_static.c
index 5101f3f383..b73bbf4f1b 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_static.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_static.c
@@ -21,7 +21,8 @@ u32 g_zpodt_data = 45; /* controller data - P ODT */
u32 g_znodt_data = 45; /* controller data - N ODT */
u32 g_zpodt_ctrl = 45; /* controller data - P ODT */
u32 g_znodt_ctrl = 45; /* controller data - N ODT */
-u32 g_odt_config = 0x120012;
+u32 g_odt_config_2cs = 0x120012;
+u32 g_odt_config_1cs = 0x10000;
u32 g_rtt_nom = 0x44;
u32 g_dic = 0x2;
diff --git a/drivers/dma/ti-edma3.c b/drivers/dma/ti-edma3.c
index 635eb7876d..852c9e1fd7 100644
--- a/drivers/dma/ti-edma3.c
+++ b/drivers/dma/ti-edma3.c
@@ -34,10 +34,14 @@
#define EDMA3_QEESR 0x108c
#define EDMA3_QSECR 0x1094
+#define EDMA_FILL_BUFFER_SIZE 512
+
struct ti_edma3_priv {
u32 base;
};
+static u8 edma_fill_buffer[EDMA_FILL_BUFFER_SIZE] __aligned(ARCH_DMA_MINALIGN);
+
/**
* qedma3_start - start qdma on a channel
* @base: base address of edma
@@ -391,7 +395,7 @@ void qedma3_stop(u32 base, struct edma3_channel_config *cfg)
}
void __edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num,
- void *dst, void *src, size_t len)
+ void *dst, void *src, size_t len, size_t s_len)
{
struct edma3_slot_config slot;
struct edma3_channel_config edma_channel;
@@ -401,7 +405,11 @@ void __edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num,
unsigned int addr = (unsigned int) (dst);
unsigned int max_acnt = 0x7FFFU;
- if (len > max_acnt) {
+ if (len > s_len) {
+ b_cnt_value = (len / s_len);
+ rem_bytes = (len % s_len);
+ a_cnt_value = s_len;
+ } else if (len > max_acnt) {
b_cnt_value = (len / max_acnt);
rem_bytes = (len % max_acnt);
a_cnt_value = max_acnt;
@@ -412,7 +420,10 @@ void __edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num,
slot.acnt = a_cnt_value;
slot.bcnt = b_cnt_value;
slot.ccnt = 1;
- slot.src_bidx = a_cnt_value;
+ if (len == s_len)
+ slot.src_bidx = a_cnt_value;
+ else
+ slot.src_bidx = 0;
slot.dst_bidx = a_cnt_value;
slot.src_cidx = 0;
slot.dst_cidx = 0;
@@ -438,8 +449,11 @@ void __edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num,
if (rem_bytes != 0) {
slot.opt = 0;
- slot.src =
- (b_cnt_value * max_acnt) + ((unsigned int) src);
+ if (len == s_len)
+ slot.src =
+ (b_cnt_value * max_acnt) + ((unsigned int) src);
+ else
+ slot.src = (unsigned int) src;
slot.acnt = rem_bytes;
slot.bcnt = 1;
slot.ccnt = 1;
@@ -468,12 +482,39 @@ void __edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num,
}
}
+void __edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num,
+ void *dst, u8 val, size_t len)
+{
+ int xfer_len;
+ int max_xfer = EDMA_FILL_BUFFER_SIZE * 65535;
+
+ memset((void *)edma_fill_buffer, val, sizeof(edma_fill_buffer));
+
+ while (len) {
+ xfer_len = len;
+ if (xfer_len > max_xfer)
+ xfer_len = max_xfer;
+
+ __edma3_transfer(edma3_base_addr, edma_slot_num, dst,
+ edma_fill_buffer, xfer_len,
+ EDMA_FILL_BUFFER_SIZE);
+ len -= xfer_len;
+ dst += xfer_len;
+ }
+}
+
#ifndef CONFIG_DMA
void edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num,
void *dst, void *src, size_t len)
{
- __edma3_transfer(edma3_base_addr, edma_slot_num, dst, src, len);
+ __edma3_transfer(edma3_base_addr, edma_slot_num, dst, src, len, len);
+}
+
+void edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num,
+ void *dst, u8 val, size_t len)
+{
+ __edma3_fill(edma3_base_addr, edma_slot_num, dst, val, len);
}
#else
@@ -488,7 +529,7 @@ static int ti_edma3_transfer(struct udevice *dev, int direction, void *dst,
switch (direction) {
case DMA_MEM_TO_MEM:
- __edma3_transfer(priv->base, 1, dst, src, len);
+ __edma3_transfer(priv->base, 1, dst, src, len, len);
break;
default:
pr_err("Transfer type not implemented in DMA driver\n");
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 201d7bfff9..8525679091 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -48,7 +48,6 @@ obj-$(CONFIG_ADI_GPIO2) += adi_gpio2.o
obj-$(CONFIG_TCA642X) += tca642x.o
obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o
obj-$(CONFIG_LPC32XX_GPIO) += lpc32xx_gpio.o
-obj-$(CONFIG_STM32_GPIO) += stm32_gpio.o
obj-$(CONFIG_STM32F7_GPIO) += stm32f7_gpio.o
obj-$(CONFIG_GPIO_UNIPHIER) += gpio-uniphier.o
obj-$(CONFIG_ZYNQ_GPIO) += zynq_gpio.o
diff --git a/drivers/gpio/pca953x.c b/drivers/gpio/pca953x.c
index d1c1ae1411..10a105df94 100644
--- a/drivers/gpio/pca953x.c
+++ b/drivers/gpio/pca953x.c
@@ -142,7 +142,7 @@ int pca953x_get_val(uint8_t chip)
return (int)val;
}
-#ifdef CONFIG_CMD_PCA953X
+#if defined(CONFIG_CMD_PCA953X) && !defined(CONFIG_SPL_BUILD)
/*
* Display pca953x information
*/
@@ -193,7 +193,7 @@ static int pca953x_info(uint8_t chip)
return 0;
}
-cmd_tbl_t cmd_pca953x[] = {
+static cmd_tbl_t cmd_pca953x[] = {
U_BOOT_CMD_MKENT(device, 3, 0, (void *)PCA953X_CMD_DEVICE, "", ""),
U_BOOT_CMD_MKENT(output, 4, 0, (void *)PCA953X_CMD_OUTPUT, "", ""),
U_BOOT_CMD_MKENT(input, 3, 0, (void *)PCA953X_CMD_INPUT, "", ""),
@@ -201,7 +201,7 @@ cmd_tbl_t cmd_pca953x[] = {
U_BOOT_CMD_MKENT(info, 2, 0, (void *)PCA953X_CMD_INFO, "", ""),
};
-int do_pca953x(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_pca953x(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
static uint8_t chip = CONFIG_SYS_I2C_PCA953X_ADDR;
int ret = CMD_RET_USAGE, val;
diff --git a/drivers/gpio/pm8916_gpio.c b/drivers/gpio/pm8916_gpio.c
index 9ec2a24b3e..42f068ecb6 100644
--- a/drivers/gpio/pm8916_gpio.c
+++ b/drivers/gpio/pm8916_gpio.c
@@ -29,7 +29,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define REG_STATUS_VAL_MASK 0x1
/* MODE_CTL */
-#define REG_CTL 0x40
+#define REG_CTL 0x40
#define REG_CTL_MODE_MASK 0x70
#define REG_CTL_MODE_INPUT 0x00
#define REG_CTL_MODE_INOUT 0x20
@@ -183,7 +183,7 @@ static int pm8916_gpio_probe(struct udevice *dev)
return -ENODEV;
reg = pmic_reg_read(dev->parent, priv->pid + REG_SUBTYPE);
- if (reg != 0x5)
+ if (reg != 0x5 && reg != 0x1)
return -ENODEV;
return 0;
@@ -203,6 +203,7 @@ static int pm8916_gpio_ofdata_to_platdata(struct udevice *dev)
static const struct udevice_id pm8916_gpio_ids[] = {
{ .compatible = "qcom,pm8916-gpio" },
+ { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */
{ }
};
@@ -278,6 +279,7 @@ static int pm8941_pwrkey_ofdata_to_platdata(struct udevice *dev)
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
uc_priv->gpio_count = 2;
+ uc_priv->bank_name = dev_read_string(dev, "gpio-bank-name");
if (uc_priv->bank_name == NULL)
uc_priv->bank_name = "pm8916_key";
@@ -286,6 +288,7 @@ static int pm8941_pwrkey_ofdata_to_platdata(struct udevice *dev)
static const struct udevice_id pm8941_pwrkey_ids[] = {
{ .compatible = "qcom,pm8916-pwrkey" },
+ { .compatible = "qcom,pm8994-pwrkey" },
{ }
};
diff --git a/drivers/gpio/stm32_gpio.c b/drivers/gpio/stm32_gpio.c
deleted file mode 100644
index c04cef4cb9..0000000000
--- a/drivers/gpio/stm32_gpio.c
+++ /dev/null
@@ -1,182 +0,0 @@
-/*
- * (C) Copyright 2011
- * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
- *
- * (C) Copyright 2015
- * Kamil Lulko, <kamil.lulko@gmail.com>
- *
- * Copyright 2015 ATS Advanced Telematics Systems GmbH
- * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <linux/errno.h>
-#include <asm/arch/stm32.h>
-#include <asm/arch/gpio.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static const unsigned long io_base[] = {
- STM32_GPIOA_BASE, STM32_GPIOB_BASE, STM32_GPIOC_BASE,
- STM32_GPIOD_BASE, STM32_GPIOE_BASE, STM32_GPIOF_BASE,
- STM32_GPIOG_BASE, STM32_GPIOH_BASE, STM32_GPIOI_BASE
-};
-
-struct stm32_gpio_regs {
- u32 moder; /* GPIO port mode */
- u32 otyper; /* GPIO port output type */
- u32 ospeedr; /* GPIO port output speed */
- u32 pupdr; /* GPIO port pull-up/pull-down */
- u32 idr; /* GPIO port input data */
- u32 odr; /* GPIO port output data */
- u32 bsrr; /* GPIO port bit set/reset */
- u32 lckr; /* GPIO port configuration lock */
- u32 afr[2]; /* GPIO alternate function */
-};
-
-#define CHECK_DSC(x) (!x || x->port > 8 || x->pin > 15)
-#define CHECK_CTL(x) (!x || x->af > 15 || x->mode > 3 || x->otype > 1 || \
- x->pupd > 2 || x->speed > 3)
-
-int stm32_gpio_config(const struct stm32_gpio_dsc *dsc,
- const struct stm32_gpio_ctl *ctl)
-{
- struct stm32_gpio_regs *gpio_regs;
- u32 i;
- int rv;
-
- if (CHECK_DSC(dsc)) {
- rv = -EINVAL;
- goto out;
- }
- if (CHECK_CTL(ctl)) {
- rv = -EINVAL;
- goto out;
- }
-
- gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
-
- i = (dsc->pin & 0x07) * 4;
- clrsetbits_le32(&gpio_regs->afr[dsc->pin >> 3], 0xF << i, ctl->af << i);
-
- i = dsc->pin * 2;
-
- clrsetbits_le32(&gpio_regs->moder, 0x3 << i, ctl->mode << i);
- clrsetbits_le32(&gpio_regs->otyper, 0x3 << i, ctl->otype << i);
- clrsetbits_le32(&gpio_regs->ospeedr, 0x3 << i, ctl->speed << i);
- clrsetbits_le32(&gpio_regs->pupdr, 0x3 << i, ctl->pupd << i);
-
- rv = 0;
-out:
- return rv;
-}
-
-int stm32_gpout_set(const struct stm32_gpio_dsc *dsc, int state)
-{
- struct stm32_gpio_regs *gpio_regs;
- int rv;
-
- if (CHECK_DSC(dsc)) {
- rv = -EINVAL;
- goto out;
- }
-
- gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
-
- if (state)
- writel(1 << dsc->pin, &gpio_regs->bsrr);
- else
- writel(1 << (dsc->pin + 16), &gpio_regs->bsrr);
-
- rv = 0;
-out:
- return rv;
-}
-
-int stm32_gpin_get(const struct stm32_gpio_dsc *dsc)
-{
- struct stm32_gpio_regs *gpio_regs;
- int rv;
-
- if (CHECK_DSC(dsc)) {
- rv = -EINVAL;
- goto out;
- }
-
- gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
- rv = readl(&gpio_regs->idr) & (1 << dsc->pin);
-out:
- return rv;
-}
-
-/* Common GPIO API */
-
-int gpio_request(unsigned gpio, const char *label)
-{
- return 0;
-}
-
-int gpio_free(unsigned gpio)
-{
- return 0;
-}
-
-int gpio_direction_input(unsigned gpio)
-{
- struct stm32_gpio_dsc dsc;
- struct stm32_gpio_ctl ctl;
-
- dsc.port = stm32_gpio_to_port(gpio);
- dsc.pin = stm32_gpio_to_pin(gpio);
- ctl.af = STM32_GPIO_AF0;
- ctl.mode = STM32_GPIO_MODE_IN;
- ctl.otype = STM32_GPIO_OTYPE_PP;
- ctl.pupd = STM32_GPIO_PUPD_NO;
- ctl.speed = STM32_GPIO_SPEED_50M;
-
- return stm32_gpio_config(&dsc, &ctl);
-}
-
-int gpio_direction_output(unsigned gpio, int value)
-{
- struct stm32_gpio_dsc dsc;
- struct stm32_gpio_ctl ctl;
- int res;
-
- dsc.port = stm32_gpio_to_port(gpio);
- dsc.pin = stm32_gpio_to_pin(gpio);
- ctl.af = STM32_GPIO_AF0;
- ctl.mode = STM32_GPIO_MODE_OUT;
- ctl.pupd = STM32_GPIO_PUPD_NO;
- ctl.speed = STM32_GPIO_SPEED_50M;
-
- res = stm32_gpio_config(&dsc, &ctl);
- if (res < 0)
- goto out;
- res = stm32_gpout_set(&dsc, value);
-out:
- return res;
-}
-
-int gpio_get_value(unsigned gpio)
-{
- struct stm32_gpio_dsc dsc;
-
- dsc.port = stm32_gpio_to_port(gpio);
- dsc.pin = stm32_gpio_to_pin(gpio);
-
- return stm32_gpin_get(&dsc);
-}
-
-int gpio_set_value(unsigned gpio, int value)
-{
- struct stm32_gpio_dsc dsc;
-
- dsc.port = stm32_gpio_to_port(gpio);
- dsc.pin = stm32_gpio_to_pin(gpio);
-
- return stm32_gpout_set(&dsc, value);
-}
diff --git a/drivers/gpio/tca642x.c b/drivers/gpio/tca642x.c
index 6386835d5d..730460a999 100644
--- a/drivers/gpio/tca642x.c
+++ b/drivers/gpio/tca642x.c
@@ -163,7 +163,7 @@ int tca642x_set_inital_state(uchar chip, struct tca642x_bank_info init_data[])
return ret;
}
-#ifdef CONFIG_CMD_TCA642X
+#if defined(CONFIG_CMD_TCA642X) && !defined(CONFIG_SPL_BUILD)
/*
* Display tca642x information
*/
@@ -212,7 +212,7 @@ static int tca642x_info(uchar chip)
return 0;
}
-cmd_tbl_t cmd_tca642x[] = {
+static cmd_tbl_t cmd_tca642x[] = {
U_BOOT_CMD_MKENT(device, 3, 0, (void *)TCA642X_CMD_DEVICE, "", ""),
U_BOOT_CMD_MKENT(output, 4, 0, (void *)TCA642X_CMD_OUTPUT, "", ""),
U_BOOT_CMD_MKENT(input, 3, 0, (void *)TCA642X_CMD_INPUT, "", ""),
@@ -220,7 +220,7 @@ cmd_tbl_t cmd_tca642x[] = {
U_BOOT_CMD_MKENT(info, 2, 0, (void *)TCA642X_CMD_INFO, "", ""),
};
-int do_tca642x(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_tca642x(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
static uchar chip = CONFIG_SYS_I2C_TCA642X_ADDR;
int ret = CMD_RET_USAGE, val;
diff --git a/drivers/i2c/imx_lpi2c.c b/drivers/i2c/imx_lpi2c.c
index e7ec17fe9e..de74e89efd 100644
--- a/drivers/i2c/imx_lpi2c.c
+++ b/drivers/i2c/imx_lpi2c.c
@@ -258,7 +258,7 @@ static int bus_i2c_set_bus_speed(struct udevice *bus, int speed)
int i;
regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
- clock_rate = imx_get_i2cclk(bus->seq + 4);
+ clock_rate = imx_get_i2cclk(bus->seq);
if (!clock_rate)
return -EPERM;
@@ -419,14 +419,14 @@ static int imx_lpi2c_probe(struct udevice *bus)
i2c_bus->bus = bus;
/* power up i2c resource */
- ret = init_i2c_power(bus->seq + 4);
+ ret = init_i2c_power(bus->seq);
if (ret) {
debug("init_i2c_power err = %d\n", ret);
return ret;
}
- /* Enable clk, only i2c4-7 can be handled by A7 core */
- ret = enable_i2c_clk(1, bus->seq + 4);
+ /* To i.MX7ULP, only i2c4-7 can be handled by A7 core */
+ ret = enable_i2c_clk(1, bus->seq);
if (ret < 0)
return ret;
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 205274e947..79228c2757 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -784,9 +784,9 @@ static int mxc_i2c_probe(struct udevice *bus)
ret2 = gpio_request_by_name_nodev(offset_to_ofnode(node),
"sda-gpios", 0, &i2c_bus->sda_gpio,
GPIOD_IS_OUT);
- if (!dm_gpio_is_valid(&i2c_bus->sda_gpio) |
- !dm_gpio_is_valid(&i2c_bus->scl_gpio) |
- ret | ret2) {
+ if (!dm_gpio_is_valid(&i2c_bus->sda_gpio) ||
+ !dm_gpio_is_valid(&i2c_bus->scl_gpio) ||
+ ret || ret2) {
dev_err(dev, "i2c bus %d at %lu, fail to request scl/sda gpio\n", bus->seq, i2c_bus->base);
return -EINVAL;
}
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index ada7624417..e8d598cd47 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -53,3 +53,4 @@ obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o
obj-$(CONFIG_QFW) += qfw.o
obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o
obj-$(CONFIG_STM32_RCC) += stm32_rcc.o
+obj-$(CONFIG_SYS_DPAA_QBMAN) += fsl_portals.o
diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c
new file mode 100644
index 0000000000..3b3dd023bb
--- /dev/null
+++ b/drivers/misc/fsl_portals.c
@@ -0,0 +1,305 @@
+/*
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#include <asm/processor.h>
+#include <asm/io.h>
+#ifdef CONFIG_PPC
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#endif
+#include <fsl_qbman.h>
+
+#define MAX_BPORTALS (CONFIG_SYS_BMAN_CINH_SIZE / CONFIG_SYS_BMAN_SP_CINH_SIZE)
+#define MAX_QPORTALS (CONFIG_SYS_QMAN_CINH_SIZE / CONFIG_SYS_QMAN_SP_CINH_SIZE)
+void setup_qbman_portals(void)
+{
+ void __iomem *bpaddr = (void *)CONFIG_SYS_BMAN_CINH_BASE +
+ CONFIG_SYS_BMAN_SWP_ISDR_REG;
+ void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE +
+ CONFIG_SYS_QMAN_SWP_ISDR_REG;
+#ifdef CONFIG_PPC
+ struct ccsr_qman *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
+
+ /* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */
+#ifdef CONFIG_PHYS_64BIT
+ out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
+#endif
+ out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS);
+#endif
+#ifdef CONFIG_FSL_CORENET
+ int i;
+
+ for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
+ u8 sdest = qp_info[i].sdest;
+ u16 fliodn = qp_info[i].fliodn;
+ u16 dliodn = qp_info[i].dliodn;
+ u16 liodn_off = qp_info[i].liodn_offset;
+
+ out_be32(&qman->qcsp[i].qcsp_lio_cfg, (liodn_off << 16) |
+ dliodn);
+ /* set frame liodn */
+ out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | fliodn);
+ }
+#endif
+
+ /* Change default state of BMan ISDR portals to all 1s */
+ inhibit_portals(bpaddr, CONFIG_SYS_BMAN_NUM_PORTALS, MAX_BPORTALS,
+ CONFIG_SYS_BMAN_SP_CINH_SIZE);
+ inhibit_portals(qpaddr, CONFIG_SYS_QMAN_NUM_PORTALS, MAX_QPORTALS,
+ CONFIG_SYS_QMAN_SP_CINH_SIZE);
+}
+
+void inhibit_portals(void __iomem *addr, int max_portals,
+ int arch_max_portals, int portal_cinh_size)
+{
+ u32 val;
+ int i;
+
+ /* arch_max_portals is the maximum based on memory size. This includes
+ * the reserved memory in the SoC. max_portals the number of physical
+ * portals in the SoC
+ */
+ if (max_portals > arch_max_portals) {
+ printf("ERROR: portal config error\n");
+ max_portals = arch_max_portals;
+ }
+
+ for (i = 0; i < max_portals; i++) {
+ out_be32(addr, -1);
+ val = in_be32(addr);
+ if (!val) {
+ printf("ERROR: Stopped after %d portals\n", i);
+ return;
+ }
+ addr += portal_cinh_size;
+ }
+ debug("Cleared %d portals\n", i);
+}
+
+#ifdef CONFIG_PPC
+static int fdt_qportal(void *blob, int off, int id, char *name,
+ enum fsl_dpaa_dev dev, int create)
+{
+ int childoff, dev_off, ret = 0;
+ u32 dev_handle;
+#ifdef CONFIG_FSL_CORENET
+ int num;
+ u32 liodns[2];
+#endif
+
+ childoff = fdt_subnode_offset(blob, off, name);
+ if (create) {
+ char handle[64], *p;
+
+ strncpy(handle, name, sizeof(handle));
+ p = strchr(handle, '@');
+ if (!strncmp(name, "fman", 4)) {
+ *p = *(p + 1);
+ p++;
+ }
+ *p = '\0';
+
+ dev_off = fdt_path_offset(blob, handle);
+ /* skip this node if alias is not found */
+ if (dev_off == -FDT_ERR_BADPATH)
+ return 0;
+ if (dev_off < 0)
+ return dev_off;
+
+ if (childoff <= 0)
+ childoff = fdt_add_subnode(blob, off, name);
+
+ /* need to update the dev_off after adding a subnode */
+ dev_off = fdt_path_offset(blob, handle);
+ if (dev_off < 0)
+ return dev_off;
+
+ if (childoff > 0) {
+ dev_handle = fdt_get_phandle(blob, dev_off);
+ if (dev_handle <= 0) {
+ dev_handle = fdt_alloc_phandle(blob);
+ ret = fdt_set_phandle(blob, dev_off,
+ dev_handle);
+ if (ret < 0)
+ return ret;
+ }
+
+ ret = fdt_setprop(blob, childoff, "dev-handle",
+ &dev_handle, sizeof(dev_handle));
+ if (ret < 0)
+ return ret;
+
+#ifdef CONFIG_FSL_CORENET
+ num = get_dpaa_liodn(dev, &liodns[0], id);
+ ret = fdt_setprop(blob, childoff, "fsl,liodn",
+ &liodns[0], sizeof(u32) * num);
+ if (!strncmp(name, "pme", 3)) {
+ u32 pme_rev1, pme_rev2;
+ ccsr_pme_t *pme_regs =
+ (void *)CONFIG_SYS_FSL_CORENET_PME_ADDR;
+
+ pme_rev1 = in_be32(&pme_regs->pm_ip_rev_1);
+ pme_rev2 = in_be32(&pme_regs->pm_ip_rev_2);
+ ret = fdt_setprop(blob, childoff,
+ "fsl,pme-rev1", &pme_rev1,
+ sizeof(u32));
+ if (ret < 0)
+ return ret;
+ ret = fdt_setprop(blob, childoff,
+ "fsl,pme-rev2", &pme_rev2,
+ sizeof(u32));
+ }
+#endif
+ } else {
+ return childoff;
+ }
+ } else {
+ if (childoff > 0)
+ ret = fdt_del_node(blob, childoff);
+ }
+
+ return ret;
+}
+#endif /* CONFIG_PPC */
+
+void fdt_fixup_qportals(void *blob)
+{
+ int off, err;
+ unsigned int maj, min;
+ unsigned int ip_cfg;
+ struct ccsr_qman *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
+ u32 rev_1 = in_be32(&qman->ip_rev_1);
+ u32 rev_2 = in_be32(&qman->ip_rev_2);
+ char compat[64];
+ int compat_len;
+
+ maj = (rev_1 >> 8) & 0xff;
+ min = rev_1 & 0xff;
+ ip_cfg = rev_2 & 0xff;
+
+ compat_len = sprintf(compat, "fsl,qman-portal-%u.%u.%u",
+ maj, min, ip_cfg) + 1;
+ compat_len += sprintf(compat + compat_len, "fsl,qman-portal") + 1;
+
+ off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal");
+ while (off != -FDT_ERR_NOTFOUND) {
+#ifdef CONFIG_PPC
+#ifdef CONFIG_FSL_CORENET
+ u32 liodns[2];
+#endif
+ const int *ci = fdt_getprop(blob, off, "cell-index", &err);
+ int i;
+
+ if (!ci)
+ goto err;
+
+ i = *ci;
+#ifdef CONFIG_SYS_DPAA_FMAN
+ int j;
+#endif
+
+#endif /* CONFIG_PPC */
+ err = fdt_setprop(blob, off, "compatible", compat, compat_len);
+ if (err < 0)
+ goto err;
+#ifdef CONFIG_PPC
+#ifdef CONFIG_FSL_CORENET
+ liodns[0] = qp_info[i].dliodn;
+ liodns[1] = qp_info[i].fliodn;
+ err = fdt_setprop(blob, off, "fsl,liodn",
+ &liodns, sizeof(u32) * 2);
+ if (err < 0)
+ goto err;
+#endif
+
+ i++;
+
+ err = fdt_qportal(blob, off, i, "crypto@0", FSL_HW_PORTAL_SEC,
+ IS_E_PROCESSOR(get_svr()));
+ if (err < 0)
+ goto err;
+
+#ifdef CONFIG_FSL_CORENET
+#ifdef CONFIG_SYS_DPAA_PME
+ err = fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 1);
+ if (err < 0)
+ goto err;
+#else
+ fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 0);
+#endif
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) {
+ char name[] = "fman@0";
+
+ name[sizeof(name) - 2] = '0' + j;
+ err = fdt_qportal(blob, off, i, name,
+ FSL_HW_PORTAL_FMAN1 + j, 1);
+ if (err < 0)
+ goto err;
+ }
+#endif
+#ifdef CONFIG_SYS_DPAA_RMAN
+ err = fdt_qportal(blob, off, i, "rman@0",
+ FSL_HW_PORTAL_RMAN, 1);
+ if (err < 0)
+ goto err;
+#endif
+#endif /* CONFIG_PPC */
+
+err:
+ if (err < 0) {
+ printf("ERROR: unable to create props for %s: %s\n",
+ fdt_get_name(blob, off, NULL),
+ fdt_strerror(err));
+ return;
+ }
+
+ off = fdt_node_offset_by_compatible(blob, off,
+ "fsl,qman-portal");
+ }
+}
+
+void fdt_fixup_bportals(void *blob)
+{
+ int off, err;
+ unsigned int maj, min;
+ unsigned int ip_cfg;
+ struct ccsr_bman *bman = (void *)CONFIG_SYS_FSL_BMAN_ADDR;
+ u32 rev_1 = in_be32(&bman->ip_rev_1);
+ u32 rev_2 = in_be32(&bman->ip_rev_2);
+ char compat[64];
+ int compat_len;
+
+ maj = (rev_1 >> 8) & 0xff;
+ min = rev_1 & 0xff;
+
+ ip_cfg = rev_2 & 0xff;
+
+ compat_len = sprintf(compat, "fsl,bman-portal-%u.%u.%u",
+ maj, min, ip_cfg) + 1;
+ compat_len += sprintf(compat + compat_len, "fsl,bman-portal") + 1;
+
+ off = fdt_node_offset_by_compatible(blob, -1, "fsl,bman-portal");
+ while (off != -FDT_ERR_NOTFOUND) {
+ err = fdt_setprop(blob, off, "compatible", compat, compat_len);
+ if (err < 0) {
+ printf("ERROR: unable to create props for %s: %s\n",
+ fdt_get_name(blob, off, NULL),
+ fdt_strerror(err));
+ return;
+ }
+
+ off = fdt_node_offset_by_compatible(blob, off,
+ "fsl,bman-portal");
+ }
+}
diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c
index 8986bb4ad0..18a2730909 100644
--- a/drivers/misc/mxc_ocotp.c
+++ b/drivers/misc/mxc_ocotp.c
@@ -342,6 +342,23 @@ int fuse_sense(u32 bank, u32 word, u32 *val)
static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word,
const char *caller)
{
+#ifdef CONFIG_MX7ULP
+ u32 val;
+ int ret;
+
+ /* Only bank 0 and 1 are redundancy mode, others are ECC mode */
+ if (bank != 0 && bank != 1) {
+ ret = fuse_sense(bank, word, &val);
+ if (ret)
+ return ret;
+
+ if (val != 0) {
+ printf("mxc_ocotp: The word has been programmed, no more write\n");
+ return -EPERM;
+ }
+ }
+#endif
+
return prepare_access(regs, bank, word, true, caller);
}
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 8fbeaa740d..bc29611d78 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -10,6 +10,18 @@ config MMC
If you want MMC/SD/SDIO support, you should say Y here and
also to your specific host controller driver.
+config MMC_WRITE
+ bool "support for MMC/SD write operations"
+ depends on MMC
+ default y
+ help
+ Enable write access to MMC and SD Cards
+
+config MMC_BROKEN_CD
+ bool "Poll for broken card detection case"
+ help
+ If card detection feature is broken, just poll to detect.
+
config DM_MMC
bool "Enable MMC controllers using Driver Model"
depends on DM
@@ -42,6 +54,75 @@ config ARM_PL180_MMCI
If you have an ARM(R) platform with a Multimedia Card slot,
say Y or M here.
+config MMC_QUIRKS
+ bool "Enable quirks"
+ default y
+ help
+ Some cards and hosts may sometimes behave unexpectedly (quirks).
+ This option enable workarounds to handle those quirks. Some of them
+ are enabled by default, other may require additionnal flags or are
+ enabled by the host driver.
+
+config MMC_HW_PARTITIONING
+ bool "Support for HW partitioning command(eMMC)"
+ default y
+ help
+ This adds a command and an API to do hardware partitioning on eMMC
+ devices.
+
+config MMC_IO_VOLTAGE
+ bool "Support IO voltage configuration"
+ help
+ IO voltage configuration allows selecting the voltage level of the IO
+ lines (not the level of main supply). This is required for UHS
+ support. For eMMC this not mandatory, but not enabling this option may
+ prevent the driver of using the faster modes.
+
+config SPL_MMC_IO_VOLTAGE
+ bool "Support IO voltage configuration in SPL"
+ default n
+ help
+ IO voltage configuration allows selecting the voltage level of the IO
+ lines (not the level of main supply). This is required for UHS
+ support. For eMMC this not mandatory, but not enabling this option may
+ prevent the driver of using the faster modes.
+
+config MMC_UHS_SUPPORT
+ bool "enable UHS support"
+ depends on MMC_IO_VOLTAGE
+ help
+ The Ultra High Speed (UHS) bus is available on some SDHC and SDXC
+ cards. The IO voltage must be switchable from 3.3v to 1.8v. The bus
+ frequency can go up to 208MHz (SDR104)
+
+config SPL_MMC_UHS_SUPPORT
+ bool "enable UHS support in SPL"
+ depends on SPL_MMC_IO_VOLTAGE
+ help
+ The Ultra High Speed (UHS) bus is available on some SDHC and SDXC
+ cards. The IO voltage must be switchable from 3.3v to 1.8v. The bus
+ frequency can go up to 208MHz (SDR104)
+
+config MMC_HS200_SUPPORT
+ bool "enable HS200 support"
+ help
+ The HS200 mode is support by some eMMC. The bus frequency is up to
+ 200MHz. This mode requires tuning the IO.
+
+
+config SPL_MMC_HS200_SUPPORT
+ bool "enable HS200 support in SPL"
+ help
+ The HS200 mode is support by some eMMC. The bus frequency is up to
+ 200MHz. This mode requires tuning the IO.
+
+config MMC_VERBOSE
+ bool "Output more information about the MMC"
+ default y
+ help
+ Enable the output of more information about the card such as the
+ operating mode.
+
config SPL_MMC_TINY
bool "Tiny MMC framework in SPL"
help
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 9af375b044..64b6f21c61 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -7,6 +7,7 @@
obj-y += mmc.o
obj-$(CONFIG_$(SPL_)DM_MMC) += mmc-uclass.o
+obj-$(CONFIG_$(SPL_)MMC_WRITE) += mmc_write.o
ifndef CONFIG_$(SPL_)BLK
obj-y += mmc_legacy.o
@@ -16,9 +17,6 @@ obj-$(CONFIG_SUPPORT_EMMC_BOOT) += mmc_boot.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o
-obj-$(CONFIG_SPL_SAVEENV) += mmc_write.o
-else
-obj-y += mmc_write.o
endif
obj-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index 5edd383c68..e40575e589 100644
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -168,6 +168,7 @@ static int exynos_dwmci_get_config(const void *blob, int node,
if (host->dev_index > 4) {
printf("DWMMC%d: Can't get the dev index\n", host->dev_index);
+ free(priv);
return -EINVAL;
}
@@ -178,6 +179,7 @@ static int exynos_dwmci_get_config(const void *blob, int node,
base = fdtdec_get_addr(blob, node, "reg");
if (!base) {
printf("DWMMC%d: Can't get base address\n", host->dev_index);
+ free(priv);
return -EINVAL;
}
host->ioaddr = (void *)base;
@@ -187,6 +189,7 @@ static int exynos_dwmci_get_config(const void *blob, int node,
if (err) {
printf("DWMMC%d: Can't get sdr-timings for devider\n",
host->dev_index);
+ free(priv);
return -EINVAL;
}
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 499d622c6d..8d1e2f8a01 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -528,14 +528,19 @@ out:
static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
{
+ struct fsl_esdhc *regs = priv->esdhc_regs;
int div = 1;
#ifdef ARCH_MXC
+#ifdef CONFIG_MX53
+ /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
+ int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
+#else
int pre_div = 1;
+#endif
#else
int pre_div = 2;
#endif
int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
- struct fsl_esdhc *regs = priv->esdhc_regs;
int sdhc_clk = priv->sdhc_clk;
uint clk;
@@ -647,7 +652,11 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
esdhc_write32(&regs->clktunectrlstatus, 0x0);
/* Put VEND_SPEC to default value */
- esdhc_write32(&regs->vendorspec, VENDORSPEC_INIT);
+ if (priv->vs18_enable)
+ esdhc_write32(&regs->vendorspec, (VENDORSPEC_INIT |
+ ESDHC_VENDORSPEC_VSELECT));
+ else
+ esdhc_write32(&regs->vendorspec, VENDORSPEC_INIT);
/* Disable DLL_CTRL delay line */
esdhc_write32(&regs->dllctrl, 0x0);
@@ -665,7 +674,7 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
#endif
/* Set the initial clock speed */
- mmc_set_clock(mmc, 400000);
+ mmc_set_clock(mmc, 400000, false);
/* Disable the BRR and BWR bits in IRQSTAT */
esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
@@ -676,9 +685,6 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
/* Set timout to the maximum value */
esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
- if (priv->vs18_enable)
- esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
-
return 0;
}
diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c
index 22154d13d7..1c108b5470 100644
--- a/drivers/mmc/gen_atmel_mci.c
+++ b/drivers/mmc/gen_atmel_mci.c
@@ -74,6 +74,20 @@ static void dump_cmd(u32 cmdr, u32 arg, u32 status, const char* msg)
cmdr, cmdr & 0x3F, arg, status, msg);
}
+static inline void mci_set_blklen(atmel_mci_t *mci, int blklen)
+{
+ unsigned int version = atmel_mci_get_version(mci);
+
+ blklen &= 0xfffc;
+
+ /* MCI IP version >= 0x200 has blkr */
+ if (version >= 0x200)
+ writel(MMCI_BFINS(BLKLEN, blklen, readl(&mci->blkr)),
+ &mci->blkr);
+ else
+ writel(MMCI_BFINS(BLKLEN, blklen, readl(&mci->mr)), &mci->mr);
+}
+
/* Setup for MCI Clock and Block Size */
#ifdef CONFIG_DM_MMC
static void mci_set_mode(struct udevice *dev, u32 hz, u32 blklen)
@@ -124,7 +138,6 @@ static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen)
priv->curr_clk = bus_hz / (clkdiv * 2 + clkodd + 2);
else
priv->curr_clk = (bus_hz / (clkdiv + 1)) / 2;
- blklen &= 0xfffc;
mr = MMCI_BF(CLKDIV, clkdiv);
@@ -138,14 +151,10 @@ static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen)
*/
if (version >= 0x500)
mr |= MMCI_BF(CLKODD, clkodd);
- else
- mr |= MMCI_BF(BLKLEN, blklen);
writel(mr, &mci->mr);
- /* MCI IP version >= 0x200 has blkr */
- if (version >= 0x200)
- writel(MMCI_BF(BLKLEN, blklen), &mci->blkr);
+ mci_set_blklen(mci, blklen);
if (mmc->card_caps & mmc->cfg->host_caps & MMC_MODE_HS)
writel(MMCI_BIT(HSMODE), &mci->cfg);
@@ -236,7 +245,6 @@ static int atmel_mci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
{
struct atmel_mci_plat *plat = dev_get_platdata(dev);
struct atmel_mci_priv *priv = dev_get_priv(dev);
- struct mmc *mmc = mmc_get_mmc_dev(dev);
atmel_mci_t *mci = plat->mci;
#else
static int
@@ -257,11 +265,13 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
/* Figure out the transfer arguments */
cmdr = mci_encode_cmd(cmd, data, &error_flags);
+ mci_set_blklen(mci, data->blocksize);
+
/* For multi blocks read/write, set the block register */
if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK)
|| (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK))
- writel(data->blocks | MMCI_BF(BLKLEN, mmc->read_bl_len),
- &mci->blkr);
+ writel(data->blocks | MMCI_BF(BLKLEN, data->blocksize),
+ &mci->blkr);
/* Send the command */
writel(cmd->cmdarg, &mci->argr);
@@ -295,17 +305,15 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
if (data) {
u32 word_count, block_count;
u32* ioptr;
- u32 sys_blocksize, dummy, i;
+ u32 i;
u32 (*mci_data_op)
(atmel_mci_t *mci, u32* data, u32 error_flags);
if (data->flags & MMC_DATA_READ) {
mci_data_op = mci_data_read;
- sys_blocksize = mmc->read_bl_len;
ioptr = (u32*)data->dest;
} else {
mci_data_op = mci_data_write;
- sys_blocksize = mmc->write_bl_len;
ioptr = (u32*)data->src;
}
@@ -328,16 +336,6 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
1, cnt, 0);
}
#endif
-#ifdef DEBUG
- if (!status && word_count < (sys_blocksize / 4))
- printf("filling rest of block...\n");
-#endif
- /* fill the rest of a full block */
- while (!status && word_count < (sys_blocksize / 4)) {
- status = mci_data_op(mci, &dummy,
- error_flags);
- word_count++;
- }
if (status) {
dump_cmd(cmdr, cmd->cmdarg, status,
"Data Transfer Failed");
diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
index 4652fab45e..a2cd5d3a44 100644
--- a/drivers/mmc/meson_gx_mmc.c
+++ b/drivers/mmc/meson_gx_mmc.c
@@ -250,7 +250,7 @@ static int meson_mmc_probe(struct udevice *dev)
mmc->priv = pdata;
upriv->mmc = mmc;
- mmc_set_clock(mmc, cfg->f_min);
+ mmc_set_clock(mmc, cfg->f_min, false);
/* reset all status bits */
meson_write(mmc, STATUS_MASK, MESON_SD_EMMC_STATUS);
diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c
index 5dda20cda5..a3536b15ae 100644
--- a/drivers/mmc/mmc-uclass.c
+++ b/drivers/mmc/mmc-uclass.c
@@ -10,7 +10,6 @@
#include <dm.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
-#include <dm/root.h>
#include "mmc_private.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -51,6 +50,35 @@ int mmc_set_ios(struct mmc *mmc)
return dm_mmc_set_ios(mmc->dev);
}
+void dm_mmc_send_init_stream(struct udevice *dev)
+{
+ struct dm_mmc_ops *ops = mmc_get_ops(dev);
+
+ if (ops->send_init_stream)
+ ops->send_init_stream(dev);
+}
+
+void mmc_send_init_stream(struct mmc *mmc)
+{
+ dm_mmc_send_init_stream(mmc->dev);
+}
+
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
+int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout)
+{
+ struct dm_mmc_ops *ops = mmc_get_ops(dev);
+
+ if (!ops->wait_dat0)
+ return -ENOSYS;
+ return ops->wait_dat0(dev, state, timeout);
+}
+
+int mmc_wait_dat0(struct mmc *mmc, int state, int timeout)
+{
+ return dm_mmc_wait_dat0(mmc->dev, state, timeout);
+}
+#endif
+
int dm_mmc_get_wp(struct udevice *dev)
{
struct dm_mmc_ops *ops = mmc_get_ops(dev);
@@ -79,6 +107,72 @@ int mmc_getcd(struct mmc *mmc)
return dm_mmc_get_cd(mmc->dev);
}
+#ifdef MMC_SUPPORTS_TUNING
+int dm_mmc_execute_tuning(struct udevice *dev, uint opcode)
+{
+ struct dm_mmc_ops *ops = mmc_get_ops(dev);
+
+ if (!ops->execute_tuning)
+ return -ENOSYS;
+ return ops->execute_tuning(dev, opcode);
+}
+
+int mmc_execute_tuning(struct mmc *mmc, uint opcode)
+{
+ return dm_mmc_execute_tuning(mmc->dev, opcode);
+}
+#endif
+
+int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg)
+{
+ int val;
+
+ val = dev_read_u32_default(dev, "bus-width", 1);
+
+ switch (val) {
+ case 0x8:
+ cfg->host_caps |= MMC_MODE_8BIT;
+ /* fall through */
+ case 0x4:
+ cfg->host_caps |= MMC_MODE_4BIT;
+ /* fall through */
+ case 0x1:
+ cfg->host_caps |= MMC_MODE_1BIT;
+ break;
+ default:
+ dev_err(dev, "Invalid \"bus-width\" value %u!\n", val);
+ return -EINVAL;
+ }
+
+ /* f_max is obtained from the optional "max-frequency" property */
+ dev_read_u32(dev, "max-frequency", &cfg->f_max);
+
+ if (dev_read_bool(dev, "cap-sd-highspeed"))
+ cfg->host_caps |= MMC_CAP(SD_HS);
+ if (dev_read_bool(dev, "cap-mmc-highspeed"))
+ cfg->host_caps |= MMC_CAP(MMC_HS);
+ if (dev_read_bool(dev, "sd-uhs-sdr12"))
+ cfg->host_caps |= MMC_CAP(UHS_SDR12);
+ if (dev_read_bool(dev, "sd-uhs-sdr25"))
+ cfg->host_caps |= MMC_CAP(UHS_SDR25);
+ if (dev_read_bool(dev, "sd-uhs-sdr50"))
+ cfg->host_caps |= MMC_CAP(UHS_SDR50);
+ if (dev_read_bool(dev, "sd-uhs-sdr104"))
+ cfg->host_caps |= MMC_CAP(UHS_SDR104);
+ if (dev_read_bool(dev, "sd-uhs-ddr50"))
+ cfg->host_caps |= MMC_CAP(UHS_DDR50);
+ if (dev_read_bool(dev, "mmc-ddr-1_8v"))
+ cfg->host_caps |= MMC_CAP(MMC_DDR_52);
+ if (dev_read_bool(dev, "mmc-ddr-1_2v"))
+ cfg->host_caps |= MMC_CAP(MMC_DDR_52);
+ if (dev_read_bool(dev, "mmc-hs200-1_8v"))
+ cfg->host_caps |= MMC_CAP(MMC_HS_200);
+ if (dev_read_bool(dev, "mmc-hs200-1_2v"))
+ cfg->host_caps |= MMC_CAP(MMC_HS_200);
+
+ return 0;
+}
+
struct mmc *mmc_get_mmc_dev(struct udevice *dev)
{
struct mmc_uclass_priv *upriv;
@@ -275,7 +369,7 @@ static int mmc_blk_probe(struct udevice *dev)
static const struct blk_ops mmc_blk_ops = {
.read = mmc_bread,
-#ifndef CONFIG_SPL_BUILD
+#if CONFIG_IS_ENABLED(MMC_WRITE)
.write = mmc_bwrite,
.erase = mmc_berase,
#endif
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 38d2e07dd5..255310a8e6 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -22,13 +22,9 @@
#include <div64.h>
#include "mmc_private.h"
-static const unsigned int sd_au_size[] = {
- 0, SZ_16K / 512, SZ_32K / 512,
- SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
- SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
- SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
- SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512, SZ_64M / 512,
-};
+static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
+static int mmc_power_cycle(struct mmc *mmc);
+static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps);
#if CONFIG_IS_ENABLED(MMC_TINY)
static struct mmc mmc_static;
@@ -54,6 +50,14 @@ struct blk_desc *mmc_get_blk_desc(struct mmc *mmc)
#endif
#if !CONFIG_IS_ENABLED(DM_MMC)
+
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
+static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout)
+{
+ return -ENOSYS;
+}
+#endif
+
__weak int board_mmc_getwp(struct mmc *mmc)
{
return -1;
@@ -149,6 +153,71 @@ void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
}
#endif
+#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
+const char *mmc_mode_name(enum bus_mode mode)
+{
+ static const char *const names[] = {
+ [MMC_LEGACY] = "MMC legacy",
+ [SD_LEGACY] = "SD Legacy",
+ [MMC_HS] = "MMC High Speed (26MHz)",
+ [SD_HS] = "SD High Speed (50MHz)",
+ [UHS_SDR12] = "UHS SDR12 (25MHz)",
+ [UHS_SDR25] = "UHS SDR25 (50MHz)",
+ [UHS_SDR50] = "UHS SDR50 (100MHz)",
+ [UHS_SDR104] = "UHS SDR104 (208MHz)",
+ [UHS_DDR50] = "UHS DDR50 (50MHz)",
+ [MMC_HS_52] = "MMC High Speed (52MHz)",
+ [MMC_DDR_52] = "MMC DDR52 (52MHz)",
+ [MMC_HS_200] = "HS200 (200MHz)",
+ };
+
+ if (mode >= MMC_MODES_END)
+ return "Unknown mode";
+ else
+ return names[mode];
+}
+#endif
+
+static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
+{
+ static const int freqs[] = {
+ [SD_LEGACY] = 25000000,
+ [MMC_HS] = 26000000,
+ [SD_HS] = 50000000,
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
+ [UHS_SDR12] = 25000000,
+ [UHS_SDR25] = 50000000,
+ [UHS_SDR50] = 100000000,
+ [UHS_DDR50] = 50000000,
+#ifdef MMC_SUPPORTS_TUNING
+ [UHS_SDR104] = 208000000,
+#endif
+#endif
+ [MMC_HS_52] = 52000000,
+ [MMC_DDR_52] = 52000000,
+#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
+ [MMC_HS_200] = 200000000,
+#endif
+ };
+
+ if (mode == MMC_LEGACY)
+ return mmc->legacy_speed;
+ else if (mode >= MMC_MODES_END)
+ return 0;
+ else
+ return freqs[mode];
+}
+
+static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
+{
+ mmc->selected_mode = mode;
+ mmc->tran_speed = mmc_mode2freq(mmc, mode);
+ mmc->ddr_mode = mmc_is_mode_ddr(mode);
+ debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
+ mmc->tran_speed / 1000000);
+ return 0;
+}
+
#if !CONFIG_IS_ENABLED(DM_MMC)
int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
{
@@ -179,10 +248,11 @@ int mmc_send_status(struct mmc *mmc, int timeout)
(cmd.response[0] & MMC_STATUS_CURR_STATE) !=
MMC_STATE_PRG)
break;
- else if (cmd.response[0] & MMC_STATUS_MASK) {
+
+ if (cmd.response[0] & MMC_STATUS_MASK) {
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
- printf("Status Error: 0x%08X\n",
- cmd.response[0]);
+ pr_err("Status Error: 0x%08X\n",
+ cmd.response[0]);
#endif
return -ECOMM;
}
@@ -198,7 +268,7 @@ int mmc_send_status(struct mmc *mmc, int timeout)
mmc_trace_state(mmc, &cmd);
if (timeout <= 0) {
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
- printf("Timeout waiting card ready\n");
+ pr_err("Timeout waiting card ready\n");
#endif
return -ETIMEDOUT;
}
@@ -209,6 +279,7 @@ int mmc_send_status(struct mmc *mmc, int timeout)
int mmc_set_blocklen(struct mmc *mmc, int len)
{
struct mmc_cmd cmd;
+ int err;
if (mmc->ddr_mode)
return 0;
@@ -217,9 +288,96 @@ int mmc_set_blocklen(struct mmc *mmc, int len)
cmd.resp_type = MMC_RSP_R1;
cmd.cmdarg = len;
- return mmc_send_cmd(mmc, &cmd, NULL);
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+
+#ifdef CONFIG_MMC_QUIRKS
+ if (err && (mmc->quirks & MMC_QUIRK_RETRY_SET_BLOCKLEN)) {
+ int retries = 4;
+ /*
+ * It has been seen that SET_BLOCKLEN may fail on the first
+ * attempt, let's try a few more time
+ */
+ do {
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+ if (!err)
+ break;
+ } while (retries--);
+ }
+#endif
+
+ return err;
}
+#ifdef MMC_SUPPORTS_TUNING
+static const u8 tuning_blk_pattern_4bit[] = {
+ 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
+ 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
+ 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
+ 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
+ 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
+ 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
+ 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
+ 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
+};
+
+static const u8 tuning_blk_pattern_8bit[] = {
+ 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
+ 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
+ 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
+ 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
+ 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
+ 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
+ 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
+ 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
+ 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
+ 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
+ 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
+ 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
+ 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
+ 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
+ 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
+};
+
+int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error)
+{
+ struct mmc_cmd cmd;
+ struct mmc_data data;
+ const u8 *tuning_block_pattern;
+ int size, err;
+
+ if (mmc->bus_width == 8) {
+ tuning_block_pattern = tuning_blk_pattern_8bit;
+ size = sizeof(tuning_blk_pattern_8bit);
+ } else if (mmc->bus_width == 4) {
+ tuning_block_pattern = tuning_blk_pattern_4bit;
+ size = sizeof(tuning_blk_pattern_4bit);
+ } else {
+ return -EINVAL;
+ }
+
+ ALLOC_CACHE_ALIGN_BUFFER(u8, data_buf, size);
+
+ cmd.cmdidx = opcode;
+ cmd.cmdarg = 0;
+ cmd.resp_type = MMC_RSP_R1;
+
+ data.dest = (void *)data_buf;
+ data.blocks = 1;
+ data.blocksize = size;
+ data.flags = MMC_DATA_READ;
+
+ err = mmc_send_cmd(mmc, &cmd, &data);
+ if (err)
+ return err;
+
+ if (memcmp(data_buf, tuning_block_pattern, size))
+ return -EIO;
+
+ return 0;
+}
+#endif
+
static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
lbaint_t blkcnt)
{
@@ -252,7 +410,7 @@ static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
cmd.resp_type = MMC_RSP_R1b;
if (mmc_send_cmd(mmc, &cmd, NULL)) {
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
- printf("mmc fail to send stop cmd\n");
+ pr_err("mmc fail to send stop cmd\n");
#endif
return 0;
}
@@ -292,8 +450,8 @@ ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
if ((start + blkcnt) > block_dev->lba) {
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
- printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
- start + blkcnt, block_dev->lba);
+ pr_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
+ start + blkcnt, block_dev->lba);
#endif
return 0;
}
@@ -339,7 +497,69 @@ static int mmc_go_idle(struct mmc *mmc)
return 0;
}
-static int sd_send_op_cond(struct mmc *mmc)
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
+static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage)
+{
+ struct mmc_cmd cmd;
+ int err = 0;
+
+ /*
+ * Send CMD11 only if the request is to switch the card to
+ * 1.8V signalling.
+ */
+ if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
+ return mmc_set_signal_voltage(mmc, signal_voltage);
+
+ cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
+ cmd.cmdarg = 0;
+ cmd.resp_type = MMC_RSP_R1;
+
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+ if (err)
+ return err;
+
+ if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR))
+ return -EIO;
+
+ /*
+ * The card should drive cmd and dat[0:3] low immediately
+ * after the response of cmd11, but wait 100 us to be sure
+ */
+ err = mmc_wait_dat0(mmc, 0, 100);
+ if (err == -ENOSYS)
+ udelay(100);
+ else if (err)
+ return -ETIMEDOUT;
+
+ /*
+ * During a signal voltage level switch, the clock must be gated
+ * for 5 ms according to the SD spec
+ */
+ mmc_set_clock(mmc, mmc->clock, true);
+
+ err = mmc_set_signal_voltage(mmc, signal_voltage);
+ if (err)
+ return err;
+
+ /* Keep clock gated for at least 10 ms, though spec only says 5 ms */
+ mdelay(10);
+ mmc_set_clock(mmc, mmc->clock, false);
+
+ /*
+ * Failure to switch is indicated by the card holding
+ * dat[0:3] low. Wait for at least 1 ms according to spec
+ */
+ err = mmc_wait_dat0(mmc, 1, 1000);
+ if (err == -ENOSYS)
+ udelay(1000);
+ else if (err)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+#endif
+
+static int sd_send_op_cond(struct mmc *mmc, bool uhs_en)
{
int timeout = 1000;
int err;
@@ -371,6 +591,9 @@ static int sd_send_op_cond(struct mmc *mmc)
if (mmc->version == SD_VERSION_2)
cmd.cmdarg |= OCR_HCS;
+ if (uhs_en)
+ cmd.cmdarg |= OCR_S18R;
+
err = mmc_send_cmd(mmc, &cmd, NULL);
if (err)
@@ -401,6 +624,15 @@ static int sd_send_op_cond(struct mmc *mmc)
mmc->ocr = cmd.response[0];
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
+ if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000)
+ == 0x41000000) {
+ err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
+ if (err)
+ return err;
+ }
+#endif
+
mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
mmc->rca = 0;
@@ -546,53 +778,86 @@ int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
}
-static int mmc_change_freq(struct mmc *mmc)
+static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode)
{
- ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
- char cardtype;
int err;
+ int speed_bits;
- mmc->card_caps = 0;
+ ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
- if (mmc_host_is_spi(mmc))
- return 0;
+ switch (mode) {
+ case MMC_HS:
+ case MMC_HS_52:
+ case MMC_DDR_52:
+ speed_bits = EXT_CSD_TIMING_HS;
+ break;
+#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
+ case MMC_HS_200:
+ speed_bits = EXT_CSD_TIMING_HS200;
+ break;
+#endif
+ case MMC_LEGACY:
+ speed_bits = EXT_CSD_TIMING_LEGACY;
+ break;
+ default:
+ return -EINVAL;
+ }
+ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
+ speed_bits);
+ if (err)
+ return err;
- /* Only version 4 supports high-speed */
- if (mmc->version < MMC_VERSION_4)
- return 0;
+ if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
+ /* Now check to see that it worked */
+ err = mmc_send_ext_csd(mmc, test_csd);
+ if (err)
+ return err;
- mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
+ /* No high-speed support */
+ if (!test_csd[EXT_CSD_HS_TIMING])
+ return -ENOTSUPP;
+ }
- err = mmc_send_ext_csd(mmc, ext_csd);
+ return 0;
+}
- if (err)
- return err;
+static int mmc_get_capabilities(struct mmc *mmc)
+{
+ u8 *ext_csd = mmc->ext_csd;
+ char cardtype;
- cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
+ mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
- err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
+ if (mmc_host_is_spi(mmc))
+ return 0;
- if (err)
- return err;
+ /* Only version 4 supports high-speed */
+ if (mmc->version < MMC_VERSION_4)
+ return 0;
- /* Now check to see that it worked */
- err = mmc_send_ext_csd(mmc, ext_csd);
+ if (!ext_csd) {
+ pr_err("No ext_csd found!\n"); /* this should enver happen */
+ return -ENOTSUPP;
+ }
- if (err)
- return err;
+ mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
- /* No high-speed support */
- if (!ext_csd[EXT_CSD_HS_TIMING])
- return 0;
+ cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0x3f;
+ mmc->cardtype = cardtype;
- /* High Speed is set, there are two types: 52MHz and 26MHz */
+#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
+ if (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
+ EXT_CSD_CARD_TYPE_HS200_1_8V)) {
+ mmc->card_caps |= MMC_MODE_HS200;
+ }
+#endif
if (cardtype & EXT_CSD_CARD_TYPE_52) {
- if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
+ if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
mmc->card_caps |= MMC_MODE_DDR_52MHz;
- mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
- } else {
- mmc->card_caps |= MMC_MODE_HS;
+ mmc->card_caps |= MMC_MODE_HS_52MHz;
}
+ if (cardtype & EXT_CSD_CARD_TYPE_26)
+ mmc->card_caps |= MMC_MODE_HS;
return 0;
}
@@ -625,10 +890,46 @@ static int mmc_set_capacity(struct mmc *mmc, int part_num)
return 0;
}
+#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
+static int mmc_boot_part_access_chk(struct mmc *mmc, unsigned int part_num)
+{
+ int forbidden = 0;
+ bool change = false;
+
+ if (part_num & PART_ACCESS_MASK)
+ forbidden = MMC_CAP(MMC_HS_200);
+
+ if (MMC_CAP(mmc->selected_mode) & forbidden) {
+ debug("selected mode (%s) is forbidden for part %d\n",
+ mmc_mode_name(mmc->selected_mode), part_num);
+ change = true;
+ } else if (mmc->selected_mode != mmc->best_mode) {
+ debug("selected mode is not optimal\n");
+ change = true;
+ }
+
+ if (change)
+ return mmc_select_mode_and_width(mmc,
+ mmc->card_caps & ~forbidden);
+
+ return 0;
+}
+#else
+static inline int mmc_boot_part_access_chk(struct mmc *mmc,
+ unsigned int part_num)
+{
+ return 0;
+}
+#endif
+
int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
{
int ret;
+ ret = mmc_boot_part_access_chk(mmc, part_num);
+ if (ret)
+ return ret;
+
ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
(mmc->part_config & ~PART_ACCESS_MASK)
| (part_num & PART_ACCESS_MASK));
@@ -645,6 +946,7 @@ int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
return ret;
}
+#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
int mmc_hwpart_config(struct mmc *mmc,
const struct mmc_hwpart_conf *conf,
enum mmc_hwpart_conf_mode mode)
@@ -663,17 +965,17 @@ int mmc_hwpart_config(struct mmc *mmc,
return -EINVAL;
if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
- printf("eMMC >= 4.4 required for enhanced user data area\n");
+ pr_err("eMMC >= 4.4 required for enhanced user data area\n");
return -EMEDIUMTYPE;
}
if (!(mmc->part_support & PART_SUPPORT)) {
- printf("Card does not support partitioning\n");
+ pr_err("Card does not support partitioning\n");
return -EMEDIUMTYPE;
}
if (!mmc->hc_wp_grp_size) {
- printf("Card does not define HC WP group size\n");
+ pr_err("Card does not define HC WP group size\n");
return -EMEDIUMTYPE;
}
@@ -681,7 +983,7 @@ int mmc_hwpart_config(struct mmc *mmc,
if (conf->user.enh_size) {
if (conf->user.enh_size % mmc->hc_wp_grp_size ||
conf->user.enh_start % mmc->hc_wp_grp_size) {
- printf("User data enhanced area not HC WP group "
+ pr_err("User data enhanced area not HC WP group "
"size aligned\n");
return -EINVAL;
}
@@ -700,7 +1002,7 @@ int mmc_hwpart_config(struct mmc *mmc,
for (pidx = 0; pidx < 4; pidx++) {
if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
- printf("GP%i partition not HC WP group size "
+ pr_err("GP%i partition not HC WP group size "
"aligned\n", pidx+1);
return -EINVAL;
}
@@ -712,7 +1014,7 @@ int mmc_hwpart_config(struct mmc *mmc,
}
if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
- printf("Card does not support enhanced attribute\n");
+ pr_err("Card does not support enhanced attribute\n");
return -EMEDIUMTYPE;
}
@@ -725,7 +1027,7 @@ int mmc_hwpart_config(struct mmc *mmc,
(ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
if (tot_enh_size_mult > max_enh_size_mult) {
- printf("Total enhanced size exceeds maximum (%u > %u)\n",
+ pr_err("Total enhanced size exceeds maximum (%u > %u)\n",
tot_enh_size_mult, max_enh_size_mult);
return -EMEDIUMTYPE;
}
@@ -759,7 +1061,7 @@ int mmc_hwpart_config(struct mmc *mmc,
if (ext_csd[EXT_CSD_PARTITION_SETTING] &
EXT_CSD_PARTITION_SETTING_COMPLETED) {
- printf("Card already partitioned\n");
+ pr_err("Card already partitioned\n");
return -EPERM;
}
@@ -838,6 +1140,7 @@ int mmc_hwpart_config(struct mmc *mmc,
return 0;
}
+#endif
#if !CONFIG_IS_ENABLED(DM_MMC)
int mmc_getcd(struct mmc *mmc)
@@ -878,16 +1181,19 @@ static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
}
-static int sd_change_freq(struct mmc *mmc)
+static int sd_get_capabilities(struct mmc *mmc)
{
int err;
struct mmc_cmd cmd;
- ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2);
- ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
+ ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
+ ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
struct mmc_data data;
int timeout;
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
+ u32 sd3_bus_mode;
+#endif
- mmc->card_caps = 0;
+ mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(SD_LEGACY);
if (mmc_host_is_spi(mmc))
return 0;
@@ -964,32 +1270,115 @@ retry_scr:
}
/* If high-speed isn't supported, we return */
- if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
- return 0;
+ if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
+ mmc->card_caps |= MMC_CAP(SD_HS);
- /*
- * If the host doesn't support SD_HIGHSPEED, do not switch card to
- * HIGHSPEED mode even if the card support SD_HIGHSPPED.
- * This can avoid furthur problem when the card runs in different
- * mode between the host.
- */
- if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) &&
- (mmc->cfg->host_caps & MMC_MODE_HS)))
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
+ /* Version before 3.0 don't support UHS modes */
+ if (mmc->version < SD_VERSION_3)
return 0;
- err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
+ sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f;
+ if (sd3_bus_mode & SD_MODE_UHS_SDR104)
+ mmc->card_caps |= MMC_CAP(UHS_SDR104);
+ if (sd3_bus_mode & SD_MODE_UHS_SDR50)
+ mmc->card_caps |= MMC_CAP(UHS_SDR50);
+ if (sd3_bus_mode & SD_MODE_UHS_SDR25)
+ mmc->card_caps |= MMC_CAP(UHS_SDR25);
+ if (sd3_bus_mode & SD_MODE_UHS_SDR12)
+ mmc->card_caps |= MMC_CAP(UHS_SDR12);
+ if (sd3_bus_mode & SD_MODE_UHS_DDR50)
+ mmc->card_caps |= MMC_CAP(UHS_DDR50);
+#endif
+
+ return 0;
+}
+
+static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
+{
+ int err;
+
+ ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
+ int speed;
+
+ switch (mode) {
+ case SD_LEGACY:
+ speed = UHS_SDR12_BUS_SPEED;
+ break;
+ case SD_HS:
+ speed = HIGH_SPEED_BUS_SPEED;
+ break;
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
+ case UHS_SDR12:
+ speed = UHS_SDR12_BUS_SPEED;
+ break;
+ case UHS_SDR25:
+ speed = UHS_SDR25_BUS_SPEED;
+ break;
+ case UHS_SDR50:
+ speed = UHS_SDR50_BUS_SPEED;
+ break;
+ case UHS_DDR50:
+ speed = UHS_DDR50_BUS_SPEED;
+ break;
+ case UHS_SDR104:
+ speed = UHS_SDR104_BUS_SPEED;
+ break;
+#endif
+ default:
+ return -EINVAL;
+ }
+
+ err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status);
+ if (err)
+ return err;
+
+ if ((__be32_to_cpu(switch_status[4]) >> 24) != speed)
+ return -ENOTSUPP;
+
+ return 0;
+}
+
+int sd_select_bus_width(struct mmc *mmc, int w)
+{
+ int err;
+ struct mmc_cmd cmd;
+
+ if ((w != 4) && (w != 1))
+ return -EINVAL;
+ cmd.cmdidx = MMC_CMD_APP_CMD;
+ cmd.resp_type = MMC_RSP_R1;
+ cmd.cmdarg = mmc->rca << 16;
+
+ err = mmc_send_cmd(mmc, &cmd, NULL);
if (err)
return err;
- if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000)
- mmc->card_caps |= MMC_MODE_HS;
+ cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
+ cmd.resp_type = MMC_RSP_R1;
+ if (w == 4)
+ cmd.cmdarg = 2;
+ else if (w == 1)
+ cmd.cmdarg = 0;
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+ if (err)
+ return err;
return 0;
}
+#if CONFIG_IS_ENABLED(MMC_WRITE)
static int sd_read_ssr(struct mmc *mmc)
{
+ static const unsigned int sd_au_size[] = {
+ 0, SZ_16K / 512, SZ_32K / 512,
+ SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
+ SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
+ SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
+ SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512,
+ SZ_64M / 512,
+ };
int err, i;
struct mmc_cmd cmd;
ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
@@ -1043,7 +1432,7 @@ retry_ssr:
return 0;
}
-
+#endif
/* frequency bases */
/* divided by 10 to be nice to platforms without floating point */
static const int fbase[] = {
@@ -1075,44 +1464,665 @@ static const u8 multipliers[] = {
80,
};
+static inline int bus_width(uint cap)
+{
+ if (cap == MMC_MODE_8BIT)
+ return 8;
+ if (cap == MMC_MODE_4BIT)
+ return 4;
+ if (cap == MMC_MODE_1BIT)
+ return 1;
+ pr_warn("invalid bus witdh capability 0x%x\n", cap);
+ return 0;
+}
+
#if !CONFIG_IS_ENABLED(DM_MMC)
-static void mmc_set_ios(struct mmc *mmc)
+#ifdef MMC_SUPPORTS_TUNING
+static int mmc_execute_tuning(struct mmc *mmc, uint opcode)
+{
+ return -ENOTSUPP;
+}
+#endif
+
+static void mmc_send_init_stream(struct mmc *mmc)
+{
+}
+
+static int mmc_set_ios(struct mmc *mmc)
{
+ int ret = 0;
+
if (mmc->cfg->ops->set_ios)
- mmc->cfg->ops->set_ios(mmc);
+ ret = mmc->cfg->ops->set_ios(mmc);
+
+ return ret;
}
#endif
-void mmc_set_clock(struct mmc *mmc, uint clock)
+int mmc_set_clock(struct mmc *mmc, uint clock, bool disable)
{
- if (clock > mmc->cfg->f_max)
- clock = mmc->cfg->f_max;
+ if (!disable) {
+ if (clock > mmc->cfg->f_max)
+ clock = mmc->cfg->f_max;
- if (clock < mmc->cfg->f_min)
- clock = mmc->cfg->f_min;
+ if (clock < mmc->cfg->f_min)
+ clock = mmc->cfg->f_min;
+ }
mmc->clock = clock;
+ mmc->clk_disable = disable;
- mmc_set_ios(mmc);
+ return mmc_set_ios(mmc);
}
-static void mmc_set_bus_width(struct mmc *mmc, uint width)
+static int mmc_set_bus_width(struct mmc *mmc, uint width)
{
mmc->bus_width = width;
- mmc_set_ios(mmc);
+ return mmc_set_ios(mmc);
+}
+
+#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
+/*
+ * helper function to display the capabilities in a human
+ * friendly manner. The capabilities include bus width and
+ * supported modes.
+ */
+void mmc_dump_capabilities(const char *text, uint caps)
+{
+ enum bus_mode mode;
+
+ printf("%s: widths [", text);
+ if (caps & MMC_MODE_8BIT)
+ printf("8, ");
+ if (caps & MMC_MODE_4BIT)
+ printf("4, ");
+ if (caps & MMC_MODE_1BIT)
+ printf("1, ");
+ printf("\b\b] modes [");
+ for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
+ if (MMC_CAP(mode) & caps)
+ printf("%s, ", mmc_mode_name(mode));
+ printf("\b\b]\n");
+}
+#endif
+
+struct mode_width_tuning {
+ enum bus_mode mode;
+ uint widths;
+#ifdef MMC_SUPPORTS_TUNING
+ uint tuning;
+#endif
+};
+
+#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
+int mmc_voltage_to_mv(enum mmc_voltage voltage)
+{
+ switch (voltage) {
+ case MMC_SIGNAL_VOLTAGE_000: return 0;
+ case MMC_SIGNAL_VOLTAGE_330: return 3300;
+ case MMC_SIGNAL_VOLTAGE_180: return 1800;
+ case MMC_SIGNAL_VOLTAGE_120: return 1200;
+ }
+ return -EINVAL;
+}
+
+static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
+{
+ int err;
+
+ if (mmc->signal_voltage == signal_voltage)
+ return 0;
+
+ mmc->signal_voltage = signal_voltage;
+ err = mmc_set_ios(mmc);
+ if (err)
+ debug("unable to set voltage (err %d)\n", err);
+
+ return err;
+}
+#else
+static inline int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
+{
+ return 0;
+}
+#endif
+
+static const struct mode_width_tuning sd_modes_by_pref[] = {
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
+#ifdef MMC_SUPPORTS_TUNING
+ {
+ .mode = UHS_SDR104,
+ .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
+ .tuning = MMC_CMD_SEND_TUNING_BLOCK
+ },
+#endif
+ {
+ .mode = UHS_SDR50,
+ .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
+ },
+ {
+ .mode = UHS_DDR50,
+ .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
+ },
+ {
+ .mode = UHS_SDR25,
+ .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
+ },
+#endif
+ {
+ .mode = SD_HS,
+ .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
+ },
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
+ {
+ .mode = UHS_SDR12,
+ .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
+ },
+#endif
+ {
+ .mode = SD_LEGACY,
+ .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
+ }
+};
+
+#define for_each_sd_mode_by_pref(caps, mwt) \
+ for (mwt = sd_modes_by_pref;\
+ mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
+ mwt++) \
+ if (caps & MMC_CAP(mwt->mode))
+
+static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
+{
+ int err;
+ uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
+ const struct mode_width_tuning *mwt;
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
+ bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false;
+#else
+ bool uhs_en = false;
+#endif
+ uint caps;
+
+#ifdef DEBUG
+ mmc_dump_capabilities("sd card", card_caps);
+ mmc_dump_capabilities("host", mmc->host_caps);
+#endif
+
+ /* Restrict card's capabilities by what the host can do */
+ caps = card_caps & mmc->host_caps;
+
+ if (!uhs_en)
+ caps &= ~UHS_CAPS;
+
+ for_each_sd_mode_by_pref(caps, mwt) {
+ uint *w;
+
+ for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
+ if (*w & caps & mwt->widths) {
+ debug("trying mode %s width %d (at %d MHz)\n",
+ mmc_mode_name(mwt->mode),
+ bus_width(*w),
+ mmc_mode2freq(mmc, mwt->mode) / 1000000);
+
+ /* configure the bus width (card + host) */
+ err = sd_select_bus_width(mmc, bus_width(*w));
+ if (err)
+ goto error;
+ mmc_set_bus_width(mmc, bus_width(*w));
+
+ /* configure the bus mode (card) */
+ err = sd_set_card_speed(mmc, mwt->mode);
+ if (err)
+ goto error;
+
+ /* configure the bus mode (host) */
+ mmc_select_mode(mmc, mwt->mode);
+ mmc_set_clock(mmc, mmc->tran_speed, false);
+
+#ifdef MMC_SUPPORTS_TUNING
+ /* execute tuning if needed */
+ if (mwt->tuning && !mmc_host_is_spi(mmc)) {
+ err = mmc_execute_tuning(mmc,
+ mwt->tuning);
+ if (err) {
+ debug("tuning failed\n");
+ goto error;
+ }
+ }
+#endif
+
+#if CONFIG_IS_ENABLED(MMC_WRITE)
+ err = sd_read_ssr(mmc);
+ if (!err)
+ pr_warn("unable to read ssr\n");
+#endif
+ if (!err)
+ return 0;
+
+error:
+ /* revert to a safer bus speed */
+ mmc_select_mode(mmc, SD_LEGACY);
+ mmc_set_clock(mmc, mmc->tran_speed, false);
+ }
+ }
+ }
+
+ printf("unable to select a mode\n");
+ return -ENOTSUPP;
+}
+
+/*
+ * read the compare the part of ext csd that is constant.
+ * This can be used to check that the transfer is working
+ * as expected.
+ */
+static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
+{
+ int err;
+ const u8 *ext_csd = mmc->ext_csd;
+ ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
+
+ if (mmc->version < MMC_VERSION_4)
+ return 0;
+
+ err = mmc_send_ext_csd(mmc, test_csd);
+ if (err)
+ return err;
+
+ /* Only compare read only fields */
+ if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
+ == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
+ ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
+ == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
+ ext_csd[EXT_CSD_REV]
+ == test_csd[EXT_CSD_REV] &&
+ ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
+ == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
+ memcmp(&ext_csd[EXT_CSD_SEC_CNT],
+ &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
+ return 0;
+
+ return -EBADMSG;
+}
+
+#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
+static int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
+ uint32_t allowed_mask)
+{
+ u32 card_mask = 0;
+
+ switch (mode) {
+ case MMC_HS_200:
+ if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS200_1_8V)
+ card_mask |= MMC_SIGNAL_VOLTAGE_180;
+ if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS200_1_2V)
+ card_mask |= MMC_SIGNAL_VOLTAGE_120;
+ break;
+ case MMC_DDR_52:
+ if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
+ card_mask |= MMC_SIGNAL_VOLTAGE_330 |
+ MMC_SIGNAL_VOLTAGE_180;
+ if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_2V)
+ card_mask |= MMC_SIGNAL_VOLTAGE_120;
+ break;
+ default:
+ card_mask |= MMC_SIGNAL_VOLTAGE_330;
+ break;
+ }
+
+ while (card_mask & allowed_mask) {
+ enum mmc_voltage best_match;
+
+ best_match = 1 << (ffs(card_mask & allowed_mask) - 1);
+ if (!mmc_set_signal_voltage(mmc, best_match))
+ return 0;
+
+ allowed_mask &= ~best_match;
+ }
+
+ return -ENOTSUPP;
+}
+#else
+static inline int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
+ uint32_t allowed_mask)
+{
+ return 0;
+}
+#endif
+
+static const struct mode_width_tuning mmc_modes_by_pref[] = {
+#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
+ {
+ .mode = MMC_HS_200,
+ .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
+ .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
+ },
+#endif
+ {
+ .mode = MMC_DDR_52,
+ .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
+ },
+ {
+ .mode = MMC_HS_52,
+ .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
+ },
+ {
+ .mode = MMC_HS,
+ .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
+ },
+ {
+ .mode = MMC_LEGACY,
+ .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
+ }
+};
+
+#define for_each_mmc_mode_by_pref(caps, mwt) \
+ for (mwt = mmc_modes_by_pref;\
+ mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
+ mwt++) \
+ if (caps & MMC_CAP(mwt->mode))
+
+static const struct ext_csd_bus_width {
+ uint cap;
+ bool is_ddr;
+ uint ext_csd_bits;
+} ext_csd_bus_width[] = {
+ {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},
+ {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},
+ {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},
+ {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},
+ {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},
+};
+
+#define for_each_supported_width(caps, ddr, ecbv) \
+ for (ecbv = ext_csd_bus_width;\
+ ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
+ ecbv++) \
+ if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
+
+static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
+{
+ int err;
+ const struct mode_width_tuning *mwt;
+ const struct ext_csd_bus_width *ecbw;
+
+#ifdef DEBUG
+ mmc_dump_capabilities("mmc", card_caps);
+ mmc_dump_capabilities("host", mmc->host_caps);
+#endif
+
+ /* Restrict card's capabilities by what the host can do */
+ card_caps &= mmc->host_caps;
+
+ /* Only version 4 of MMC supports wider bus widths */
+ if (mmc->version < MMC_VERSION_4)
+ return 0;
+
+ if (!mmc->ext_csd) {
+ debug("No ext_csd found!\n"); /* this should enver happen */
+ return -ENOTSUPP;
+ }
+
+ mmc_set_clock(mmc, mmc->legacy_speed, false);
+
+ for_each_mmc_mode_by_pref(card_caps, mwt) {
+ for_each_supported_width(card_caps & mwt->widths,
+ mmc_is_mode_ddr(mwt->mode), ecbw) {
+ enum mmc_voltage old_voltage;
+ debug("trying mode %s width %d (at %d MHz)\n",
+ mmc_mode_name(mwt->mode),
+ bus_width(ecbw->cap),
+ mmc_mode2freq(mmc, mwt->mode) / 1000000);
+ old_voltage = mmc->signal_voltage;
+ err = mmc_set_lowest_voltage(mmc, mwt->mode,
+ MMC_ALL_SIGNAL_VOLTAGE);
+ if (err)
+ continue;
+
+ /* configure the bus width (card + host) */
+ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+ EXT_CSD_BUS_WIDTH,
+ ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);
+ if (err)
+ goto error;
+ mmc_set_bus_width(mmc, bus_width(ecbw->cap));
+
+ /* configure the bus speed (card) */
+ err = mmc_set_card_speed(mmc, mwt->mode);
+ if (err)
+ goto error;
+
+ /*
+ * configure the bus width AND the ddr mode (card)
+ * The host side will be taken care of in the next step
+ */
+ if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {
+ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+ EXT_CSD_BUS_WIDTH,
+ ecbw->ext_csd_bits);
+ if (err)
+ goto error;
+ }
+
+ /* configure the bus mode (host) */
+ mmc_select_mode(mmc, mwt->mode);
+ mmc_set_clock(mmc, mmc->tran_speed, false);
+#ifdef MMC_SUPPORTS_TUNING
+
+ /* execute tuning if needed */
+ if (mwt->tuning) {
+ err = mmc_execute_tuning(mmc, mwt->tuning);
+ if (err) {
+ debug("tuning failed\n");
+ goto error;
+ }
+ }
+#endif
+
+ /* do a transfer to check the configuration */
+ err = mmc_read_and_compare_ext_csd(mmc);
+ if (!err)
+ return 0;
+error:
+ mmc_set_signal_voltage(mmc, old_voltage);
+ /* if an error occured, revert to a safer bus mode */
+ mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+ EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
+ mmc_select_mode(mmc, MMC_LEGACY);
+ mmc_set_bus_width(mmc, 1);
+ }
+ }
+
+ pr_err("unable to select a mode\n");
+
+ return -ENOTSUPP;
+}
+
+static int mmc_startup_v4(struct mmc *mmc)
+{
+ int err, i;
+ u64 capacity;
+ bool has_parts = false;
+ bool part_completed;
+ static const u32 mmc_versions[] = {
+ MMC_VERSION_4,
+ MMC_VERSION_4_1,
+ MMC_VERSION_4_2,
+ MMC_VERSION_4_3,
+ MMC_VERSION_4_41,
+ MMC_VERSION_4_5,
+ MMC_VERSION_5_0,
+ MMC_VERSION_5_1
+ };
+
+ ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
+
+ if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
+ return 0;
+
+ /* check ext_csd version and capacity */
+ err = mmc_send_ext_csd(mmc, ext_csd);
+ if (err)
+ goto error;
+
+ /* store the ext csd for future reference */
+ if (!mmc->ext_csd)
+ mmc->ext_csd = malloc(MMC_MAX_BLOCK_LEN);
+ if (!mmc->ext_csd)
+ return -ENOMEM;
+ memcpy(mmc->ext_csd, ext_csd, MMC_MAX_BLOCK_LEN);
+
+ if (ext_csd[EXT_CSD_REV] > ARRAY_SIZE(mmc_versions))
+ return -EINVAL;
+
+ mmc->version = mmc_versions[ext_csd[EXT_CSD_REV]];
+
+ if (mmc->version >= MMC_VERSION_4_2) {
+ /*
+ * According to the JEDEC Standard, the value of
+ * ext_csd's capacity is valid if the value is more
+ * than 2GB
+ */
+ capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
+ | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
+ | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
+ | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
+ capacity *= MMC_MAX_BLOCK_LEN;
+ if ((capacity >> 20) > 2 * 1024)
+ mmc->capacity_user = capacity;
+ }
+
+ /* The partition data may be non-zero but it is only
+ * effective if PARTITION_SETTING_COMPLETED is set in
+ * EXT_CSD, so ignore any data if this bit is not set,
+ * except for enabling the high-capacity group size
+ * definition (see below).
+ */
+ part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
+ EXT_CSD_PARTITION_SETTING_COMPLETED);
+
+ /* store the partition info of emmc */
+ mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
+ if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
+ ext_csd[EXT_CSD_BOOT_MULT])
+ mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
+ if (part_completed &&
+ (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
+ mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
+
+ mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
+
+ mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
+
+ for (i = 0; i < 4; i++) {
+ int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
+ uint mult = (ext_csd[idx + 2] << 16) +
+ (ext_csd[idx + 1] << 8) + ext_csd[idx];
+ if (mult)
+ has_parts = true;
+ if (!part_completed)
+ continue;
+ mmc->capacity_gp[i] = mult;
+ mmc->capacity_gp[i] *=
+ ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
+ mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
+ mmc->capacity_gp[i] <<= 19;
+ }
+
+#ifndef CONFIG_SPL_BUILD
+ if (part_completed) {
+ mmc->enh_user_size =
+ (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
+ (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
+ ext_csd[EXT_CSD_ENH_SIZE_MULT];
+ mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
+ mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
+ mmc->enh_user_size <<= 19;
+ mmc->enh_user_start =
+ (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
+ (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
+ (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
+ ext_csd[EXT_CSD_ENH_START_ADDR];
+ if (mmc->high_capacity)
+ mmc->enh_user_start <<= 9;
+ }
+#endif
+
+ /*
+ * Host needs to enable ERASE_GRP_DEF bit if device is
+ * partitioned. This bit will be lost every time after a reset
+ * or power off. This will affect erase size.
+ */
+ if (part_completed)
+ has_parts = true;
+ if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
+ (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
+ has_parts = true;
+ if (has_parts) {
+ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+ EXT_CSD_ERASE_GROUP_DEF, 1);
+
+ if (err)
+ goto error;
+
+ ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
+ }
+
+ if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
+#if CONFIG_IS_ENABLED(MMC_WRITE)
+ /* Read out group size from ext_csd */
+ mmc->erase_grp_size =
+ ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
+#endif
+ /*
+ * if high capacity and partition setting completed
+ * SEC_COUNT is valid even if it is smaller than 2 GiB
+ * JEDEC Standard JESD84-B45, 6.2.4
+ */
+ if (mmc->high_capacity && part_completed) {
+ capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
+ (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
+ (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
+ (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
+ capacity *= MMC_MAX_BLOCK_LEN;
+ mmc->capacity_user = capacity;
+ }
+ }
+#if CONFIG_IS_ENABLED(MMC_WRITE)
+ else {
+ /* Calculate the group size from the csd value. */
+ int erase_gsz, erase_gmul;
+
+ erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
+ erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
+ mmc->erase_grp_size = (erase_gsz + 1)
+ * (erase_gmul + 1);
+ }
+#endif
+#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
+ mmc->hc_wp_grp_size = 1024
+ * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
+ * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
+#endif
+
+ mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
+
+ return 0;
+error:
+ if (mmc->ext_csd) {
+ free(mmc->ext_csd);
+ mmc->ext_csd = NULL;
+ }
+ return err;
}
static int mmc_startup(struct mmc *mmc)
{
int err, i;
uint mult, freq;
- u64 cmult, csize, capacity;
+ u64 cmult, csize;
struct mmc_cmd cmd;
- ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
- ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
- bool has_parts = false;
- bool part_completed;
struct blk_desc *bdesc;
#ifdef CONFIG_MMC_SPI_CRC_ON
@@ -1121,7 +2131,6 @@ static int mmc_startup(struct mmc *mmc)
cmd.resp_type = MMC_RSP_R1;
cmd.cmdarg = 1;
err = mmc_send_cmd(mmc, &cmd, NULL);
-
if (err)
return err;
}
@@ -1135,6 +2144,21 @@ static int mmc_startup(struct mmc *mmc)
err = mmc_send_cmd(mmc, &cmd, NULL);
+#ifdef CONFIG_MMC_QUIRKS
+ if (err && (mmc->quirks & MMC_QUIRK_RETRY_SEND_CID)) {
+ int retries = 4;
+ /*
+ * It has been seen that SEND_CID may fail on the first
+ * attempt, let's try a few more time
+ */
+ do {
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+ if (!err)
+ break;
+ } while (retries--);
+ }
+#endif
+
if (err)
return err;
@@ -1203,15 +2227,18 @@ static int mmc_startup(struct mmc *mmc)
freq = fbase[(cmd.response[0] & 0x7)];
mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
- mmc->tran_speed = freq * mult;
+ mmc->legacy_speed = freq * mult;
+ mmc_select_mode(mmc, MMC_LEGACY);
mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
+#if CONFIG_IS_ENABLED(MMC_WRITE)
if (IS_SD(mmc))
mmc->write_bl_len = mmc->read_bl_len;
else
mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
+#endif
if (mmc->high_capacity) {
csize = (mmc->csd[1] & 0x3f) << 16
@@ -1233,15 +2260,17 @@ static int mmc_startup(struct mmc *mmc)
if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
+#if CONFIG_IS_ENABLED(MMC_WRITE)
if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
+#endif
if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
cmd.cmdidx = MMC_CMD_SET_DSR;
cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
cmd.resp_type = MMC_RSP_NONE;
if (mmc_send_cmd(mmc, &cmd, NULL))
- printf("MMC: SET_DSR failed\n");
+ pr_warn("MMC: SET_DSR failed\n");
}
/* Select the card, and put it into Transfer Mode */
@@ -1258,299 +2287,42 @@ static int mmc_startup(struct mmc *mmc)
/*
* For SD, its erase group is always one sector
*/
+#if CONFIG_IS_ENABLED(MMC_WRITE)
mmc->erase_grp_size = 1;
+#endif
mmc->part_config = MMCPART_NOAVAILABLE;
- if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
- /* check ext_csd version and capacity */
- err = mmc_send_ext_csd(mmc, ext_csd);
- if (err)
- return err;
- if (ext_csd[EXT_CSD_REV] >= 2) {
- /*
- * According to the JEDEC Standard, the value of
- * ext_csd's capacity is valid if the value is more
- * than 2GB
- */
- capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
- | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
- | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
- | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
- capacity *= MMC_MAX_BLOCK_LEN;
- if ((capacity >> 20) > 2 * 1024)
- mmc->capacity_user = capacity;
- }
- switch (ext_csd[EXT_CSD_REV]) {
- case 1:
- mmc->version = MMC_VERSION_4_1;
- break;
- case 2:
- mmc->version = MMC_VERSION_4_2;
- break;
- case 3:
- mmc->version = MMC_VERSION_4_3;
- break;
- case 5:
- mmc->version = MMC_VERSION_4_41;
- break;
- case 6:
- mmc->version = MMC_VERSION_4_5;
- break;
- case 7:
- mmc->version = MMC_VERSION_5_0;
- break;
- case 8:
- mmc->version = MMC_VERSION_5_1;
- break;
- }
-
- /* The partition data may be non-zero but it is only
- * effective if PARTITION_SETTING_COMPLETED is set in
- * EXT_CSD, so ignore any data if this bit is not set,
- * except for enabling the high-capacity group size
- * definition (see below). */
- part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
- EXT_CSD_PARTITION_SETTING_COMPLETED);
-
- /* store the partition info of emmc */
- mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
- if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
- ext_csd[EXT_CSD_BOOT_MULT])
- mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
- if (part_completed &&
- (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
- mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
-
- mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
-
- mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
-
- for (i = 0; i < 4; i++) {
- int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
- uint mult = (ext_csd[idx + 2] << 16) +
- (ext_csd[idx + 1] << 8) + ext_csd[idx];
- if (mult)
- has_parts = true;
- if (!part_completed)
- continue;
- mmc->capacity_gp[i] = mult;
- mmc->capacity_gp[i] *=
- ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
- mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
- mmc->capacity_gp[i] <<= 19;
- }
-
- if (part_completed) {
- mmc->enh_user_size =
- (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) +
- (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) +
- ext_csd[EXT_CSD_ENH_SIZE_MULT];
- mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
- mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
- mmc->enh_user_size <<= 19;
- mmc->enh_user_start =
- (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) +
- (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) +
- (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) +
- ext_csd[EXT_CSD_ENH_START_ADDR];
- if (mmc->high_capacity)
- mmc->enh_user_start <<= 9;
- }
-
- /*
- * Host needs to enable ERASE_GRP_DEF bit if device is
- * partitioned. This bit will be lost every time after a reset
- * or power off. This will affect erase size.
- */
- if (part_completed)
- has_parts = true;
- if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
- (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
- has_parts = true;
- if (has_parts) {
- err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
- EXT_CSD_ERASE_GROUP_DEF, 1);
-
- if (err)
- return err;
- else
- ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
- }
-
- if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
- /* Read out group size from ext_csd */
- mmc->erase_grp_size =
- ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
- /*
- * if high capacity and partition setting completed
- * SEC_COUNT is valid even if it is smaller than 2 GiB
- * JEDEC Standard JESD84-B45, 6.2.4
- */
- if (mmc->high_capacity && part_completed) {
- capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
- (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
- (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
- (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
- capacity *= MMC_MAX_BLOCK_LEN;
- mmc->capacity_user = capacity;
- }
- } else {
- /* Calculate the group size from the csd value. */
- int erase_gsz, erase_gmul;
- erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
- erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
- mmc->erase_grp_size = (erase_gsz + 1)
- * (erase_gmul + 1);
- }
-
- mmc->hc_wp_grp_size = 1024
- * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
- * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
-
- mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
- }
-
- err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
+ err = mmc_startup_v4(mmc);
if (err)
return err;
- if (IS_SD(mmc))
- err = sd_change_freq(mmc);
- else
- err = mmc_change_freq(mmc);
-
+ err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
if (err)
return err;
- /* Restrict card's capabilities by what the host can do */
- mmc->card_caps &= mmc->cfg->host_caps;
-
if (IS_SD(mmc)) {
- if (mmc->card_caps & MMC_MODE_4BIT) {
- cmd.cmdidx = MMC_CMD_APP_CMD;
- cmd.resp_type = MMC_RSP_R1;
- cmd.cmdarg = mmc->rca << 16;
-
- err = mmc_send_cmd(mmc, &cmd, NULL);
- if (err)
- return err;
-
- cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
- cmd.resp_type = MMC_RSP_R1;
- cmd.cmdarg = 2;
- err = mmc_send_cmd(mmc, &cmd, NULL);
- if (err)
- return err;
-
- mmc_set_bus_width(mmc, 4);
- }
-
- err = sd_read_ssr(mmc);
+ err = sd_get_capabilities(mmc);
if (err)
return err;
-
- if (mmc->card_caps & MMC_MODE_HS)
- mmc->tran_speed = 50000000;
- else
- mmc->tran_speed = 25000000;
- } else if (mmc->version >= MMC_VERSION_4) {
- /* Only version 4 of MMC supports wider bus widths */
- int idx;
-
- /* An array of possible bus widths in order of preference */
- static unsigned ext_csd_bits[] = {
- EXT_CSD_DDR_BUS_WIDTH_8,
- EXT_CSD_DDR_BUS_WIDTH_4,
- EXT_CSD_BUS_WIDTH_8,
- EXT_CSD_BUS_WIDTH_4,
- EXT_CSD_BUS_WIDTH_1,
- };
-
- /* An array to map CSD bus widths to host cap bits */
- static unsigned ext_to_hostcaps[] = {
- [EXT_CSD_DDR_BUS_WIDTH_4] =
- MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
- [EXT_CSD_DDR_BUS_WIDTH_8] =
- MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
- [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
- [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
- };
-
- /* An array to map chosen bus width to an integer */
- static unsigned widths[] = {
- 8, 4, 8, 4, 1,
- };
-
- for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
- unsigned int extw = ext_csd_bits[idx];
- unsigned int caps = ext_to_hostcaps[extw];
-
- /*
- * If the bus width is still not changed,
- * don't try to set the default again.
- * Otherwise, recover from switch attempts
- * by switching to 1-bit bus width.
- */
- if (extw == EXT_CSD_BUS_WIDTH_1 &&
- mmc->bus_width == 1) {
- err = 0;
- break;
- }
-
- /*
- * Check to make sure the card and controller support
- * these capabilities
- */
- if ((mmc->card_caps & caps) != caps)
- continue;
-
- err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
- EXT_CSD_BUS_WIDTH, extw);
-
- if (err)
- continue;
-
- mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
- mmc_set_bus_width(mmc, widths[idx]);
-
- err = mmc_send_ext_csd(mmc, test_csd);
-
- if (err)
- continue;
-
- /* Only compare read only fields */
- if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
- == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
- ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
- == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
- ext_csd[EXT_CSD_REV]
- == test_csd[EXT_CSD_REV] &&
- ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
- == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
- memcmp(&ext_csd[EXT_CSD_SEC_CNT],
- &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
- break;
- else
- err = -EBADMSG;
- }
-
+ err = sd_select_mode_and_width(mmc, mmc->card_caps);
+ } else {
+ err = mmc_get_capabilities(mmc);
if (err)
return err;
-
- if (mmc->card_caps & MMC_MODE_HS) {
- if (mmc->card_caps & MMC_MODE_HS_52MHz)
- mmc->tran_speed = 52000000;
- else
- mmc->tran_speed = 26000000;
- }
+ mmc_select_mode_and_width(mmc, mmc->card_caps);
}
- mmc_set_clock(mmc, mmc->tran_speed);
+ if (err)
+ return err;
+
+ mmc->best_mode = mmc->selected_mode;
/* Fix the block length for DDR mode */
if (mmc->ddr_mode) {
mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
+#if CONFIG_IS_ENABLED(MMC_WRITE)
mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
+#endif
}
/* fill in device description */
@@ -1618,22 +2390,18 @@ __weak void board_mmc_power_init(void)
static int mmc_power_init(struct mmc *mmc)
{
#if CONFIG_IS_ENABLED(DM_MMC)
-#if defined(CONFIG_DM_REGULATOR) && !defined(CONFIG_SPL_BUILD)
- struct udevice *vmmc_supply;
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
int ret;
ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
- &vmmc_supply);
- if (ret) {
+ &mmc->vmmc_supply);
+ if (ret)
debug("%s: No vmmc supply\n", mmc->dev->name);
- return 0;
- }
- ret = regulator_set_enable(vmmc_supply, true);
- if (ret) {
- puts("Error enabling VMMC supply\n");
- return ret;
- }
+ ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
+ &mmc->vqmmc_supply);
+ if (ret)
+ debug("%s: No vqmmc supply\n", mmc->dev->name);
#endif
#else /* !CONFIG_DM_MMC */
/*
@@ -1645,13 +2413,92 @@ static int mmc_power_init(struct mmc *mmc)
return 0;
}
+/*
+ * put the host in the initial state:
+ * - turn on Vdd (card power supply)
+ * - configure the bus width and clock to minimal values
+ */
+static void mmc_set_initial_state(struct mmc *mmc)
+{
+ int err;
+
+ /* First try to set 3.3V. If it fails set to 1.8V */
+ err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
+ if (err != 0)
+ err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
+ if (err != 0)
+ pr_warn("mmc: failed to set signal voltage\n");
+
+ mmc_select_mode(mmc, MMC_LEGACY);
+ mmc_set_bus_width(mmc, 1);
+ mmc_set_clock(mmc, 0, false);
+}
+
+static int mmc_power_on(struct mmc *mmc)
+{
+#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
+ if (mmc->vmmc_supply) {
+ int ret = regulator_set_enable(mmc->vmmc_supply, true);
+
+ if (ret) {
+ puts("Error enabling VMMC supply\n");
+ return ret;
+ }
+ }
+#endif
+ return 0;
+}
+
+static int mmc_power_off(struct mmc *mmc)
+{
+ mmc_set_clock(mmc, 0, true);
+#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
+ if (mmc->vmmc_supply) {
+ int ret = regulator_set_enable(mmc->vmmc_supply, false);
+
+ if (ret) {
+ debug("Error disabling VMMC supply\n");
+ return ret;
+ }
+ }
+#endif
+ return 0;
+}
+
+static int mmc_power_cycle(struct mmc *mmc)
+{
+ int ret;
+
+ ret = mmc_power_off(mmc);
+ if (ret)
+ return ret;
+ /*
+ * SD spec recommends at least 1ms of delay. Let's wait for 2ms
+ * to be on the safer side.
+ */
+ udelay(2000);
+ return mmc_power_on(mmc);
+}
+
int mmc_start_init(struct mmc *mmc)
{
bool no_card;
+ bool uhs_en = supports_uhs(mmc->cfg->host_caps);
int err;
+ /*
+ * all hosts are capable of 1 bit bus-width and able to use the legacy
+ * timings.
+ */
+ mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(SD_LEGACY) |
+ MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT;
+
+#if !defined(CONFIG_MMC_BROKEN_CD)
/* we pretend there's no card when init is NULL */
no_card = mmc_getcd(mmc) == 0;
+#else
+ no_card = 0;
+#endif
#if !CONFIG_IS_ENABLED(DM_MMC)
no_card = no_card || (mmc->cfg->ops->init == NULL);
#endif
@@ -1673,6 +2520,26 @@ int mmc_start_init(struct mmc *mmc)
if (err)
return err;
+#ifdef CONFIG_MMC_QUIRKS
+ mmc->quirks = MMC_QUIRK_RETRY_SET_BLOCKLEN |
+ MMC_QUIRK_RETRY_SEND_CID;
+#endif
+
+ err = mmc_power_cycle(mmc);
+ if (err) {
+ /*
+ * if power cycling is not supported, we should not try
+ * to use the UHS modes, because we wouldn't be able to
+ * recover from an error during the UHS initialization.
+ */
+ debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
+ uhs_en = false;
+ mmc->host_caps &= ~UHS_CAPS;
+ err = mmc_power_on(mmc);
+ }
+ if (err)
+ return err;
+
#if CONFIG_IS_ENABLED(DM_MMC)
/* The device has already been probed ready for use */
#else
@@ -1682,8 +2549,10 @@ int mmc_start_init(struct mmc *mmc)
return err;
#endif
mmc->ddr_mode = 0;
- mmc_set_bus_width(mmc, 1);
- mmc_set_clock(mmc, 1);
+
+retry:
+ mmc_set_initial_state(mmc);
+ mmc_send_init_stream(mmc);
/* Reset the Card */
err = mmc_go_idle(mmc);
@@ -1698,7 +2567,12 @@ int mmc_start_init(struct mmc *mmc)
err = mmc_send_if_cond(mmc);
/* Now try to get the SD card's operating condition */
- err = sd_send_op_cond(mmc);
+ err = sd_send_op_cond(mmc, uhs_en);
+ if (err && uhs_en) {
+ uhs_en = false;
+ mmc_power_cycle(mmc);
+ goto retry;
+ }
/* If the command timed out, we check for an MMC card */
if (err == -ETIMEDOUT) {
@@ -1706,7 +2580,7 @@ int mmc_start_init(struct mmc *mmc)
if (err) {
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
- printf("Card did not respond to voltage select!\n");
+ pr_err("Card did not respond to voltage select!\n");
#endif
return -EOPNOTSUPP;
}
@@ -1812,7 +2686,7 @@ static int mmc_probe(bd_t *bis)
uclass_foreach_dev(dev, uc) {
ret = device_probe(dev);
if (ret)
- printf("%s - probe failed: %d\n", dev->name, ret);
+ pr_err("%s - probe failed: %d\n", dev->name, ret);
}
return 0;
diff --git a/drivers/mmc/mmc_private.h b/drivers/mmc/mmc_private.h
index 1290eed590..a9be4b0102 100644
--- a/drivers/mmc/mmc_private.h
+++ b/drivers/mmc/mmc_private.h
@@ -28,7 +28,7 @@ ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
void *dst);
#endif
-#if !(defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_SAVEENV))
+#if CONFIG_IS_ENABLED(MMC_WRITE)
#if CONFIG_IS_ENABLED(BLK)
ulong mmc_bwrite(struct udevice *dev, lbaint_t start, lbaint_t blkcnt,
@@ -40,7 +40,7 @@ ulong mmc_bwrite(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
ulong mmc_berase(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt);
#endif
-#else /* CONFIG_SPL_BUILD and CONFIG_SPL_SAVEENV is not defined */
+#else /* CONFIG_SPL_MMC_WRITE is not defined */
/* declare dummies to reduce code size. */
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index efa43896fc..b12d6d9102 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -25,12 +25,13 @@
#include <config.h>
#include <common.h>
#include <malloc.h>
+#include <memalign.h>
#include <mmc.h>
#include <part.h>
#include <i2c.h>
-#include <twl4030.h>
-#include <twl6030.h>
+#if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
#include <palmas.h>
+#endif
#include <asm/io.h>
#include <asm/arch/mmc_host_def.h>
#if !defined(CONFIG_SOC_KEYSTONE)
@@ -56,10 +57,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define SYSCTL_SRC (1 << 25)
#define SYSCTL_SRD (1 << 26)
-struct omap2_mmc_platform_config {
- u32 reg_offset;
-};
-
struct omap_hsmmc_data {
struct hsmmc *base_addr;
#if !CONFIG_IS_ENABLED(DM_MMC)
@@ -75,11 +72,45 @@ struct omap_hsmmc_data {
int wp_gpio;
#endif
#endif
+ u8 controller_flags;
+#ifndef CONFIG_OMAP34XX
+ struct omap_hsmmc_adma_desc *adma_desc_table;
+ uint desc_slot;
+#endif
+};
+
+#ifndef CONFIG_OMAP34XX
+struct omap_hsmmc_adma_desc {
+ u8 attr;
+ u8 reserved;
+ u16 len;
+ u32 addr;
};
+#define ADMA_MAX_LEN 63488
+
+/* Decriptor table defines */
+#define ADMA_DESC_ATTR_VALID BIT(0)
+#define ADMA_DESC_ATTR_END BIT(1)
+#define ADMA_DESC_ATTR_INT BIT(2)
+#define ADMA_DESC_ATTR_ACT1 BIT(4)
+#define ADMA_DESC_ATTR_ACT2 BIT(5)
+
+#define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
+#define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
+#endif
+
/* If we fail after 1 second wait, something is really bad */
#define MAX_RETRY_MS 1000
+/* DMA transfers can take a long time if a lot a data is transferred.
+ * The timeout must take in account the amount of data. Let's assume
+ * that the time will never exceed 333 ms per MB (in other word we assume
+ * that the bandwidth is always above 3MB/s).
+ */
+#define DMA_TIMEOUT_PER_MB 333
+#define OMAP_HSMMC_USE_ADMA BIT(2)
+
static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
unsigned int siz);
@@ -246,6 +277,11 @@ static int omap_hsmmc_init_setup(struct mmc *mmc)
return -ETIMEDOUT;
}
}
+#ifndef CONFIG_OMAP34XX
+ reg_val = readl(&mmc_base->hl_hwinfo);
+ if (reg_val & MADMA_EN)
+ priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
+#endif
writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
&mmc_base->capa);
@@ -258,7 +294,7 @@ static int omap_hsmmc_init_setup(struct mmc *mmc)
dsor = 240;
mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
- (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
+ (ICE_STOP | DTO_15THDTO));
mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
(dsor << CLKD_OFFSET) | ICE_OSCILLATE);
start = get_timer(0);
@@ -273,8 +309,8 @@ static int omap_hsmmc_init_setup(struct mmc *mmc)
writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
- IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
- &mmc_base->ie);
+ IE_CEB | IE_CCRC | IE_ADMAE | IE_CTO | IE_BRR | IE_BWR | IE_TC |
+ IE_CC, &mmc_base->ie);
mmc_init_stream(mmc_base);
@@ -326,6 +362,118 @@ static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
}
}
}
+
+#ifndef CONFIG_OMAP34XX
+static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
+{
+ struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
+ struct omap_hsmmc_adma_desc *desc;
+ u8 attr;
+
+ desc = &priv->adma_desc_table[priv->desc_slot];
+
+ attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
+ if (!end)
+ priv->desc_slot++;
+ else
+ attr |= ADMA_DESC_ATTR_END;
+
+ desc->len = len;
+ desc->addr = (u32)buf;
+ desc->reserved = 0;
+ desc->attr = attr;
+}
+
+static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
+ struct mmc_data *data)
+{
+ uint total_len = data->blocksize * data->blocks;
+ uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
+ struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
+ int i = desc_count;
+ char *buf;
+
+ priv->desc_slot = 0;
+ priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
+ memalign(ARCH_DMA_MINALIGN, desc_count *
+ sizeof(struct omap_hsmmc_adma_desc));
+
+ if (data->flags & MMC_DATA_READ)
+ buf = data->dest;
+ else
+ buf = (char *)data->src;
+
+ while (--i) {
+ omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
+ buf += ADMA_MAX_LEN;
+ total_len -= ADMA_MAX_LEN;
+ }
+
+ omap_hsmmc_adma_desc(mmc, buf, total_len, true);
+
+ flush_dcache_range((long)priv->adma_desc_table,
+ (long)priv->adma_desc_table +
+ ROUND(desc_count *
+ sizeof(struct omap_hsmmc_adma_desc),
+ ARCH_DMA_MINALIGN));
+}
+
+static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
+{
+ struct hsmmc *mmc_base;
+ struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
+ u32 val;
+ char *buf;
+
+ mmc_base = priv->base_addr;
+ omap_hsmmc_prepare_adma_table(mmc, data);
+
+ if (data->flags & MMC_DATA_READ)
+ buf = data->dest;
+ else
+ buf = (char *)data->src;
+
+ val = readl(&mmc_base->hctl);
+ val |= DMA_SELECT;
+ writel(val, &mmc_base->hctl);
+
+ val = readl(&mmc_base->con);
+ val |= DMA_MASTER;
+ writel(val, &mmc_base->con);
+
+ writel((u32)priv->adma_desc_table, &mmc_base->admasal);
+
+ flush_dcache_range((u32)buf,
+ (u32)buf +
+ ROUND(data->blocksize * data->blocks,
+ ARCH_DMA_MINALIGN));
+}
+
+static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
+{
+ struct hsmmc *mmc_base;
+ struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
+ u32 val;
+
+ mmc_base = priv->base_addr;
+
+ val = readl(&mmc_base->con);
+ val &= ~DMA_MASTER;
+ writel(val, &mmc_base->con);
+
+ val = readl(&mmc_base->hctl);
+ val &= ~DMA_SELECT;
+ writel(val, &mmc_base->hctl);
+
+ kfree(priv->adma_desc_table);
+}
+#else
+#define omap_hsmmc_adma_desc
+#define omap_hsmmc_prepare_adma_table
+#define omap_hsmmc_prepare_data
+#define omap_hsmmc_dma_cleanup
+#endif
+
#if !CONFIG_IS_ENABLED(DM_MMC)
static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
@@ -336,12 +484,20 @@ static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
struct mmc_data *data)
{
struct omap_hsmmc_data *priv = dev_get_priv(dev);
+#ifndef CONFIG_OMAP34XX
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct mmc *mmc = upriv->mmc;
+#endif
#endif
struct hsmmc *mmc_base;
unsigned int flags, mmc_stat;
ulong start;
mmc_base = priv->base_addr;
+
+ if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
+ return 0;
+
start = get_timer(0);
while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
if (get_timer(0) - start > MAX_RETRY_MS) {
@@ -388,7 +544,8 @@ static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
/* enable default flags */
flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
- MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
+ MSBS_SGLEBLK);
+ flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
if (cmd->resp_type & MMC_RSP_CRC)
flags |= CCCE_CHECK;
@@ -398,7 +555,7 @@ static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
if (data) {
if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
(cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
- flags |= (MSBS_MULTIBLK | BCE_ENABLE);
+ flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
data->blocksize = 512;
writel(data->blocksize | (data->blocks << 16),
&mmc_base->blk);
@@ -409,6 +566,14 @@ static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
flags |= (DP_DATA | DDIR_READ);
else
flags |= (DP_DATA | DDIR_WRITE);
+
+#ifndef CONFIG_OMAP34XX
+ if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
+ !mmc_is_tuning_cmd(cmd->cmdidx)) {
+ omap_hsmmc_prepare_data(mmc, data);
+ flags |= DE_ENABLE;
+ }
+#endif
}
writel(cmd->cmdarg, &mmc_base->arg);
@@ -418,7 +583,7 @@ static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
start = get_timer(0);
do {
mmc_stat = readl(&mmc_base->stat);
- if (get_timer(0) - start > MAX_RETRY_MS) {
+ if (get_timer(start) > MAX_RETRY_MS) {
printf("%s : timeout: No status update\n", __func__);
return -ETIMEDOUT;
}
@@ -445,6 +610,41 @@ static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
}
}
+#ifndef CONFIG_OMAP34XX
+ if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
+ !mmc_is_tuning_cmd(cmd->cmdidx)) {
+ u32 sz_mb, timeout;
+
+ if (mmc_stat & IE_ADMAE) {
+ omap_hsmmc_dma_cleanup(mmc);
+ return -EIO;
+ }
+
+ sz_mb = DIV_ROUND_UP(data->blocksize * data->blocks, 1 << 20);
+ timeout = sz_mb * DMA_TIMEOUT_PER_MB;
+ if (timeout < MAX_RETRY_MS)
+ timeout = MAX_RETRY_MS;
+
+ start = get_timer(0);
+ do {
+ mmc_stat = readl(&mmc_base->stat);
+ if (mmc_stat & TC_MASK) {
+ writel(readl(&mmc_base->stat) | TC_MASK,
+ &mmc_base->stat);
+ break;
+ }
+ if (get_timer(start) > timeout) {
+ printf("%s : DMA timeout: No status update\n",
+ __func__);
+ return -ETIMEDOUT;
+ }
+ } while (1);
+
+ omap_hsmmc_dma_cleanup(mmc);
+ return 0;
+ }
+#endif
+
if (data && (data->flags & MMC_DATA_READ)) {
mmc_read_data(mmc_base, data->dest,
data->blocksize * data->blocks);
@@ -612,7 +812,7 @@ static int omap_hsmmc_set_ios(struct udevice *dev)
}
mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
- (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
+ (ICE_STOP | DTO_15THDTO));
mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
(dsor << CLKD_OFFSET) | ICE_OSCILLATE);
@@ -802,15 +1002,13 @@ static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
{
struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
struct mmc_config *cfg = &plat->cfg;
- struct omap2_mmc_platform_config *data =
- (struct omap2_mmc_platform_config *)dev_get_driver_data(dev);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
int val;
plat->base_addr = map_physmem(devfdt_get_addr(dev),
sizeof(struct hsmmc *),
- MAP_NOCACHE) + data->reg_offset;
+ MAP_NOCACHE);
cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
val = fdtdec_get_int(fdt, node, "bus-width", -1);
@@ -886,31 +1084,10 @@ static int omap_hsmmc_probe(struct udevice *dev)
}
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
-static const struct omap2_mmc_platform_config omap3_mmc_pdata = {
- .reg_offset = 0,
-};
-
-static const struct omap2_mmc_platform_config am33xx_mmc_pdata = {
- .reg_offset = 0x100,
-};
-
-static const struct omap2_mmc_platform_config omap4_mmc_pdata = {
- .reg_offset = 0x100,
-};
-
static const struct udevice_id omap_hsmmc_ids[] = {
- {
- .compatible = "ti,omap3-hsmmc",
- .data = (ulong)&omap3_mmc_pdata
- },
- {
- .compatible = "ti,omap4-hsmmc",
- .data = (ulong)&omap4_mmc_pdata
- },
- {
- .compatible = "ti,am33xx-hsmmc",
- .data = (ulong)&am33xx_mmc_pdata
- },
+ { .compatible = "ti,omap3-hsmmc" },
+ { .compatible = "ti,omap4-hsmmc" },
+ { .compatible = "ti,am33xx-hsmmc" },
{ }
};
#endif
diff --git a/drivers/mmc/sandbox_mmc.c b/drivers/mmc/sandbox_mmc.c
index fdb29a5505..8a5d256c11 100644
--- a/drivers/mmc/sandbox_mmc.c
+++ b/drivers/mmc/sandbox_mmc.c
@@ -48,9 +48,12 @@ static int sandbox_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
cmd->response[1] = 10 << 16; /* 1 << block_len */
break;
case SD_CMD_SWITCH_FUNC: {
+ if (!data)
+ break;
u32 *resp = (u32 *)data->dest;
-
resp[7] = cpu_to_be32(SD_HIGHSPEED_BUSY);
+ if ((cmd->cmdarg & 0xF) == UHS_SDR12_BUS_SPEED)
+ resp[4] = (cmd->cmdarg & 0xF) << 24;
break;
}
case MMC_CMD_READ_SINGLE_BLOCK:
diff --git a/drivers/mmc/sdhci-cadence.c b/drivers/mmc/sdhci-cadence.c
index 72d1c646a2..0b174fc44d 100644
--- a/drivers/mmc/sdhci-cadence.c
+++ b/drivers/mmc/sdhci-cadence.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <dm.h>
+#include <linux/bitfield.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/sizes.h>
@@ -19,15 +20,14 @@
#define SDHCI_CDNS_HRS04_ACK BIT(26)
#define SDHCI_CDNS_HRS04_RD BIT(25)
#define SDHCI_CDNS_HRS04_WR BIT(24)
-#define SDHCI_CDNS_HRS04_RDATA_SHIFT 16
-#define SDHCI_CDNS_HRS04_WDATA_SHIFT 8
-#define SDHCI_CDNS_HRS04_ADDR_SHIFT 0
+#define SDHCI_CDNS_HRS04_RDATA GENMASK(23, 16)
+#define SDHCI_CDNS_HRS04_WDATA GENMASK(15, 8)
+#define SDHCI_CDNS_HRS04_ADDR GENMASK(5, 0)
#define SDHCI_CDNS_HRS06 0x18 /* eMMC control */
#define SDHCI_CDNS_HRS06_TUNE_UP BIT(15)
-#define SDHCI_CDNS_HRS06_TUNE_SHIFT 8
-#define SDHCI_CDNS_HRS06_TUNE_MASK 0x3f
-#define SDHCI_CDNS_HRS06_MODE_MASK 0x7
+#define SDHCI_CDNS_HRS06_TUNE GENMASK(13, 8)
+#define SDHCI_CDNS_HRS06_MODE GENMASK(2, 0)
#define SDHCI_CDNS_HRS06_MODE_SD 0x0
#define SDHCI_CDNS_HRS06_MODE_MMC_SDR 0x2
#define SDHCI_CDNS_HRS06_MODE_MMC_DDR 0x3
@@ -52,6 +52,13 @@
#define SDHCI_CDNS_PHY_DLY_HSMMC 0x0c
#define SDHCI_CDNS_PHY_DLY_STROBE 0x0d
+/*
+ * The tuned val register is 6 bit-wide, but not the whole of the range is
+ * available. The range 0-42 seems to be available (then 43 wraps around to 0)
+ * but I am not quite sure if it is official. Use only 0 to 39 for safety.
+ */
+#define SDHCI_CDNS_MAX_TUNING_LOOP 40
+
struct sdhci_cdns_plat {
struct mmc_config cfg;
struct mmc mmc;
@@ -84,8 +91,8 @@ static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_plat *plat,
u32 tmp;
int ret;
- tmp = (data << SDHCI_CDNS_HRS04_WDATA_SHIFT) |
- (addr << SDHCI_CDNS_HRS04_ADDR_SHIFT);
+ tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) |
+ FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr);
writel(tmp, reg);
tmp |= SDHCI_CDNS_HRS04_WR;
@@ -135,25 +142,23 @@ static void sdhci_cdns_set_control_reg(struct sdhci_host *host)
* The mode should be decided by MMC_TIMING_* like Linux, but
* U-Boot does not support timing. Use the clock frequency instead.
*/
- if (clock <= 26000000)
+ if (clock <= 26000000) {
mode = SDHCI_CDNS_HRS06_MODE_SD; /* use this for Legacy */
- else if (clock <= 52000000) {
+ } else if (clock <= 52000000) {
if (mmc->ddr_mode)
mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR;
else
mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR;
} else {
- /*
- * REVISIT:
- * The IP supports HS200/HS400, revisit once U-Boot support it
- */
- printf("unsupported frequency %d\n", clock);
- return;
+ if (mmc->ddr_mode)
+ mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400;
+ else
+ mode = SDHCI_CDNS_HRS06_MODE_MMC_HS200;
}
tmp = readl(plat->hrs_addr + SDHCI_CDNS_HRS06);
- tmp &= ~SDHCI_CDNS_HRS06_MODE_MASK;
- tmp |= mode;
+ tmp &= ~SDHCI_CDNS_HRS06_MODE;
+ tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode);
writel(tmp, plat->hrs_addr + SDHCI_CDNS_HRS06);
}
@@ -161,6 +166,69 @@ static const struct sdhci_ops sdhci_cdns_ops = {
.set_control_reg = sdhci_cdns_set_control_reg,
};
+static int sdhci_cdns_set_tune_val(struct sdhci_cdns_plat *plat,
+ unsigned int val)
+{
+ void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS06;
+ u32 tmp;
+
+ if (WARN_ON(!FIELD_FIT(SDHCI_CDNS_HRS06_TUNE, val)))
+ return -EINVAL;
+
+ tmp = readl(reg);
+ tmp &= ~SDHCI_CDNS_HRS06_TUNE;
+ tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_TUNE, val);
+ tmp |= SDHCI_CDNS_HRS06_TUNE_UP;
+ writel(tmp, reg);
+
+ return readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS06_TUNE_UP),
+ 1);
+}
+
+static int __maybe_unused sdhci_cdns_execute_tuning(struct udevice *dev,
+ unsigned int opcode)
+{
+ struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
+ struct mmc *mmc = &plat->mmc;
+ int cur_streak = 0;
+ int max_streak = 0;
+ int end_of_streak = 0;
+ int i;
+
+ /*
+ * This handler only implements the eMMC tuning that is specific to
+ * this controller. The tuning for SD timing should be handled by the
+ * SDHCI core.
+ */
+ if (!IS_MMC(mmc))
+ return -ENOTSUPP;
+
+ if (WARN_ON(opcode != MMC_CMD_SEND_TUNING_BLOCK_HS200))
+ return -EINVAL;
+
+ for (i = 0; i < SDHCI_CDNS_MAX_TUNING_LOOP; i++) {
+ if (sdhci_cdns_set_tune_val(plat, i) ||
+ mmc_send_tuning(mmc, opcode, NULL)) { /* bad */
+ cur_streak = 0;
+ } else { /* good */
+ cur_streak++;
+ if (cur_streak > max_streak) {
+ max_streak = cur_streak;
+ end_of_streak = i;
+ }
+ }
+ }
+
+ if (!max_streak) {
+ dev_err(dev, "no tuning point found\n");
+ return -EIO;
+ }
+
+ return sdhci_cdns_set_tune_val(plat, end_of_streak - max_streak / 2);
+}
+
+static struct dm_mmc_ops sdhci_cdns_mmc_ops;
+
static int sdhci_cdns_bind(struct udevice *dev)
{
struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
@@ -189,6 +257,14 @@ static int sdhci_cdns_probe(struct udevice *dev)
host->ioaddr = plat->hrs_addr + SDHCI_CDNS_SRS_BASE;
host->ops = &sdhci_cdns_ops;
host->quirks |= SDHCI_QUIRK_WAIT_SEND_CMD;
+ sdhci_cdns_mmc_ops = sdhci_ops;
+#ifdef MMC_SUPPORTS_TUNING
+ sdhci_cdns_mmc_ops.execute_tuning = sdhci_cdns_execute_tuning;
+#endif
+
+ ret = mmc_of_parse(dev, &plat->cfg);
+ if (ret)
+ return ret;
ret = sdhci_cdns_phy_init(plat, gd->fdt_blob, dev_of_offset(dev));
if (ret)
@@ -219,5 +295,5 @@ U_BOOT_DRIVER(sdhci_cdns) = {
.probe = sdhci_cdns_probe,
.priv_auto_alloc_size = sizeof(struct sdhci_host),
.platdata_auto_alloc_size = sizeof(struct sdhci_cdns_plat),
- .ops = &sdhci_ops,
+ .ops = &sdhci_cdns_mmc_ops,
};
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 11d1f0c24c..d31793a7b7 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -86,8 +86,8 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
do {
stat = sdhci_readl(host, SDHCI_INT_STATUS);
if (stat & SDHCI_INT_ERROR) {
- printf("%s: Error detected in status(0x%X)!\n",
- __func__, stat);
+ pr_debug("%s: Error detected in status(0x%X)!\n",
+ __func__, stat);
return -EIO;
}
if (!transfer_done && (stat & rdy)) {
@@ -157,7 +157,6 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
/* Timeout unit - ms */
static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
- sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
/* We shouldn't wait for data inihibit for stop commands, even
@@ -181,6 +180,8 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
udelay(1000);
}
+ sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
+
mask = SDHCI_INT_RESPONSE;
if (!(cmd->resp_type & MMC_RSP_PRESENT))
flags = SDHCI_CMD_RESP_NONE;
@@ -201,7 +202,7 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
flags |= SDHCI_CMD_DATA;
/* Set Transfer mode regarding to data flag */
- if (data != 0) {
+ if (data) {
sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
mode = SDHCI_TRNS_BLK_CNT_EN;
trans_bytes = data->blocks * data->blocksize;
@@ -249,7 +250,7 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
#ifdef CONFIG_MMC_SDHCI_SDMA
- if (data != 0) {
+ if (data) {
trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE);
flush_cache(start_addr, trans_bytes);
}
@@ -593,7 +594,7 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
cfg->voltages |= host->voltages;
- cfg->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
+ cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
/* Since Host Controller Version3.0 */
if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index d42d915f17..de1947ccc1 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -160,12 +160,12 @@ config FTMAC100
This MAC is present in Andestech SoCs.
config MVNETA
- bool "Marvell Armada 385 network interface support"
- depends on ARMADA_XP || ARMADA_38X
+ bool "Marvell Armada XP/385/3700 network interface support"
+ depends on ARMADA_XP || ARMADA_38X || ARMADA_3700
select PHYLIB
help
This driver supports the network interface units in the
- Marvell ARMADA XP and 38X SoCs
+ Marvell ARMADA XP, ARMADA 38X and ARMADA 3700 SoCs
config MVPP2
bool "Marvell Armada 375/7K/8K network interface support"
@@ -185,6 +185,13 @@ config MACB
GEM (Gigabit Ethernet MAC) found in some ARM SoC devices.
Say Y to include support for the MACB/GEM chip.
+config MACB_ZYNQ
+ bool "Cadence MACB/GEM Ethernet Interface for Xilinx Zynq"
+ depends on MACB
+ help
+ The Cadence MACB ethernet interface was used on Zynq platform.
+ Say Y to enable support for the MACB/GEM in Zynq chip.
+
config PCH_GBE
bool "Intel Platform Controller Hub EG20T GMAC driver"
depends on DM_ETH && DM_PCI
@@ -269,6 +276,12 @@ config SUN8I_EMAC
It can be found in H3/A64/A83T based SoCs and compatible with both
External and Internal PHYs.
+config SH_ETHER
+ bool "Renesas SH Ethernet MAC"
+ select PHYLIB
+ help
+ This driver supports the Ethernet for Renesas SH and ARM SoCs.
+
config XILINX_AXIEMAC
depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
select PHYLIB
@@ -373,4 +386,28 @@ config FEC2_PHY_NORXERR
The PHY does not have a RXERR line (RMII only).
(so program the FEC to ignore it).
+config SYS_DPAA_QBMAN
+ bool "Device tree fixup for QBMan on freescale SOCs"
+ depends on (ARM || PPC) && !SPL_BUILD
+ default y if ARCH_B4860 || \
+ ARCH_B4420 || \
+ ARCH_P1023 || \
+ ARCH_P2041 || \
+ ARCH_T1023 || \
+ ARCH_T1024 || \
+ ARCH_T1040 || \
+ ARCH_T1042 || \
+ ARCH_T2080 || \
+ ARCH_T2081 || \
+ ARCH_T4240 || \
+ ARCH_T4160 || \
+ ARCH_P4080 || \
+ ARCH_P3041 || \
+ ARCH_P5040 || \
+ ARCH_P5020 || \
+ ARCH_LS1043A || \
+ ARCH_LS1046A
+ help
+ QBman fixups to allow deep sleep in DPAA 1 SOCs
+
endif # NETDEVICES
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index 036d231071..6d5307128d 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -10,6 +10,7 @@
*/
#include <common.h>
+#include <clk.h>
#include <dm.h>
#include <errno.h>
#include <miiphy.h>
@@ -17,6 +18,7 @@
#include <pci.h>
#include <linux/compiler.h>
#include <linux/err.h>
+#include <linux/kernel.h>
#include <asm/io.h>
#include <power/regulator.h>
#include "designware.h"
@@ -343,6 +345,8 @@ int designware_eth_enable(struct dw_eth_dev *priv)
return 0;
}
+#define ETH_ZLEN 60
+
static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
{
struct eth_dma_regs *dma_p = priv->dma_regs_p;
@@ -369,6 +373,8 @@ static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
return -EPERM;
}
+ length = max(length, ETH_ZLEN);
+
memcpy((void *)data_start, packet, length);
/* Flush data to be sent */
@@ -661,6 +667,35 @@ int designware_eth_probe(struct udevice *dev)
u32 iobase = pdata->iobase;
ulong ioaddr;
int ret;
+#ifdef CONFIG_CLK
+ int i, err, clock_nb;
+
+ priv->clock_count = 0;
+ clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
+ if (clock_nb > 0) {
+ priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk),
+ GFP_KERNEL);
+ if (!priv->clocks)
+ return -ENOMEM;
+
+ for (i = 0; i < clock_nb; i++) {
+ err = clk_get_by_index(dev, i, &priv->clocks[i]);
+ if (err < 0)
+ break;
+
+ err = clk_enable(&priv->clocks[i]);
+ if (err) {
+ pr_err("failed to enable clock %d\n", i);
+ clk_free(&priv->clocks[i]);
+ goto clk_err;
+ }
+ priv->clock_count++;
+ }
+ } else if (clock_nb != -ENOENT) {
+ pr_err("failed to get clock phandle(%d)\n", clock_nb);
+ return clock_nb;
+ }
+#endif
#if defined(CONFIG_DM_REGULATOR)
struct udevice *phy_supply;
@@ -707,6 +742,15 @@ int designware_eth_probe(struct udevice *dev)
debug("%s, ret=%d\n", __func__, ret);
return ret;
+
+#ifdef CONFIG_CLK
+clk_err:
+ ret = clk_release_all(priv->clocks, priv->clock_count);
+ if (ret)
+ pr_err("failed to disable all clocks\n");
+
+ return err;
+#endif
}
static int designware_eth_remove(struct udevice *dev)
@@ -717,7 +761,11 @@ static int designware_eth_remove(struct udevice *dev)
mdio_unregister(priv->bus);
mdio_free(priv->bus);
+#ifdef CONFIG_CLK
+ return clk_release_all(priv->clocks, priv->clock_count);
+#else
return 0;
+#endif
}
const struct eth_ops designware_eth_ops = {
diff --git a/drivers/net/designware.h b/drivers/net/designware.h
index 7992d0ebee..252cd24f1a 100644
--- a/drivers/net/designware.h
+++ b/drivers/net/designware.h
@@ -239,6 +239,10 @@ struct dw_eth_dev {
#ifdef CONFIG_DM_GPIO
struct gpio_desc reset_gpio;
#endif
+#ifdef CONFIG_CLK
+ struct clk *clocks; /* clock list */
+ int clock_count; /* number of clock in clock list */
+#endif
struct phy_device *phydev;
struct mii_dev *bus;
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index f9373db0b9..e62aefcd0d 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -52,6 +52,22 @@ DECLARE_GLOBAL_DATA_PTR;
#define MACB_TX_TIMEOUT 1000
#define MACB_AUTONEG_TIMEOUT 5000000
+#ifdef CONFIG_MACB_ZYNQ
+/* INCR4 AHB bursts */
+#define MACB_ZYNQ_GEM_DMACR_BLENGTH 0x00000004
+/* Use full configured addressable space (8 Kb) */
+#define MACB_ZYNQ_GEM_DMACR_RXSIZE 0x00000300
+/* Use full configured addressable space (4 Kb) */
+#define MACB_ZYNQ_GEM_DMACR_TXSIZE 0x00000400
+/* Set RXBUF with use of 128 byte */
+#define MACB_ZYNQ_GEM_DMACR_RXBUF 0x00020000
+#define MACB_ZYNQ_GEM_DMACR_INIT \
+ (MACB_ZYNQ_GEM_DMACR_BLENGTH | \
+ MACB_ZYNQ_GEM_DMACR_RXSIZE | \
+ MACB_ZYNQ_GEM_DMACR_TXSIZE | \
+ MACB_ZYNQ_GEM_DMACR_RXBUF)
+#endif
+
struct macb_dma_desc {
u32 addr;
u32 ctrl;
@@ -461,13 +477,25 @@ static int macb_phy_find(struct macb_device *macb, const char *name)
phy_id = macb_mdio_read(macb, MII_PHYSID1);
if (phy_id != 0xffff) {
printf("%s: PHY present at %d\n", name, i);
- return 1;
+ return 0;
}
}
/* PHY isn't up to snuff */
printf("%s: PHY not found\n", name);
+ return -ENODEV;
+}
+
+/**
+ * macb_linkspd_cb - Linkspeed change callback function
+ * @regs: Base Register of MACB devices
+ * @speed: Linkspeed
+ * Returns 0 when operation success and negative errno number
+ * when operation failed.
+ */
+int __weak macb_linkspd_cb(void *regs, unsigned int speed)
+{
return 0;
}
@@ -483,18 +511,20 @@ static int macb_phy_init(struct macb_device *macb, const char *name)
u32 ncfgr;
u16 phy_id, status, adv, lpa;
int media, speed, duplex;
+ int ret;
int i;
arch_get_mdio_control(name);
/* Auto-detect phy_addr */
- if (!macb_phy_find(macb, name))
- return 0;
+ ret = macb_phy_find(macb, name);
+ if (ret)
+ return ret;
/* Check if the PHY is up to snuff... */
phy_id = macb_mdio_read(macb, MII_PHYSID1);
if (phy_id == 0xffff) {
printf("%s: No PHY present\n", name);
- return 0;
+ return -ENODEV;
}
#ifdef CONFIG_PHYLIB
@@ -530,7 +560,7 @@ static int macb_phy_init(struct macb_device *macb, const char *name)
if (!(status & BMSR_LSTATUS)) {
printf("%s: link down (status: 0x%04x)\n",
name, status);
- return 0;
+ return -ENETDOWN;
}
/* First check for GMAC and that it is GiB capable */
@@ -554,7 +584,11 @@ static int macb_phy_init(struct macb_device *macb, const char *name)
macb_writel(macb, NCFGR, ncfgr);
- return 1;
+ ret = macb_linkspd_cb(macb->regs, _1000BASET);
+ if (ret)
+ return ret;
+
+ return 0;
}
}
@@ -573,13 +607,21 @@ static int macb_phy_init(struct macb_device *macb, const char *name)
ncfgr = macb_readl(macb, NCFGR);
ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | GEM_BIT(GBE));
- if (speed)
+ if (speed) {
ncfgr |= MACB_BIT(SPD);
+ ret = macb_linkspd_cb(macb->regs, _100BASET);
+ } else {
+ ret = macb_linkspd_cb(macb->regs, _10BASET);
+ }
+
+ if (ret)
+ return ret;
+
if (duplex)
ncfgr |= MACB_BIT(FD);
macb_writel(macb, NCFGR, ncfgr);
- return 1;
+ return 0;
}
static int gmac_init_multi_queues(struct macb_device *macb)
@@ -616,6 +658,7 @@ static int _macb_init(struct macb_device *macb, const char *name)
struct macb_device *macb = dev_get_priv(dev);
#endif
unsigned long paddr;
+ int ret;
int i;
/*
@@ -649,6 +692,10 @@ static int _macb_init(struct macb_device *macb, const char *name)
macb->tx_tail = 0;
macb->next_rx_tail = 0;
+#ifdef CONFIG_MACB_ZYNQ
+ macb_writel(macb, DMACFG, MACB_ZYNQ_GEM_DMACR_INIT);
+#endif
+
macb_writel(macb, RBQP, macb->rx_ring_dma);
macb_writel(macb, TBQP, macb->tx_ring_dma);
@@ -709,11 +756,12 @@ static int _macb_init(struct macb_device *macb, const char *name)
}
#ifdef CONFIG_DM_ETH
- if (!macb_phy_init(dev, name))
+ ret = macb_phy_init(dev, name);
#else
- if (!macb_phy_init(macb, name))
+ ret = macb_phy_init(macb, name);
#endif
- return -1;
+ if (ret)
+ return ret;
/* Enable TX and RX */
macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE));
@@ -1013,9 +1061,15 @@ static int macb_enable_clk(struct udevice *dev)
if (ret)
return -EINVAL;
+ /*
+ * Zynq clock driver didn't support for enable or disable
+ * clock. Hence, clk_enable() didn't apply for Zynq
+ */
+#ifndef CONFIG_MACB_ZYNQ
ret = clk_enable(&clk);
if (ret)
return ret;
+#endif
clk_rate = clk_get_rate(&clk);
if (!clk_rate)
@@ -1083,12 +1137,24 @@ static int macb_eth_remove(struct udevice *dev)
return 0;
}
+/**
+ * macb_late_eth_ofdata_to_platdata
+ * @dev: udevice struct
+ * Returns 0 when operation success and negative errno number
+ * when operation failed.
+ */
+int __weak macb_late_eth_ofdata_to_platdata(struct udevice *dev)
+{
+ return 0;
+}
+
static int macb_eth_ofdata_to_platdata(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
pdata->iobase = devfdt_get_addr(dev);
- return 0;
+
+ return macb_late_eth_ofdata_to_platdata(dev);
}
static const struct udevice_id macb_eth_ids[] = {
@@ -1097,6 +1163,7 @@ static const struct udevice_id macb_eth_ids[] = {
{ .compatible = "atmel,sama5d2-gem" },
{ .compatible = "atmel,sama5d3-gem" },
{ .compatible = "atmel,sama5d4-gem" },
+ { .compatible = "cdns,zynq-gem" },
{ }
};
diff --git a/drivers/net/macb.h b/drivers/net/macb.h
index 5bb48f449c..c39554df5f 100644
--- a/drivers/net/macb.h
+++ b/drivers/net/macb.h
@@ -11,6 +11,7 @@
#define MACB_NCFGR 0x0004
#define MACB_NSR 0x0008
#define GEM_UR 0x000c
+#define MACB_DMACFG 0x0010
#define MACB_TSR 0x0014
#define MACB_RBQP 0x0018
#define MACB_TBQP 0x001c
diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c
index f1be9521a9..83e3153768 100644
--- a/drivers/net/mvneta.c
+++ b/drivers/net/mvneta.c
@@ -1654,7 +1654,11 @@ static int mvneta_recv(struct udevice *dev, int flags, uchar **packetp)
*/
*packetp = data;
- mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
+ /*
+ * Only mark one descriptor as free
+ * since only one was processed
+ */
+ mvneta_rxq_desc_num_update(pp, rxq, 1, 1);
}
return rx_bytes;
diff --git a/drivers/net/netconsole.c b/drivers/net/netconsole.c
index e9dbedf326..028fca9663 100644
--- a/drivers/net/netconsole.c
+++ b/drivers/net/netconsole.c
@@ -153,14 +153,17 @@ int nc_input_packet(uchar *pkt, struct in_addr src_ip, unsigned dest_port,
len = sizeof(input_buffer) - input_size;
end = input_offset + input_size;
- if (end > sizeof(input_buffer))
+ if (end >= sizeof(input_buffer))
end -= sizeof(input_buffer);
chunk = len;
- if (end + len > sizeof(input_buffer)) {
+ /* Check if packet will wrap in input_buffer */
+ if (end + len >= sizeof(input_buffer)) {
chunk = sizeof(input_buffer) - end;
+ /* Copy the second part of the pkt to start of input_buffer */
memcpy(input_buffer, pkt + chunk, len - chunk);
}
+ /* Copy first (or only) part of pkt after end of current valid input*/
memcpy(input_buffer + end, pkt, chunk);
input_size += len;
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index e32f1eb1c0..95b7534323 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -12,6 +12,23 @@ menuconfig PHYLIB
if PHYLIB
+config B53_SWITCH
+ bool "Broadcom BCM53xx (RoboSwitch) Ethernet switch PHY support."
+ help
+ Enable support for Broadcom BCM53xx (RoboSwitch) Ethernet switches.
+ This currently supports BCM53125 and similar models.
+
+if B53_SWITCH
+
+config B53_CPU_PORT
+ int "CPU port"
+ default 8
+
+config B53_PHY_PORTS
+ hex "Bitmask of PHY ports"
+
+endif # B53_SWITCH
+
config MV88E61XX_SWITCH
bool "Marvel MV88E61xx Ethernet switch PHY support."
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 1e264b2f2b..f1980371c3 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -6,6 +6,7 @@
#
obj-$(CONFIG_BITBANGMII) += miiphybb.o
+obj-$(CONFIG_B53_SWITCH) += b53.o
obj-$(CONFIG_MV88E61XX_SWITCH) += mv88e61xx.o
obj-$(CONFIG_MV88E6352_SWITCH) += mv88e6352.o
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index b34cdd3d87..d7e76deeb7 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -19,6 +19,7 @@
static int ar8021_config(struct phy_device *phydev)
{
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x00, 0x1200);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
diff --git a/drivers/net/phy/b53.c b/drivers/net/phy/b53.c
new file mode 100644
index 0000000000..f7f2d9f1ee
--- /dev/null
+++ b/drivers/net/phy/b53.c
@@ -0,0 +1,768 @@
+/*
+ * Copyright (C) 2017
+ * Broadcom
+ * Florian Fainelli <f.fainelli@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * PHY driver for Broadcom BCM53xx (roboswitch) Ethernet switches.
+ *
+ * This driver configures the b53 for basic use as a PHY. The switch supports
+ * vendor tags and VLAN configuration that can affect the switching decisions.
+ * This driver uses a simple configuration in which all ports are only allowed
+ * to send frames to the CPU port and receive frames from the CPU port this
+ * providing port isolation (no cross talk).
+ *
+ * The configuration determines which PHY ports to activate using the
+ * CONFIG_B53_PHY_PORTS bitmask. Set bit N will active port N and so on.
+ *
+ * This driver was written primarily for the Lamobo R1 platform using a BCM53152
+ * switch but the BCM53xx being largely register compatible, extending it to
+ * cover other switches would be trivial.
+ */
+
+#include <common.h>
+
+#include <errno.h>
+#include <malloc.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+/* Pseudo-PHY address (non configurable) to access internal registers */
+#define BRCM_PSEUDO_PHY_ADDR 30
+
+/* Maximum number of ports possible */
+#define B53_N_PORTS 9
+
+#define B53_CTRL_PAGE 0x00 /* Control */
+#define B53_MGMT_PAGE 0x02 /* Management Mode */
+/* Port VLAN Page */
+#define B53_PVLAN_PAGE 0x31
+
+/* Control Page registers */
+#define B53_PORT_CTRL(i) (0x00 + (i))
+#define PORT_CTRL_RX_DISABLE BIT(0)
+#define PORT_CTRL_TX_DISABLE BIT(1)
+#define PORT_CTRL_RX_BCST_EN BIT(2) /* Broadcast RX (P8 only) */
+#define PORT_CTRL_RX_MCST_EN BIT(3) /* Multicast RX (P8 only) */
+#define PORT_CTRL_RX_UCST_EN BIT(4) /* Unicast RX (P8 only) */
+
+/* Switch Mode Control Register (8 bit) */
+#define B53_SWITCH_MODE 0x0b
+#define SM_SW_FWD_MODE BIT(0) /* 1 = Managed Mode */
+#define SM_SW_FWD_EN BIT(1) /* Forwarding Enable */
+
+/* IMP Port state override register (8 bit) */
+#define B53_PORT_OVERRIDE_CTRL 0x0e
+#define PORT_OVERRIDE_LINK BIT(0)
+#define PORT_OVERRIDE_FULL_DUPLEX BIT(1) /* 0 = Half Duplex */
+#define PORT_OVERRIDE_SPEED_S 2
+#define PORT_OVERRIDE_SPEED_10M (0 << PORT_OVERRIDE_SPEED_S)
+#define PORT_OVERRIDE_SPEED_100M (1 << PORT_OVERRIDE_SPEED_S)
+#define PORT_OVERRIDE_SPEED_1000M (2 << PORT_OVERRIDE_SPEED_S)
+/* BCM5325 only */
+#define PORT_OVERRIDE_RV_MII_25 BIT(4)
+#define PORT_OVERRIDE_RX_FLOW BIT(4)
+#define PORT_OVERRIDE_TX_FLOW BIT(5)
+/* BCM5301X only, requires setting 1000M */
+#define PORT_OVERRIDE_SPEED_2000M BIT(6)
+#define PORT_OVERRIDE_EN BIT(7) /* Use the register contents */
+
+#define B53_RGMII_CTRL_IMP 0x60
+#define RGMII_CTRL_ENABLE_GMII BIT(7)
+#define RGMII_CTRL_TIMING_SEL BIT(2)
+#define RGMII_CTRL_DLL_RXC BIT(1)
+#define RGMII_CTRL_DLL_TXC BIT(0)
+
+/* Switch control (8 bit) */
+#define B53_SWITCH_CTRL 0x22
+#define B53_MII_DUMB_FWDG_EN BIT(6)
+
+/* Software reset register (8 bit) */
+#define B53_SOFTRESET 0x79
+#define SW_RST BIT(7)
+#define EN_CH_RST BIT(6)
+#define EN_SW_RST BIT(4)
+
+/* Fast Aging Control register (8 bit) */
+#define B53_FAST_AGE_CTRL 0x88
+#define FAST_AGE_STATIC BIT(0)
+#define FAST_AGE_DYNAMIC BIT(1)
+#define FAST_AGE_PORT BIT(2)
+#define FAST_AGE_VLAN BIT(3)
+#define FAST_AGE_STP BIT(4)
+#define FAST_AGE_MC BIT(5)
+#define FAST_AGE_DONE BIT(7)
+
+/* Port VLAN mask (16 bit) IMP port is always 8, also on 5325 & co */
+#define B53_PVLAN_PORT_MASK(i) ((i) * 2)
+
+/* MII registers */
+#define REG_MII_PAGE 0x10 /* MII Page register */
+#define REG_MII_ADDR 0x11 /* MII Address register */
+#define REG_MII_DATA0 0x18 /* MII Data register 0 */
+#define REG_MII_DATA1 0x19 /* MII Data register 1 */
+#define REG_MII_DATA2 0x1a /* MII Data register 2 */
+#define REG_MII_DATA3 0x1b /* MII Data register 3 */
+
+#define REG_MII_PAGE_ENABLE BIT(0)
+#define REG_MII_ADDR_WRITE BIT(0)
+#define REG_MII_ADDR_READ BIT(1)
+
+struct b53_device {
+ struct mii_dev *bus;
+ unsigned int cpu_port;
+};
+
+static int b53_mdio_op(struct mii_dev *bus, u8 page, u8 reg, u16 op)
+{
+ int ret;
+ int i;
+ u16 v;
+
+ /* set page number */
+ v = (page << 8) | REG_MII_PAGE_ENABLE;
+ ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
+ REG_MII_PAGE, v);
+ if (ret)
+ return ret;
+
+ /* set register address */
+ v = (reg << 8) | op;
+ ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
+ REG_MII_ADDR, v);
+ if (ret)
+ return ret;
+
+ /* check if operation completed */
+ for (i = 0; i < 5; ++i) {
+ v = bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
+ REG_MII_ADDR);
+ if (!(v & (REG_MII_ADDR_WRITE | REG_MII_ADDR_READ)))
+ break;
+
+ udelay(100);
+ }
+
+ if (i == 5)
+ return -EIO;
+
+ return 0;
+}
+
+static int b53_mdio_read8(struct mii_dev *bus, u8 page, u8 reg, u8 *val)
+{
+ int ret;
+
+ ret = b53_mdio_op(bus, page, reg, REG_MII_ADDR_READ);
+ if (ret)
+ return ret;
+
+ *val = bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
+ REG_MII_DATA0) & 0xff;
+
+ return 0;
+}
+
+static int b53_mdio_read16(struct mii_dev *bus, u8 page, u8 reg, u16 *val)
+{
+ int ret;
+
+ ret = b53_mdio_op(bus, page, reg, REG_MII_ADDR_READ);
+ if (ret)
+ return ret;
+
+ *val = bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
+ REG_MII_DATA0);
+
+ return 0;
+}
+
+static int b53_mdio_read32(struct mii_dev *bus, u8 page, u8 reg, u32 *val)
+{
+ int ret;
+
+ ret = b53_mdio_op(bus, page, reg, REG_MII_ADDR_READ);
+ if (ret)
+ return ret;
+
+ *val = bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
+ REG_MII_DATA0);
+ *val |= bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
+ REG_MII_DATA1) << 16;
+
+ return 0;
+}
+
+static int b53_mdio_read48(struct mii_dev *bus, u8 page, u8 reg, u64 *val)
+{
+ u64 temp = 0;
+ int i;
+ int ret;
+
+ ret = b53_mdio_op(bus, page, reg, REG_MII_ADDR_READ);
+ if (ret)
+ return ret;
+
+ for (i = 2; i >= 0; i--) {
+ temp <<= 16;
+ temp |= bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
+ REG_MII_DATA0 + i);
+ }
+
+ *val = temp;
+
+ return 0;
+}
+
+static int b53_mdio_read64(struct mii_dev *bus, u8 page, u8 reg, u64 *val)
+{
+ u64 temp = 0;
+ int i;
+ int ret;
+
+ ret = b53_mdio_op(bus, page, reg, REG_MII_ADDR_READ);
+ if (ret)
+ return ret;
+
+ for (i = 3; i >= 0; i--) {
+ temp <<= 16;
+ temp |= bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
+ REG_MII_DATA0 + i);
+ }
+
+ *val = temp;
+
+ return 0;
+}
+
+static int b53_mdio_write8(struct mii_dev *bus, u8 page, u8 reg, u8 value)
+{
+ int ret;
+
+ ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
+ REG_MII_DATA0, value);
+ if (ret)
+ return ret;
+
+ return b53_mdio_op(bus, page, reg, REG_MII_ADDR_WRITE);
+}
+
+static int b53_mdio_write16(struct mii_dev *bus, u8 page, u8 reg,
+ u16 value)
+{
+ int ret;
+
+ ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
+ REG_MII_DATA0, value);
+ if (ret)
+ return ret;
+
+ return b53_mdio_op(bus, page, reg, REG_MII_ADDR_WRITE);
+}
+
+static int b53_mdio_write32(struct mii_dev *bus, u8 page, u8 reg,
+ u32 value)
+{
+ unsigned int i;
+ u32 temp = value;
+
+ for (i = 0; i < 2; i++) {
+ int ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR,
+ MDIO_DEVAD_NONE,
+ REG_MII_DATA0 + i, temp & 0xffff);
+ if (ret)
+ return ret;
+ temp >>= 16;
+ }
+
+ return b53_mdio_op(bus, page, reg, REG_MII_ADDR_WRITE);
+}
+
+static int b53_mdio_write48(struct mii_dev *bus, u8 page, u8 reg,
+ u64 value)
+{
+ unsigned int i;
+ u64 temp = value;
+
+ for (i = 0; i < 3; i++) {
+ int ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR,
+ MDIO_DEVAD_NONE,
+ REG_MII_DATA0 + i, temp & 0xffff);
+ if (ret)
+ return ret;
+ temp >>= 16;
+ }
+
+ return b53_mdio_op(bus, page, reg, REG_MII_ADDR_WRITE);
+}
+
+static int b53_mdio_write64(struct mii_dev *bus, u8 page, u8 reg,
+ u64 value)
+{
+ unsigned int i;
+ u64 temp = value;
+
+ for (i = 0; i < 4; i++) {
+ int ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR,
+ MDIO_DEVAD_NONE,
+ REG_MII_DATA0 + i, temp & 0xffff);
+ if (ret)
+ return ret;
+ temp >>= 16;
+ }
+
+ return b53_mdio_op(bus, page, reg, REG_MII_ADDR_WRITE);
+}
+
+static inline int b53_read8(struct b53_device *dev, u8 page,
+ u8 reg, u8 *value)
+{
+ return b53_mdio_read8(dev->bus, page, reg, value);
+}
+
+static inline int b53_read16(struct b53_device *dev, u8 page,
+ u8 reg, u16 *value)
+{
+ return b53_mdio_read16(dev->bus, page, reg, value);
+}
+
+static inline int b53_read32(struct b53_device *dev, u8 page,
+ u8 reg, u32 *value)
+{
+ return b53_mdio_read32(dev->bus, page, reg, value);
+}
+
+static inline int b53_read48(struct b53_device *dev, u8 page,
+ u8 reg, u64 *value)
+{
+ return b53_mdio_read48(dev->bus, page, reg, value);
+}
+
+static inline int b53_read64(struct b53_device *dev, u8 page,
+ u8 reg, u64 *value)
+{
+ return b53_mdio_read64(dev->bus, page, reg, value);
+}
+
+static inline int b53_write8(struct b53_device *dev, u8 page,
+ u8 reg, u8 value)
+{
+ return b53_mdio_write8(dev->bus, page, reg, value);
+}
+
+static inline int b53_write16(struct b53_device *dev, u8 page,
+ u8 reg, u16 value)
+{
+ return b53_mdio_write16(dev->bus, page, reg, value);
+}
+
+static inline int b53_write32(struct b53_device *dev, u8 page,
+ u8 reg, u32 value)
+{
+ return b53_mdio_write32(dev->bus, page, reg, value);
+}
+
+static inline int b53_write48(struct b53_device *dev, u8 page,
+ u8 reg, u64 value)
+{
+ return b53_mdio_write48(dev->bus, page, reg, value);
+}
+
+static inline int b53_write64(struct b53_device *dev, u8 page,
+ u8 reg, u64 value)
+{
+ return b53_mdio_write64(dev->bus, page, reg, value);
+}
+
+static int b53_flush_arl(struct b53_device *dev, u8 mask)
+{
+ unsigned int i;
+
+ b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
+ FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
+
+ for (i = 0; i < 10; i++) {
+ u8 fast_age_ctrl;
+
+ b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
+ &fast_age_ctrl);
+
+ if (!(fast_age_ctrl & FAST_AGE_DONE))
+ goto out;
+
+ mdelay(1);
+ }
+
+ return -ETIMEDOUT;
+out:
+ /* Only age dynamic entries (default behavior) */
+ b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
+ return 0;
+}
+
+static int b53_switch_reset(struct phy_device *phydev)
+{
+ struct b53_device *dev = phydev->priv;
+ unsigned int timeout = 1000;
+ u8 mgmt;
+ u8 reg;
+
+ b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
+ reg |= SW_RST | EN_SW_RST | EN_CH_RST;
+ b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
+
+ do {
+ b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
+ if (!(reg & SW_RST))
+ break;
+
+ mdelay(1);
+ } while (timeout-- > 0);
+
+ if (timeout == 0)
+ return -ETIMEDOUT;
+
+ b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
+
+ if (!(mgmt & SM_SW_FWD_EN)) {
+ mgmt &= ~SM_SW_FWD_MODE;
+ mgmt |= SM_SW_FWD_EN;
+
+ b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
+ b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
+
+ if (!(mgmt & SM_SW_FWD_EN)) {
+ printf("Failed to enable switch!\n");
+ return -EINVAL;
+ }
+ }
+
+ /* Include IMP port in dumb forwarding mode when no tagging protocol
+ * is configured
+ */
+ b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
+ mgmt |= B53_MII_DUMB_FWDG_EN;
+ b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
+
+ return b53_flush_arl(dev, FAST_AGE_STATIC);
+}
+
+static void b53_enable_cpu_port(struct phy_device *phydev)
+{
+ struct b53_device *dev = phydev->priv;
+ u8 port_ctrl;
+
+ port_ctrl = PORT_CTRL_RX_BCST_EN |
+ PORT_CTRL_RX_MCST_EN |
+ PORT_CTRL_RX_UCST_EN;
+ b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(dev->cpu_port), port_ctrl);
+
+ port_ctrl = PORT_OVERRIDE_EN | PORT_OVERRIDE_LINK |
+ PORT_OVERRIDE_FULL_DUPLEX | PORT_OVERRIDE_SPEED_1000M;
+ b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, port_ctrl);
+
+ b53_read8(dev, B53_CTRL_PAGE, B53_RGMII_CTRL_IMP, &port_ctrl);
+}
+
+static void b53_imp_vlan_setup(struct b53_device *dev, int cpu_port)
+{
+ unsigned int port;
+ u16 pvlan;
+
+ /* Enable the IMP port to be in the same VLAN as the other ports
+ * on a per-port basis such that we only have Port i and IMP in
+ * the same VLAN.
+ */
+ for (port = 0; port < B53_N_PORTS; port++) {
+ if (!((1 << port) & CONFIG_B53_PHY_PORTS))
+ continue;
+
+ b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port),
+ &pvlan);
+ pvlan |= BIT(cpu_port);
+ b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port),
+ pvlan);
+ }
+}
+
+static int b53_port_enable(struct phy_device *phydev, unsigned int port)
+{
+ struct b53_device *dev = phydev->priv;
+ unsigned int cpu_port = dev->cpu_port;
+ u16 pvlan;
+
+ /* Clear the Rx and Tx disable bits and set to no spanning tree */
+ b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
+
+ /* Set this port, and only this one to be in the default VLAN */
+ b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
+ pvlan &= ~0x1ff;
+ pvlan |= BIT(port);
+ b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
+
+ b53_imp_vlan_setup(dev, cpu_port);
+
+ return 0;
+}
+
+static int b53_switch_init(struct phy_device *phydev)
+{
+ static int init;
+ int ret;
+
+ if (init)
+ return 0;
+
+ ret = b53_switch_reset(phydev);
+ if (ret < 0)
+ return ret;
+
+ b53_enable_cpu_port(phydev);
+
+ init = 1;
+
+ return 0;
+}
+
+static int b53_probe(struct phy_device *phydev)
+{
+ struct b53_device *dev;
+ int ret;
+
+ dev = malloc(sizeof(*dev));
+ if (!dev)
+ return -ENOMEM;
+
+ memset(dev, 0, sizeof(*dev));
+
+ phydev->priv = dev;
+ dev->bus = phydev->bus;
+ dev->cpu_port = CONFIG_B53_CPU_PORT;
+
+ ret = b53_switch_reset(phydev);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int b53_phy_config(struct phy_device *phydev)
+{
+ unsigned int port;
+ int res;
+
+ res = b53_switch_init(phydev);
+ if (res < 0)
+ return res;
+
+ for (port = 0; port < B53_N_PORTS; port++) {
+ if (!((1 << port) & CONFIG_B53_PHY_PORTS))
+ continue;
+
+ res = b53_port_enable(phydev, port);
+ if (res < 0) {
+ printf("Error enabling port %i\n", port);
+ continue;
+ }
+
+ res = genphy_config_aneg(phydev);
+ if (res < 0) {
+ printf("Error setting PHY %i autoneg\n", port);
+ continue;
+ }
+
+ res = 0;
+ }
+
+ return res;
+}
+
+static int b53_phy_startup(struct phy_device *phydev)
+{
+ unsigned int port;
+ int res;
+
+ for (port = 0; port < B53_N_PORTS; port++) {
+ if (!((1 << port) & CONFIG_B53_PHY_PORTS))
+ continue;
+
+ phydev->addr = port;
+
+ res = genphy_startup(phydev);
+ if (res < 0)
+ continue;
+ else
+ break;
+ }
+
+ /* Since we are connected directly to the switch, hardcode the link
+ * parameters to match those of the CPU port configured in
+ * b53_enable_cpu_port, we cannot be dependent on the user-facing port
+ * settings (e.g: 100Mbits/sec would not work here)
+ */
+ phydev->speed = 1000;
+ phydev->duplex = 1;
+ phydev->link = 1;
+
+ return 0;
+}
+
+static struct phy_driver b53_driver = {
+ .name = "Broadcom BCM53125",
+ .uid = 0x03625c00,
+ .mask = 0xfffffc00,
+ .features = PHY_GBIT_FEATURES,
+ .probe = b53_probe,
+ .config = b53_phy_config,
+ .startup = b53_phy_startup,
+ .shutdown = &genphy_shutdown,
+};
+
+int phy_b53_init(void)
+{
+ phy_register(&b53_driver);
+
+ return 0;
+}
+
+int do_b53_reg_read(const char *name, int argc, char * const argv[])
+{
+ u8 page, offset, width;
+ struct mii_dev *bus;
+ int ret = -EINVAL;
+ u64 value64 = 0;
+ u32 value32 = 0;
+ u16 value16 = 0;
+ u8 value8 = 0;
+
+ bus = miiphy_get_dev_by_name(name);
+ if (!bus) {
+ printf("unable to find MDIO bus: %s\n", name);
+ return ret;
+ }
+
+ page = simple_strtoul(argv[1], NULL, 16);
+ offset = simple_strtoul(argv[2], NULL, 16);
+ width = simple_strtoul(argv[3], NULL, 10);
+
+ switch (width) {
+ case 8:
+ ret = b53_mdio_read8(bus, page, offset, &value8);
+ printf("page=0x%02x, offset=0x%02x, value=0x%02x\n",
+ page, offset, value8);
+ break;
+ case 16:
+ ret = b53_mdio_read16(bus, page, offset, &value16);
+ printf("page=0x%02x, offset=0x%02x, value=0x%04x\n",
+ page, offset, value16);
+ break;
+ case 32:
+ ret = b53_mdio_read32(bus, page, offset, &value32);
+ printf("page=0x%02x, offset=0x%02x, value=0x%08x\n",
+ page, offset, value32);
+ break;
+ case 48:
+ ret = b53_mdio_read48(bus, page, offset, &value64);
+ printf("page=0x%02x, offset=0x%02x, value=0x%012llx\n",
+ page, offset, value64);
+ break;
+ case 64:
+ ret = b53_mdio_read48(bus, page, offset, &value64);
+ printf("page=0x%02x, offset=0x%02x, value=0x%016llx\n",
+ page, offset, value64);
+ break;
+ default:
+ printf("Unsupported width: %d\n", width);
+ break;
+ }
+
+ return ret;
+}
+
+int do_b53_reg_write(const char *name, int argc, char * const argv[])
+{
+ u8 page, offset, width;
+ struct mii_dev *bus;
+ int ret = -EINVAL;
+ u64 value64 = 0;
+ u32 value = 0;
+
+ bus = miiphy_get_dev_by_name(name);
+ if (!bus) {
+ printf("unable to find MDIO bus: %s\n", name);
+ return ret;
+ }
+
+ page = simple_strtoul(argv[1], NULL, 16);
+ offset = simple_strtoul(argv[2], NULL, 16);
+ width = simple_strtoul(argv[3], NULL, 10);
+ if (width == 48 || width == 64)
+ value64 = simple_strtoull(argv[4], NULL, 16);
+ else
+ value = simple_strtoul(argv[4], NULL, 16);
+
+ switch (width) {
+ case 8:
+ ret = b53_mdio_write8(bus, page, offset, value & 0xff);
+ break;
+ case 16:
+ ret = b53_mdio_write16(bus, page, offset, value);
+ break;
+ case 32:
+ ret = b53_mdio_write32(bus, page, offset, value);
+ break;
+ case 48:
+ ret = b53_mdio_write48(bus, page, offset, value64);
+ break;
+ case 64:
+ ret = b53_mdio_write64(bus, page, offset, value64);
+ break;
+ default:
+ printf("Unsupported width: %d\n", width);
+ break;
+ }
+
+ return ret;
+}
+
+int do_b53_reg(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ const char *cmd, *mdioname;
+ int ret = 0;
+
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
+ cmd = argv[1];
+ --argc;
+ ++argv;
+
+ if (!strcmp(cmd, "write")) {
+ if (argc < 4)
+ return cmd_usage(cmdtp);
+ mdioname = argv[1];
+ --argc;
+ ++argv;
+ ret = do_b53_reg_write(mdioname, argc, argv);
+ } else if (!strcmp(cmd, "read")) {
+ if (argc < 5)
+ return cmd_usage(cmdtp);
+ mdioname = argv[1];
+ --argc;
+ ++argv;
+ ret = do_b53_reg_read(mdioname, argc, argv);
+ } else {
+ return cmd_usage(cmdtp);
+ }
+
+ return ret;
+}
+
+U_BOOT_CMD(b53_reg, 7, 1, do_b53_reg,
+ "Broadcom B53 switch register access",
+ "write mdioname page (hex) offset (hex) width (dec) value (hex)\n"
+ "read mdioname page (hex) offset (hex) width (dec)\n"
+ );
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index b7f300e40f..0b9a9fce8a 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -104,6 +104,31 @@
#define MIIM_88E151x_MODE_SGMII 1
#define MIIM_88E151x_RESET_OFFS 15
+static int m88e1xxx_phy_extread(struct phy_device *phydev, int addr,
+ int devaddr, int regnum)
+{
+ int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE);
+ int val;
+
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, regnum);
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage);
+
+ return val;
+}
+
+static int m88e1xxx_phy_extwrite(struct phy_device *phydev, int addr,
+ int devaddr, int regnum, u16 val)
+{
+ int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE);
+
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr);
+ phy_write(phydev, MDIO_DEVAD_NONE, regnum, val);
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage);
+
+ return 0;
+}
+
/* Marvell 88E1011S */
static int m88e1011s_config(struct phy_device *phydev)
{
@@ -669,6 +694,8 @@ static struct phy_driver M88E1510_driver = {
.config = &m88e1510_config,
.startup = &m88e1011s_startup,
.shutdown = &genphy_shutdown,
+ .readext = &m88e1xxx_phy_extread,
+ .writeext = &m88e1xxx_phy_extwrite,
};
/*
@@ -684,6 +711,8 @@ static struct phy_driver M88E1518_driver = {
.config = &m88e1518_config,
.startup = &m88e1011s_startup,
.shutdown = &genphy_shutdown,
+ .readext = &m88e1xxx_phy_extread,
+ .writeext = &m88e1xxx_phy_extwrite,
};
static struct phy_driver M88E1310_driver = {
diff --git a/drivers/net/phy/miiphybb.c b/drivers/net/phy/miiphybb.c
index af676b9bae..d61722490e 100644
--- a/drivers/net/phy/miiphybb.c
+++ b/drivers/net/phy/miiphybb.c
@@ -232,7 +232,7 @@ static void miiphy_pre(struct bb_miiphy_bus *bus, char read,
*/
int bb_miiphy_read(struct mii_dev *miidev, int addr, int devad, int reg)
{
- short rdreg; /* register working value */
+ unsigned short rdreg; /* register working value */
int v;
int j; /* counter */
struct bb_miiphy_bus *bus;
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index fd3dd556c8..e31f3aa3a9 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -461,6 +461,9 @@ static LIST_HEAD(phy_drivers);
int phy_init(void)
{
+#ifdef CONFIG_B53_SWITCH
+ phy_b53_init();
+#endif
#ifdef CONFIG_MV88E61XX_SWITCH
phy_mv88e61xx_init();
#endif
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 970d730e56..6edb51e12f 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -29,7 +29,8 @@
#if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF)
#define flush_cache_wback(addr, len) \
- flush_dcache_range((u32)addr, (u32)(addr + len - 1))
+ flush_dcache_range((u32)addr, \
+ (u32)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
#else
#define flush_cache_wback(...)
#endif
@@ -67,7 +68,7 @@ int sh_eth_send(struct eth_device *dev, void *packet, int len)
/* packet must be a 4 byte boundary */
if ((int)packet & 3) {
- printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n"
+ printf(SHETHER_NAME ": %s: packet not 4 byte aligned\n"
, __func__);
ret = -EFAULT;
goto err;
@@ -86,8 +87,8 @@ int sh_eth_send(struct eth_device *dev, void *packet, int len)
flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s));
/* Restart the transmitter if disabled */
- if (!(sh_eth_read(eth, EDTRR) & EDTRR_TRNS))
- sh_eth_write(eth, EDTRR_TRNS, EDTRR);
+ if (!(sh_eth_read(port_info, EDTRR) & EDTRR_TRNS))
+ sh_eth_write(port_info, EDTRR_TRNS, EDTRR);
/* Wait until packet is transmitted */
timeout = TIMEOUT_CNT;
@@ -147,24 +148,25 @@ int sh_eth_recv(struct eth_device *dev)
}
/* Restart the receiver if disabled */
- if (!(sh_eth_read(eth, EDRRR) & EDRRR_R))
- sh_eth_write(eth, EDRRR_R, EDRRR);
+ if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
+ sh_eth_write(port_info, EDRRR_R, EDRRR);
return len;
}
static int sh_eth_reset(struct sh_eth_dev *eth)
{
+ struct sh_eth_info *port_info = &eth->port_info[eth->port];
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
int ret = 0, i;
/* Start e-dmac transmitter and receiver */
- sh_eth_write(eth, EDSR_ENALL, EDSR);
+ sh_eth_write(port_info, EDSR_ENALL, EDSR);
/* Perform a software reset and wait for it to complete */
- sh_eth_write(eth, EDMR_SRST, EDMR);
+ sh_eth_write(port_info, EDMR_SRST, EDMR);
for (i = 0; i < TIMEOUT_CNT; i++) {
- if (!(sh_eth_read(eth, EDMR) & EDMR_SRST))
+ if (!(sh_eth_read(port_info, EDMR) & EDMR_SRST))
break;
udelay(1000);
}
@@ -176,9 +178,10 @@ static int sh_eth_reset(struct sh_eth_dev *eth)
return ret;
#else
- sh_eth_write(eth, sh_eth_read(eth, EDMR) | EDMR_SRST, EDMR);
+ sh_eth_write(port_info, sh_eth_read(port_info, EDMR) | EDMR_SRST, EDMR);
udelay(3000);
- sh_eth_write(eth, sh_eth_read(eth, EDMR) & ~EDMR_SRST, EDMR);
+ sh_eth_write(port_info,
+ sh_eth_read(port_info, EDMR) & ~EDMR_SRST, EDMR);
return 0;
#endif
@@ -203,7 +206,7 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
goto err;
}
- flush_cache_wback((u32)port_info->tx_desc_alloc, alloc_desc_size);
+ flush_cache_wback(port_info->tx_desc_alloc, alloc_desc_size);
/* Make sure we use a P2 address (non-cacheable) */
port_info->tx_desc_base =
@@ -222,13 +225,15 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
cur_tx_desc--;
cur_tx_desc->td0 |= TD_TDLE;
- /* Point the controller to the tx descriptor list. Must use physical
- addresses */
- sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
+ /*
+ * Point the controller to the tx descriptor list. Must use physical
+ * addresses
+ */
+ sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
- sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
- sh_eth_write(eth, ADDR_TO_PHY(cur_tx_desc), TDFXR);
- sh_eth_write(eth, 0x01, TDFFR);/* Last discriptor bit */
+ sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
+ sh_eth_write(port_info, ADDR_TO_PHY(cur_tx_desc), TDFXR);
+ sh_eth_write(port_info, 0x01, TDFFR);/* Last discriptor bit */
#endif
err:
@@ -237,7 +242,7 @@ err:
static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
{
- int port = eth->port, i , ret = 0;
+ int port = eth->port, i, ret = 0;
u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s);
struct sh_eth_info *port_info = &eth->port_info[port];
struct rx_desc_s *cur_rx_desc;
@@ -283,7 +288,7 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
cur_rx_desc->rd0 = RD_RACT;
cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
- cur_rx_desc->rd2 = (u32) ADDR_TO_PHY(rx_buf);
+ cur_rx_desc->rd2 = (u32)ADDR_TO_PHY(rx_buf);
}
/* Mark the end of the descriptors */
@@ -291,11 +296,11 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
cur_rx_desc->rd0 |= RD_RDLE;
/* Point the controller to the rx descriptor list */
- sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
+ sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
- sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
- sh_eth_write(eth, ADDR_TO_PHY(cur_rx_desc), RDFXR);
- sh_eth_write(eth, RDFFR_RDLF, RDFFR);
+ sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
+ sh_eth_write(port_info, ADDR_TO_PHY(cur_rx_desc), RDFXR);
+ sh_eth_write(port_info, RDFFR_RDLF, RDFFR);
#endif
return ret;
@@ -371,7 +376,7 @@ static int sh_eth_phy_config(struct sh_eth_dev *eth)
return ret;
}
-static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
+static int sh_eth_config(struct sh_eth_dev *eth)
{
int port = eth->port, ret = 0;
u32 val;
@@ -380,45 +385,45 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
struct phy_device *phy;
/* Configure e-dmac registers */
- sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) |
+ sh_eth_write(port_info, (sh_eth_read(port_info, EDMR) & ~EMDR_DESC_R) |
(EMDR_DESC | EDMR_EL), EDMR);
- sh_eth_write(eth, 0, EESIPR);
- sh_eth_write(eth, 0, TRSCER);
- sh_eth_write(eth, 0, TFTR);
- sh_eth_write(eth, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
- sh_eth_write(eth, RMCR_RST, RMCR);
+ sh_eth_write(port_info, 0, EESIPR);
+ sh_eth_write(port_info, 0, TRSCER);
+ sh_eth_write(port_info, 0, TFTR);
+ sh_eth_write(port_info, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
+ sh_eth_write(port_info, RMCR_RST, RMCR);
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
- sh_eth_write(eth, 0, RPADIR);
+ sh_eth_write(port_info, 0, RPADIR);
#endif
- sh_eth_write(eth, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
+ sh_eth_write(port_info, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
/* Configure e-mac registers */
- sh_eth_write(eth, 0, ECSIPR);
+ sh_eth_write(port_info, 0, ECSIPR);
/* Set Mac address */
val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 |
dev->enetaddr[2] << 8 | dev->enetaddr[3];
- sh_eth_write(eth, val, MAHR);
+ sh_eth_write(port_info, val, MAHR);
val = dev->enetaddr[4] << 8 | dev->enetaddr[5];
- sh_eth_write(eth, val, MALR);
+ sh_eth_write(port_info, val, MALR);
- sh_eth_write(eth, RFLR_RFL_MIN, RFLR);
+ sh_eth_write(port_info, RFLR_RFL_MIN, RFLR);
#if defined(SH_ETH_TYPE_GETHER)
- sh_eth_write(eth, 0, PIPR);
+ sh_eth_write(port_info, 0, PIPR);
#endif
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
- sh_eth_write(eth, APR_AP, APR);
- sh_eth_write(eth, MPR_MP, MPR);
- sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER);
+ sh_eth_write(port_info, APR_AP, APR);
+ sh_eth_write(port_info, MPR_MP, MPR);
+ sh_eth_write(port_info, TPAUSER_TPAUSE, TPAUSER);
#endif
#if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
- sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
+ sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
- sh_eth_write(eth, sh_eth_read(eth, RMIIMR) | 0x1, RMIIMR);
+ sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR);
#endif
/* Configure phy */
ret = sh_eth_phy_config(eth);
@@ -439,9 +444,9 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
if (phy->speed == 100) {
printf(SHETHER_NAME ": 100Base/");
#if defined(SH_ETH_TYPE_GETHER)
- sh_eth_write(eth, GECMR_100B, GECMR);
+ sh_eth_write(port_info, GECMR_100B, GECMR);
#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
- sh_eth_write(eth, 1, RTRATE);
+ sh_eth_write(port_info, 1, RTRATE);
#elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) || \
defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \
defined(CONFIG_R8A7794)
@@ -450,26 +455,29 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
} else if (phy->speed == 10) {
printf(SHETHER_NAME ": 10Base/");
#if defined(SH_ETH_TYPE_GETHER)
- sh_eth_write(eth, GECMR_10B, GECMR);
+ sh_eth_write(port_info, GECMR_10B, GECMR);
#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
- sh_eth_write(eth, 0, RTRATE);
+ sh_eth_write(port_info, 0, RTRATE);
#endif
}
#if defined(SH_ETH_TYPE_GETHER)
else if (phy->speed == 1000) {
printf(SHETHER_NAME ": 1000Base/");
- sh_eth_write(eth, GECMR_1000B, GECMR);
+ sh_eth_write(port_info, GECMR_1000B, GECMR);
}
#endif
/* Check if full duplex mode is supported by the phy */
if (phy->duplex) {
printf("Full\n");
- sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM),
+ sh_eth_write(port_info,
+ val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE | ECMR_DM),
ECMR);
} else {
printf("Half\n");
- sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR);
+ sh_eth_write(port_info,
+ val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE),
+ ECMR);
}
return ret;
@@ -480,16 +488,20 @@ err_phy_cfg:
static void sh_eth_start(struct sh_eth_dev *eth)
{
+ struct sh_eth_info *port_info = &eth->port_info[eth->port];
+
/*
* Enable the e-dmac receiver only. The transmitter will be enabled when
* we have something to transmit
*/
- sh_eth_write(eth, EDRRR_R, EDRRR);
+ sh_eth_write(port_info, EDRRR_R, EDRRR);
}
static void sh_eth_stop(struct sh_eth_dev *eth)
{
- sh_eth_write(eth, ~EDRRR_R, EDRRR);
+ struct sh_eth_info *port_info = &eth->port_info[eth->port];
+
+ sh_eth_write(port_info, ~EDRRR_R, EDRRR);
}
int sh_eth_init(struct eth_device *dev, bd_t *bd)
@@ -505,7 +517,7 @@ int sh_eth_init(struct eth_device *dev, bd_t *bd)
if (ret)
goto err;
- ret = sh_eth_config(eth, bd);
+ ret = sh_eth_config(eth);
if (ret)
goto err_config;
@@ -524,6 +536,7 @@ err:
void sh_eth_halt(struct eth_device *dev)
{
struct sh_eth_dev *eth = dev->priv;
+
sh_eth_stop(eth);
}
@@ -532,6 +545,7 @@ int sh_eth_initialize(bd_t *bd)
int ret = 0;
struct sh_eth_dev *eth = NULL;
struct eth_device *dev = NULL;
+ struct mii_dev *mdiodev;
eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
if (!eth) {
@@ -551,6 +565,8 @@ int sh_eth_initialize(bd_t *bd)
eth->port = CONFIG_SH_ETHER_USE_PORT;
eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
+ eth->port_info[eth->port].iobase =
+ (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
dev->priv = (void *)eth;
dev->iobase = 0;
@@ -566,17 +582,16 @@ int sh_eth_initialize(bd_t *bd)
eth_register(dev);
bb_miiphy_buses[0].priv = eth;
- int retval;
- struct mii_dev *mdiodev = mdio_alloc();
+ mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
mdiodev->read = bb_miiphy_read;
mdiodev->write = bb_miiphy_write;
- retval = mdio_register(mdiodev);
- if (retval < 0)
- return retval;
+ ret = mdio_register(mdiodev);
+ if (ret < 0)
+ return ret;
if (!eth_env_get_enetaddr("ethaddr", dev->enetaddr))
puts("Please set MAC address\n");
@@ -603,8 +618,9 @@ static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
{
struct sh_eth_dev *eth = bus->priv;
+ struct sh_eth_info *port_info = &eth->port_info[eth->port];
- sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MMD, PIR);
+ sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR);
return 0;
}
@@ -612,8 +628,9 @@ static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
{
struct sh_eth_dev *eth = bus->priv;
+ struct sh_eth_info *port_info = &eth->port_info[eth->port];
- sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MMD, PIR);
+ sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR);
return 0;
}
@@ -621,11 +638,14 @@ static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
{
struct sh_eth_dev *eth = bus->priv;
+ struct sh_eth_info *port_info = &eth->port_info[eth->port];
if (v)
- sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDO, PIR);
+ sh_eth_write(port_info,
+ sh_eth_read(port_info, PIR) | PIR_MDO, PIR);
else
- sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDO, PIR);
+ sh_eth_write(port_info,
+ sh_eth_read(port_info, PIR) & ~PIR_MDO, PIR);
return 0;
}
@@ -633,8 +653,9 @@ static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
{
struct sh_eth_dev *eth = bus->priv;
+ struct sh_eth_info *port_info = &eth->port_info[eth->port];
- *v = (sh_eth_read(eth, PIR) & PIR_MDI) >> 3;
+ *v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3;
return 0;
}
@@ -642,11 +663,14 @@ static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
{
struct sh_eth_dev *eth = bus->priv;
+ struct sh_eth_info *port_info = &eth->port_info[eth->port];
if (v)
- sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDC, PIR);
+ sh_eth_write(port_info,
+ sh_eth_read(port_info, PIR) | PIR_MDC, PIR);
else
- sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDC, PIR);
+ sh_eth_write(port_info,
+ sh_eth_read(port_info, PIR) & ~PIR_MDC, PIR);
return 0;
}
@@ -670,4 +694,5 @@ struct bb_miiphy_bus bb_miiphy_buses[] = {
.delay = sh_eth_bb_delay,
}
};
+
int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index 3645f0eca7..a0dcfcae09 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -25,8 +25,10 @@
#define ADDR_TO_PHY(addr) ((int)(addr) & ~0xe0000000)
#endif
#elif defined(CONFIG_ARM)
-#define inl readl
+#ifndef inl
+#define inl readl
#define outl writel
+#endif
#define ADDR_TO_PHY(addr) ((int)(addr))
#define ADDR_TO_P2(addr) (addr)
#endif /* defined(CONFIG_SH) */
@@ -90,6 +92,7 @@ struct sh_eth_info {
u8 phy_addr;
struct eth_device *dev;
struct phy_device *phydev;
+ void __iomem *iobase;
};
struct sh_eth_dev {
@@ -226,61 +229,6 @@ static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
[RMII_MII] = 0x0790,
};
-#if defined(SH_ETH_TYPE_RZ)
-static const u16 sh_eth_offset_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
- [EDSR] = 0x0000,
- [EDMR] = 0x0400,
- [EDTRR] = 0x0408,
- [EDRRR] = 0x0410,
- [EESR] = 0x0428,
- [EESIPR] = 0x0430,
- [TDLAR] = 0x0010,
- [TDFAR] = 0x0014,
- [TDFXR] = 0x0018,
- [TDFFR] = 0x001c,
- [RDLAR] = 0x0030,
- [RDFAR] = 0x0034,
- [RDFXR] = 0x0038,
- [RDFFR] = 0x003c,
- [TRSCER] = 0x0438,
- [RMFCR] = 0x0440,
- [TFTR] = 0x0448,
- [FDR] = 0x0450,
- [RMCR] = 0x0458,
- [RPADIR] = 0x0460,
- [FCFTR] = 0x0468,
- [CSMR] = 0x04E4,
-
- [ECMR] = 0x0500,
- [ECSR] = 0x0510,
- [ECSIPR] = 0x0518,
- [PSR] = 0x0528,
- [PIPR] = 0x052c,
- [RFLR] = 0x0508,
- [APR] = 0x0554,
- [MPR] = 0x0558,
- [PFTCR] = 0x055c,
- [PFRCR] = 0x0560,
- [TPAUSER] = 0x0564,
- [GECMR] = 0x05b0,
- [BCULR] = 0x05b4,
- [MAHR] = 0x05c0,
- [MALR] = 0x05c8,
- [TROCR] = 0x0700,
- [CDCR] = 0x0708,
- [LCCR] = 0x0710,
- [CEFCR] = 0x0740,
- [FRECR] = 0x0748,
- [TSFRCR] = 0x0750,
- [TLFRCR] = 0x0758,
- [RFCR] = 0x0760,
- [CERCR] = 0x0768,
- [CEECR] = 0x0770,
- [MAFCR] = 0x0778,
- [RMII_MII] = 0x0790,
-};
-#endif
-
static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
[ECMR] = 0x0100,
[RFLR] = 0x0108,
@@ -654,29 +602,27 @@ enum FIFO_SIZE_BIT {
FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
};
-static inline unsigned long sh_eth_reg_addr(struct sh_eth_dev *eth,
+static inline unsigned long sh_eth_reg_addr(struct sh_eth_info *port,
int enum_index)
{
-#if defined(SH_ETH_TYPE_GETHER)
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
const u16 *reg_offset = sh_eth_offset_gigabit;
#elif defined(SH_ETH_TYPE_ETHER)
const u16 *reg_offset = sh_eth_offset_fast_sh4;
-#elif defined(SH_ETH_TYPE_RZ)
- const u16 *reg_offset = sh_eth_offset_rz;
#else
#error
#endif
- return BASE_IO_ADDR + reg_offset[enum_index] + 0x800 * eth->port;
+ return (unsigned long)port->iobase + reg_offset[enum_index];
}
-static inline void sh_eth_write(struct sh_eth_dev *eth, unsigned long data,
+static inline void sh_eth_write(struct sh_eth_info *port, unsigned long data,
int enum_index)
{
- outl(data, sh_eth_reg_addr(eth, enum_index));
+ outl(data, sh_eth_reg_addr(port, enum_index));
}
-static inline unsigned long sh_eth_read(struct sh_eth_dev *eth,
+static inline unsigned long sh_eth_read(struct sh_eth_info *port,
int enum_index)
{
- return inl(sh_eth_reg_addr(eth, enum_index));
+ return inl(sh_eth_reg_addr(port, enum_index));
}
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 5eb12efbf5..5410897e40 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -29,7 +29,6 @@ obj-$(CONFIG_SH4_PCI) += pci_sh4.o
obj-$(CONFIG_SH7751_PCI) +=pci_sh7751.o
obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o
obj-$(CONFIG_PCI_TEGRA) += pci_tegra.o
-obj-$(CONFIG_TSI108_PCI) += tsi108_pci.o
obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o
obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o
obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o
diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c
index 2900c8d9d1..ef66a1d3f4 100644
--- a/drivers/pci/pcie_imx.c
+++ b/drivers/pci/pcie_imx.c
@@ -517,10 +517,12 @@ static int imx6_pcie_init_phy(void)
__weak int imx6_pcie_toggle_power(void)
{
#ifdef CONFIG_PCIE_IMX_POWER_GPIO
+ gpio_request(CONFIG_PCIE_IMX_POWER_GPIO, "pcie_power");
gpio_direction_output(CONFIG_PCIE_IMX_POWER_GPIO, 0);
mdelay(20);
gpio_set_value(CONFIG_PCIE_IMX_POWER_GPIO, 1);
mdelay(20);
+ gpio_free(CONFIG_PCIE_IMX_POWER_GPIO);
#endif
return 0;
}
@@ -556,10 +558,12 @@ __weak int imx6_pcie_toggle_reset(void)
* state due to being previously used in U-Boot.
*/
#ifdef CONFIG_PCIE_IMX_PERST_GPIO
+ gpio_request(CONFIG_PCIE_IMX_PERST_GPIO, "pcie_reset");
gpio_direction_output(CONFIG_PCIE_IMX_PERST_GPIO, 0);
mdelay(20);
gpio_set_value(CONFIG_PCIE_IMX_PERST_GPIO, 1);
mdelay(20);
+ gpio_free(CONFIG_PCIE_IMX_PERST_GPIO);
#else
puts("WARNING: Make sure the PCIe #PERST line is connected!\n");
#endif
@@ -612,6 +616,17 @@ static int imx_pcie_link_up(void)
imx_pcie_regions_setup();
/*
+ * By default, the subordinate is set equally to the secondary
+ * bus (0x01) when the RC boots.
+ * This means that theoretically, only bus 1 is reachable from the RC.
+ * Force the PCIe RC subordinate to 0xff, otherwise no downstream
+ * devices will be detected if the enumeration is applied strictly.
+ */
+ tmp = readl(MX6_DBI_ADDR + 0x18);
+ tmp |= (0xff << 16);
+ writel(tmp, MX6_DBI_ADDR + 0x18);
+
+ /*
* FIXME: Force the PCIe RC to Gen1 operation
* The RC must be forced into Gen1 mode before bringing the link
* up, otherwise no downstream devices are detected. After the
diff --git a/drivers/pci/tsi108_pci.c b/drivers/pci/tsi108_pci.c
deleted file mode 100644
index d48e1e6fe6..0000000000
--- a/drivers/pci/tsi108_pci.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * (C) Copyright 2004 Tundra Semiconductor Corp.
- * Alex Bounine <alexandreb@tundra.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * PCI initialisation for the Tsi108 EMU board.
- */
-
-#include <config.h>
-
-#include <common.h>
-#include <pci.h>
-#include <asm/io.h>
-#include <tsi108.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#include <fdt_support.h>
-#endif
-
-struct pci_controller local_hose;
-
-void tsi108_clear_pci_error (void)
-{
- u32 err_stat, err_addr, pci_stat;
-
- /*
- * Quietly clear errors signalled as result of PCI/X configuration read
- * requests.
- */
- /* Read PB Error Log Registers */
- err_stat = *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
- TSI108_PB_REG_OFFSET + PB_ERRCS);
- err_addr = *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
- TSI108_PB_REG_OFFSET + PB_AERR);
- if (err_stat & PB_ERRCS_ES) {
- /* Clear PCI/X bus errors if applicable */
- if ((err_addr & 0xFF000000) == CONFIG_SYS_PCI_CFG_BASE) {
- /* Clear error flag */
- *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE +
- TSI108_PB_REG_OFFSET + PB_ERRCS) =
- PB_ERRCS_ES;
-
- /* Clear read error reported in PB_ISR */
- *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE +
- TSI108_PB_REG_OFFSET + PB_ISR) =
- PB_ISR_PBS_RD_ERR;
-
- /* Clear errors reported by PCI CSR (Normally Master Abort) */
- pci_stat = *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
- TSI108_PCI_REG_OFFSET +
- PCI_CSR);
- *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
- TSI108_PCI_REG_OFFSET + PCI_CSR) =
- pci_stat;
-
- *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
- TSI108_PCI_REG_OFFSET +
- PCI_IRP_STAT) = PCI_IRP_STAT_P_CSR;
- }
- }
-
- return;
-}
-
-unsigned int __get_pci_config_dword (u32 addr)
-{
- unsigned int retval;
-
- __asm__ __volatile__ (" lwbrx %0,0,%1\n"
- "1: eieio\n"
- "2:\n"
- ".section .fixup,\"ax\"\n"
- "3: li %0,-1\n"
- " b 2b\n"
- ".section __ex_table,\"a\"\n"
- " .align 2\n"
- " .long 1b,3b\n"
- ".section .text.__get_pci_config_dword"
- : "=r"(retval) : "r"(addr));
-
- return (retval);
-}
-
-static int tsi108_read_config_dword (struct pci_controller *hose,
- pci_dev_t dev, int offset, u32 * value)
-{
- dev &= (CONFIG_SYS_PCI_CFG_SIZE - 1);
- dev |= (CONFIG_SYS_PCI_CFG_BASE | (offset & 0xfc));
- *value = __get_pci_config_dword(dev);
- if (0xFFFFFFFF == *value)
- tsi108_clear_pci_error ();
- return 0;
-}
-
-static int tsi108_write_config_dword (struct pci_controller *hose,
- pci_dev_t dev, int offset, u32 value)
-{
- dev &= (CONFIG_SYS_PCI_CFG_SIZE - 1);
- dev |= (CONFIG_SYS_PCI_CFG_BASE | (offset & 0xfc));
-
- out_le32 ((volatile unsigned *)dev, value);
-
- return 0;
-}
-
-void pci_init_board (void)
-{
- struct pci_controller *hose = (struct pci_controller *)&local_hose;
-
- hose->first_busno = 0;
- hose->last_busno = 0xff;
-
- pci_set_region (hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
- /* PCI memory space */
- pci_set_region (hose->regions + 1,
- CONFIG_SYS_PCI_MEM_BUS,
- CONFIG_SYS_PCI_MEM_PHYS, CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM);
-
- /* PCI I/O space */
- pci_set_region (hose->regions + 2,
- CONFIG_SYS_PCI_IO_BUS,
- CONFIG_SYS_PCI_IO_PHYS, CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
-
- hose->region_count = 3;
-
- pci_set_ops (hose,
- pci_hose_read_config_byte_via_dword,
- pci_hose_read_config_word_via_dword,
- tsi108_read_config_dword,
- pci_hose_write_config_byte_via_dword,
- pci_hose_write_config_word_via_dword,
- tsi108_write_config_dword);
-
- pci_register_hose (hose);
-
- hose->last_busno = pci_hose_scan (hose);
-
- debug ("Done PCI initialization\n");
- return;
-}
-
-#if defined(CONFIG_OF_LIBFDT)
-void ft_pci_setup(void *blob, bd_t *bd)
-{
- int nodeoffset;
- int tmp[2];
- const char *path;
-
- nodeoffset = fdt_path_offset(blob, "/aliases");
- if (nodeoffset >= 0) {
- path = fdt_getprop(blob, nodeoffset, "pci", NULL);
- if (path) {
- tmp[0] = cpu_to_be32(local_hose.first_busno);
- tmp[1] = cpu_to_be32(local_hose.last_busno);
- do_fixup_by_path(blob, path, "bus-range",
- &tmp, sizeof(tmp), 1);
- }
- }
-}
-#endif /* CONFIG_OF_LIBFDT */
diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig
index a9388ff7e2..07d4f3e216 100644
--- a/drivers/pinctrl/mvebu/Kconfig
+++ b/drivers/pinctrl/mvebu/Kconfig
@@ -1,14 +1,14 @@
if ARCH_MVEBU
config PINCTRL_ARMADA_37XX
- depends on ARMADA_3700
+ depends on ARMADA_3700 && PINCTRL_FULL
bool "Armada 37xx pin control driver"
help
Support pin multiplexing and pin configuration control on
Marvell's Armada-37xx SoC.
config PINCTRL_ARMADA_8K
- depends on ARMADA_8K
+ depends on ARMADA_8K && PINCTRL_FULL
bool "Armada 7k/8k pin control driver"
help
Support pin multiplexing and pin configuration control on
diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c
index 51fdfb3851..2066e11cf1 100644
--- a/drivers/pinctrl/pinctrl_stm32.c
+++ b/drivers/pinctrl/pinctrl_stm32.c
@@ -182,6 +182,8 @@ static struct pinctrl_ops stm32_pinctrl_ops = {
};
static const struct udevice_id stm32_pinctrl_ids[] = {
+ { .compatible = "st,stm32f429-pinctrl" },
+ { .compatible = "st,stm32f469-pinctrl" },
{ .compatible = "st,stm32f746-pinctrl" },
{ .compatible = "st,stm32h743-pinctrl" },
{ }
diff --git a/drivers/power/pmic/s2mps11.c b/drivers/power/pmic/s2mps11.c
index 522105e5ff..3f9525b67d 100644
--- a/drivers/power/pmic/s2mps11.c
+++ b/drivers/power/pmic/s2mps11.c
@@ -15,6 +15,12 @@
DECLARE_GLOBAL_DATA_PTR;
+static const struct pmic_child_info pmic_children_info[] = {
+ { .prefix = S2MPS11_OF_LDO_PREFIX, .driver = S2MPS11_LDO_DRIVER },
+ { .prefix = S2MPS11_OF_BUCK_PREFIX, .driver = S2MPS11_BUCK_DRIVER },
+ { },
+};
+
static int s2mps11_reg_count(struct udevice *dev)
{
return S2MPS11_REG_COUNT;
@@ -43,6 +49,27 @@ static int s2mps11_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
return ret;
}
+static int s2mps11_probe(struct udevice *dev)
+{
+ ofnode regulators_node;
+ int children;
+
+ regulators_node = dev_read_subnode(dev, "voltage-regulators");
+ if (!ofnode_valid(regulators_node)) {
+ debug("%s: %s regulators subnode not found!", __func__,
+ dev->name);
+ return -ENXIO;
+ }
+
+ debug("%s: '%s' - found regulators subnode\n", __func__, dev->name);
+
+ children = pmic_bind_children(dev, regulators_node, pmic_children_info);
+ if (!children)
+ debug("%s: %s - no child found\n", __func__, dev->name);
+
+ return 0;
+}
+
static struct dm_pmic_ops s2mps11_ops = {
.reg_count = s2mps11_reg_count,
.read = s2mps11_read,
@@ -59,4 +86,5 @@ U_BOOT_DRIVER(pmic_s2mps11) = {
.id = UCLASS_PMIC,
.of_match = s2mps11_ids,
.ops = &s2mps11_ops,
+ .probe = s2mps11_probe,
};
diff --git a/drivers/power/power_core.c b/drivers/power/power_core.c
index b72286d429..46840a33e0 100644
--- a/drivers/power/power_core.c
+++ b/drivers/power/power_core.c
@@ -47,36 +47,6 @@ int pmic_set_output(struct pmic *p, u32 reg, int out, int on)
return 0;
}
-static void pmic_show_info(struct pmic *p)
-{
- printf("PMIC: %s\n", p->name);
-}
-
-static int pmic_dump(struct pmic *p)
-{
- int i, ret;
- u32 val;
-
- if (!p) {
- puts("Wrong PMIC name!\n");
- return -ENODEV;
- }
-
- pmic_show_info(p);
- for (i = 0; i < p->number_of_regs; i++) {
- ret = pmic_reg_read(p, i, &val);
- if (ret)
- puts("PMIC: Registers dump failed\n");
-
- if (!(i % 8))
- printf("\n0x%02x: ", i);
-
- printf("%08x ", val);
- }
- puts("\n");
- return 0;
-}
-
struct pmic *pmic_alloc(void)
{
struct pmic *p;
@@ -108,7 +78,33 @@ struct pmic *pmic_get(const char *s)
return NULL;
}
-const char *power_get_interface(int interface)
+#ifndef CONFIG_SPL_BUILD
+static int pmic_dump(struct pmic *p)
+{
+ int i, ret;
+ u32 val;
+
+ if (!p) {
+ puts("Wrong PMIC name!\n");
+ return -ENODEV;
+ }
+
+ printf("PMIC: %s\n", p->name);
+ for (i = 0; i < p->number_of_regs; i++) {
+ ret = pmic_reg_read(p, i, &val);
+ if (ret)
+ puts("PMIC: Registers dump failed\n");
+
+ if (!(i % 8))
+ printf("\n0x%02x: ", i);
+
+ printf("%08x ", val);
+ }
+ puts("\n");
+ return 0;
+}
+
+static const char *power_get_interface(int interface)
{
const char *power_interface[] = {"I2C", "SPI", "|+|-|"};
return power_interface[interface];
@@ -125,7 +121,7 @@ static void pmic_list_names(void)
}
}
-int do_pmic(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_pmic(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
u32 ret, reg, val;
char *cmd, *name;
@@ -221,3 +217,4 @@ U_BOOT_CMD(
"pmic name bat state - write register\n"
"pmic name bat charge - write register\n"
);
+#endif
diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
index 26fb9368ea..5b4ac10462 100644
--- a/drivers/power/regulator/Kconfig
+++ b/drivers/power/regulator/Kconfig
@@ -101,6 +101,14 @@ config REGULATOR_RK8XX
by the PMIC device. This driver is controlled by a device tree node
which includes voltage limits.
+config DM_REGULATOR_S2MPS11
+ bool "Enable driver for S2MPS11 regulator"
+ depends on DM_REGULATOR && PMIC_S2MPS11
+ ---help---
+ This enables implementation of driver-model regulator uclass
+ features for REGULATOR S2MPS11.
+ The driver implements get/set api for: value and enable.
+
config REGULATOR_S5M8767
bool "Enable support for S5M8767 regulator"
depends on DM_REGULATOR && PMIC_S5M8767
diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile
index 7a2e76dc82..728e8144de 100644
--- a/drivers/power/regulator/Makefile
+++ b/drivers/power/regulator/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_REGULATOR_PWM) += pwm_regulator.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_FIXED) += fixed.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_GPIO) += gpio-regulator.o
obj-$(CONFIG_REGULATOR_RK8XX) += rk8xx.o
+obj-$(CONFIG_DM_REGULATOR_S2MPS11) += s2mps11_regulator.o
obj-$(CONFIG_REGULATOR_S5M8767) += s5m8767.o
obj-$(CONFIG_DM_REGULATOR_SANDBOX) += sandbox.o
obj-$(CONFIG_REGULATOR_TPS65090) += tps65090_regulator.o
diff --git a/drivers/power/regulator/s2mps11_regulator.c b/drivers/power/regulator/s2mps11_regulator.c
new file mode 100644
index 0000000000..3af20e60dd
--- /dev/null
+++ b/drivers/power/regulator/s2mps11_regulator.c
@@ -0,0 +1,597 @@
+/*
+ * Copyright (C) 2018 Samsung Electronics
+ * Jaehoon Chung <jh80.chung@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <errno.h>
+#include <dm.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/s2mps11.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MODE(_id, _val, _name) { \
+ .id = _id, \
+ .register_value = _val, \
+ .name = _name, \
+}
+
+/* BUCK : 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 */
+static struct dm_regulator_mode s2mps11_buck_modes[] = {
+ MODE(OP_OFF, S2MPS11_BUCK_MODE_OFF, "OFF"),
+ MODE(OP_STANDBY, S2MPS11_BUCK_MODE_STANDBY, "ON/OFF"),
+ MODE(OP_ON, S2MPS11_BUCK_MODE_STANDBY, "ON"),
+};
+
+static struct dm_regulator_mode s2mps11_ldo_modes[] = {
+ MODE(OP_OFF, S2MPS11_LDO_MODE_OFF, "OFF"),
+ MODE(OP_STANDBY, S2MPS11_LDO_MODE_STANDBY, "ON/OFF"),
+ MODE(OP_STANDBY_LPM, S2MPS11_LDO_MODE_STANDBY_LPM, "ON/LPM"),
+ MODE(OP_ON, S2MPS11_LDO_MODE_ON, "ON"),
+};
+
+static const char s2mps11_buck_ctrl[] = {
+ 0xff, 0x25, 0x27, 0x29, 0x2b, 0x2d, 0x33, 0x35, 0x37, 0x39, 0x3b
+};
+
+static const char s2mps11_buck_out[] = {
+ 0xff, 0x26, 0x28, 0x2a, 0x2c, 0x2f, 0x34, 0x36, 0x38, 0x3a, 0x3c
+};
+
+static int s2mps11_buck_hex2volt(int buck, int hex)
+{
+ unsigned int uV = 0;
+
+ if (hex < 0)
+ goto bad;
+
+ switch (buck) {
+ case 7:
+ case 8:
+ case 10:
+ if (hex > S2MPS11_BUCK7_8_10_VOLT_MAX_HEX)
+ goto bad;
+
+ uV = hex * S2MPS11_BUCK_HSTEP + S2MPS11_BUCK_UV_HMIN;
+ break;
+ case 9:
+ if (hex > S2MPS11_BUCK9_VOLT_MAX_HEX)
+ goto bad;
+ uV = hex * S2MPS11_BUCK9_STEP * 2 + S2MPS11_BUCK9_UV_MIN;
+ break;
+ default:
+ if (buck == 5 && hex > S2MPS11_BUCK5_VOLT_MAX_HEX)
+ goto bad;
+ else if (buck != 5 && hex > S2MPS11_BUCK_VOLT_MAX_HEX)
+ goto bad;
+
+ uV = hex * S2MPS11_BUCK_LSTEP + S2MPS11_BUCK_UV_MIN;
+ break;
+ }
+
+ return uV;
+bad:
+ pr_err("Value: %#x is wrong for BUCK%d", hex, buck);
+ return -EINVAL;
+}
+
+static int s2mps11_buck_volt2hex(int buck, int uV)
+{
+ int hex;
+
+ switch (buck) {
+ case 7:
+ case 8:
+ case 10:
+ hex = (uV - S2MPS11_BUCK_UV_HMIN) / S2MPS11_BUCK_HSTEP;
+ if (hex > S2MPS11_BUCK7_8_10_VOLT_MAX_HEX)
+ goto bad;
+
+ break;
+ case 9:
+ hex = (uV - S2MPS11_BUCK9_UV_MIN) / S2MPS11_BUCK9_STEP;
+ if (hex > S2MPS11_BUCK9_VOLT_MAX_HEX)
+ goto bad;
+ break;
+ default:
+ hex = (uV - S2MPS11_BUCK_UV_MIN) / S2MPS11_BUCK_LSTEP;
+ if (buck == 5 && hex > S2MPS11_BUCK5_VOLT_MAX_HEX)
+ goto bad;
+ else if (buck != 5 && hex > S2MPS11_BUCK_VOLT_MAX_HEX)
+ goto bad;
+ break;
+ };
+
+ if (hex >= 0)
+ return hex;
+
+bad:
+ pr_err("Value: %d uV is wrong for BUCK%d", uV, buck);
+ return -EINVAL;
+}
+
+static int s2mps11_buck_val(struct udevice *dev, int op, int *uV)
+{
+ int hex, buck, ret;
+ u32 mask, addr;
+ u8 val;
+
+ buck = dev->driver_data;
+ if (buck < 1 || buck > S2MPS11_BUCK_NUM) {
+ pr_err("Wrong buck number: %d\n", buck);
+ return -EINVAL;
+ }
+
+ if (op == PMIC_OP_GET)
+ *uV = 0;
+
+ addr = s2mps11_buck_out[buck];
+
+ switch (buck) {
+ case 9:
+ mask = S2MPS11_BUCK9_VOLT_MASK;
+ break;
+ default:
+ mask = S2MPS11_BUCK_VOLT_MASK;
+ break;
+ }
+
+ ret = pmic_read(dev->parent, addr, &val, 1);
+ if (ret)
+ return ret;
+
+ if (op == PMIC_OP_GET) {
+ val &= mask;
+ ret = s2mps11_buck_hex2volt(buck, val);
+ if (ret < 0)
+ return ret;
+ *uV = ret;
+ return 0;
+ }
+
+ hex = s2mps11_buck_volt2hex(buck, *uV);
+ if (hex < 0)
+ return hex;
+
+ val &= ~mask;
+ val |= hex;
+ ret = pmic_write(dev->parent, addr, &val, 1);
+
+ return ret;
+}
+
+static int s2mps11_buck_mode(struct udevice *dev, int op, int *opmode)
+{
+ unsigned int addr, mode;
+ unsigned char val;
+ int buck, ret;
+
+ buck = dev->driver_data;
+ if (buck < 1 || buck > S2MPS11_BUCK_NUM) {
+ pr_err("Wrong buck number: %d\n", buck);
+ return -EINVAL;
+ }
+
+ addr = s2mps11_buck_ctrl[buck];
+
+ ret = pmic_read(dev->parent, addr, &val, 1);
+ if (ret)
+ return ret;
+
+ if (op == PMIC_OP_GET) {
+ val &= (S2MPS11_BUCK_MODE_MASK << S2MPS11_BUCK_MODE_SHIFT);
+ switch (val) {
+ case S2MPS11_BUCK_MODE_OFF:
+ *opmode = OP_OFF;
+ break;
+ case S2MPS11_BUCK_MODE_STANDBY:
+ *opmode = OP_STANDBY;
+ break;
+ case S2MPS11_BUCK_MODE_ON:
+ *opmode = OP_ON;
+ break;
+ default:
+ return -EINVAL;
+ }
+ return 0;
+ }
+
+ switch (*opmode) {
+ case OP_OFF:
+ mode = S2MPS11_BUCK_MODE_OFF;
+ break;
+ case OP_STANDBY:
+ mode = S2MPS11_BUCK_MODE_STANDBY;
+ break;
+ case OP_ON:
+ mode = S2MPS11_BUCK_MODE_ON;
+ break;
+ default:
+ pr_err("Wrong mode: %d for buck: %d\n", *opmode, buck);
+ return -EINVAL;
+ }
+
+ val &= ~(S2MPS11_BUCK_MODE_MASK << S2MPS11_BUCK_MODE_SHIFT);
+ val |= mode;
+ ret = pmic_write(dev->parent, addr, &val, 1);
+
+ return ret;
+}
+
+static int s2mps11_buck_enable(struct udevice *dev, int op, bool *enable)
+{
+ int ret, on_off;
+
+ if (op == PMIC_OP_GET) {
+ ret = s2mps11_buck_mode(dev, op, &on_off);
+ if (ret)
+ return ret;
+ switch (on_off) {
+ case OP_OFF:
+ *enable = false;
+ break;
+ case OP_ON:
+ *enable = true;
+ break;
+ default:
+ return -EINVAL;
+ }
+ } else if (op == PMIC_OP_SET) {
+ if (*enable)
+ on_off = OP_ON;
+ else
+ on_off = OP_OFF;
+
+ ret = s2mps11_buck_mode(dev, op, &on_off);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int buck_get_value(struct udevice *dev)
+{
+ int uV;
+ int ret;
+
+ ret = s2mps11_buck_val(dev, PMIC_OP_GET, &uV);
+ if (ret)
+ return ret;
+ return uV;
+}
+
+static int buck_set_value(struct udevice *dev, int uV)
+{
+ return s2mps11_buck_val(dev, PMIC_OP_SET, &uV);
+}
+
+static int buck_get_enable(struct udevice *dev)
+{
+ bool enable = false;
+ int ret;
+
+ ret = s2mps11_buck_enable(dev, PMIC_OP_GET, &enable);
+ if (ret)
+ return ret;
+ return enable;
+}
+
+static int buck_set_enable(struct udevice *dev, bool enable)
+{
+ return s2mps11_buck_enable(dev, PMIC_OP_SET, &enable);
+}
+
+static int buck_get_mode(struct udevice *dev)
+{
+ int mode;
+ int ret;
+
+ ret = s2mps11_buck_mode(dev, PMIC_OP_GET, &mode);
+ if (ret)
+ return ret;
+
+ return mode;
+}
+
+static int buck_set_mode(struct udevice *dev, int mode)
+{
+ return s2mps11_buck_mode(dev, PMIC_OP_SET, &mode);
+}
+
+static int s2mps11_buck_probe(struct udevice *dev)
+{
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+
+ uc_pdata->type = REGULATOR_TYPE_BUCK;
+ uc_pdata->mode = s2mps11_buck_modes;
+ uc_pdata->mode_count = ARRAY_SIZE(s2mps11_buck_modes);
+
+ return 0;
+}
+
+static const struct dm_regulator_ops s2mps11_buck_ops = {
+ .get_value = buck_get_value,
+ .set_value = buck_set_value,
+ .get_enable = buck_get_enable,
+ .set_enable = buck_set_enable,
+ .get_mode = buck_get_mode,
+ .set_mode = buck_set_mode,
+};
+
+U_BOOT_DRIVER(s2mps11_buck) = {
+ .name = S2MPS11_BUCK_DRIVER,
+ .id = UCLASS_REGULATOR,
+ .ops = &s2mps11_buck_ops,
+ .probe = s2mps11_buck_probe,
+};
+
+static int s2mps11_ldo_hex2volt(int ldo, int hex)
+{
+ unsigned int uV = 0;
+
+ if (hex > S2MPS11_LDO_VOLT_MAX_HEX) {
+ pr_err("Value: %#x is wrong for LDO%d", hex, ldo);
+ return -EINVAL;
+ }
+
+ switch (ldo) {
+ case 1:
+ case 6:
+ case 11:
+ case 22:
+ case 23:
+ uV = hex * S2MPS11_LDO_STEP + S2MPS11_LDO_UV_MIN;
+ break;
+ default:
+ uV = hex * S2MPS11_LDO_STEP * 2 + S2MPS11_LDO_UV_MIN;
+ break;
+ }
+
+ return uV;
+}
+
+static int s2mps11_ldo_volt2hex(int ldo, int uV)
+{
+ int hex = 0;
+
+ switch (ldo) {
+ case 1:
+ case 6:
+ case 11:
+ case 22:
+ case 23:
+ hex = (uV - S2MPS11_LDO_UV_MIN) / S2MPS11_LDO_STEP;
+ break;
+ default:
+ hex = (uV - S2MPS11_LDO_UV_MIN) / (S2MPS11_LDO_STEP * 2);
+ break;
+ }
+
+ if (hex >= 0 && hex <= S2MPS11_LDO_VOLT_MAX_HEX)
+ return hex;
+
+ pr_err("Value: %d uV is wrong for LDO%d", uV, ldo);
+ return -EINVAL;
+
+ return 0;
+}
+
+static int s2mps11_ldo_val(struct udevice *dev, int op, int *uV)
+{
+ unsigned int addr;
+ unsigned char val;
+ int hex, ldo, ret;
+
+ ldo = dev->driver_data;
+ if (ldo < 1 || ldo > S2MPS11_LDO_NUM) {
+ pr_err("Wrong ldo number: %d\n", ldo);
+ return -EINVAL;
+ }
+
+ addr = S2MPS11_REG_L1CTRL + ldo - 1;
+
+ ret = pmic_read(dev->parent, addr, &val, 1);
+ if (ret)
+ return ret;
+
+ if (op == PMIC_OP_GET) {
+ *uV = 0;
+ val &= S2MPS11_LDO_VOLT_MASK;
+ ret = s2mps11_ldo_hex2volt(ldo, val);
+ if (ret < 0)
+ return ret;
+
+ *uV = ret;
+ return 0;
+ }
+
+ hex = s2mps11_ldo_volt2hex(ldo, *uV);
+ if (hex < 0)
+ return hex;
+
+ val &= ~S2MPS11_LDO_VOLT_MASK;
+ val |= hex;
+ ret = pmic_write(dev->parent, addr, &val, 1);
+
+ return ret;
+}
+
+static int s2mps11_ldo_mode(struct udevice *dev, int op, int *opmode)
+{
+ unsigned int addr, mode;
+ unsigned char val;
+ int ldo, ret;
+
+ ldo = dev->driver_data;
+ if (ldo < 1 || ldo > S2MPS11_LDO_NUM) {
+ pr_err("Wrong ldo number: %d\n", ldo);
+ return -EINVAL;
+ }
+ addr = S2MPS11_REG_L1CTRL + ldo - 1;
+
+ ret = pmic_read(dev->parent, addr, &val, 1);
+ if (ret)
+ return ret;
+
+ if (op == PMIC_OP_GET) {
+ val &= (S2MPS11_LDO_MODE_MASK << S2MPS11_LDO_MODE_SHIFT);
+ switch (val) {
+ case S2MPS11_LDO_MODE_OFF:
+ *opmode = OP_OFF;
+ break;
+ case S2MPS11_LDO_MODE_STANDBY:
+ *opmode = OP_STANDBY;
+ break;
+ case S2MPS11_LDO_MODE_STANDBY_LPM:
+ *opmode = OP_STANDBY_LPM;
+ break;
+ case S2MPS11_LDO_MODE_ON:
+ *opmode = OP_ON;
+ break;
+ default:
+ return -EINVAL;
+ }
+ return 0;
+ }
+
+ switch (*opmode) {
+ case OP_OFF:
+ mode = S2MPS11_LDO_MODE_OFF;
+ break;
+ case OP_STANDBY:
+ mode = S2MPS11_LDO_MODE_STANDBY;
+ break;
+ case OP_STANDBY_LPM:
+ mode = S2MPS11_LDO_MODE_STANDBY_LPM;
+ break;
+ case OP_ON:
+ mode = S2MPS11_LDO_MODE_ON;
+ break;
+ default:
+ pr_err("Wrong mode: %d for ldo: %d\n", *opmode, ldo);
+ return -EINVAL;
+ }
+
+ val &= ~(S2MPS11_LDO_MODE_MASK << S2MPS11_LDO_MODE_SHIFT);
+ val |= mode;
+ ret = pmic_write(dev->parent, addr, &val, 1);
+
+ return ret;
+}
+
+static int s2mps11_ldo_enable(struct udevice *dev, int op, bool *enable)
+{
+ int ret, on_off;
+
+ if (op == PMIC_OP_GET) {
+ ret = s2mps11_ldo_mode(dev, op, &on_off);
+ if (ret)
+ return ret;
+ switch (on_off) {
+ case OP_OFF:
+ *enable = false;
+ break;
+ case OP_ON:
+ *enable = true;
+ break;
+ default:
+ return -EINVAL;
+ }
+ } else if (op == PMIC_OP_SET) {
+ if (*enable)
+ on_off = OP_ON;
+ else
+ on_off = OP_OFF;
+
+ ret = s2mps11_ldo_mode(dev, op, &on_off);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ldo_get_value(struct udevice *dev)
+{
+ int uV;
+ int ret;
+
+ ret = s2mps11_ldo_val(dev, PMIC_OP_GET, &uV);
+ if (ret)
+ return ret;
+
+ return uV;
+}
+
+static int ldo_set_value(struct udevice *dev, int uV)
+{
+ return s2mps11_ldo_val(dev, PMIC_OP_SET, &uV);
+}
+
+static int ldo_get_enable(struct udevice *dev)
+{
+ bool enable = false;
+ int ret;
+
+ ret = s2mps11_ldo_enable(dev, PMIC_OP_GET, &enable);
+ if (ret)
+ return ret;
+ return enable;
+}
+
+static int ldo_set_enable(struct udevice *dev, bool enable)
+{
+ return s2mps11_ldo_enable(dev, PMIC_OP_SET, &enable);
+}
+
+static int ldo_get_mode(struct udevice *dev)
+{
+ int mode, ret;
+
+ ret = s2mps11_ldo_mode(dev, PMIC_OP_GET, &mode);
+ if (ret)
+ return ret;
+ return mode;
+}
+
+static int ldo_set_mode(struct udevice *dev, int mode)
+{
+ return s2mps11_ldo_mode(dev, PMIC_OP_SET, &mode);
+}
+
+static int s2mps11_ldo_probe(struct udevice *dev)
+{
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata->type = REGULATOR_TYPE_LDO;
+ uc_pdata->mode = s2mps11_ldo_modes;
+ uc_pdata->mode_count = ARRAY_SIZE(s2mps11_ldo_modes);
+
+ return 0;
+}
+
+static const struct dm_regulator_ops s2mps11_ldo_ops = {
+ .get_value = ldo_get_value,
+ .set_value = ldo_set_value,
+ .get_enable = ldo_get_enable,
+ .set_enable = ldo_set_enable,
+ .get_mode = ldo_get_mode,
+ .set_mode = ldo_set_mode,
+};
+
+U_BOOT_DRIVER(s2mps11_ldo) = {
+ .name = S2MPS11_LDO_DRIVER,
+ .id = UCLASS_REGULATOR,
+ .ops = &s2mps11_ldo_ops,
+ .probe = s2mps11_ldo_probe,
+};
diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c
index 6e92b2222d..ec2edd67dd 100644
--- a/drivers/ram/stm32_sdram.c
+++ b/drivers/ram/stm32_sdram.c
@@ -11,6 +11,9 @@
#include <ram.h>
#include <asm/io.h>
+#define MEM_MODE_MASK GENMASK(2, 0)
+#define NOT_FOUND 0xff
+
DECLARE_GLOBAL_DATA_PTR;
struct stm32_fmc_regs {
@@ -253,9 +256,31 @@ static int stm32_fmc_ofdata_to_platdata(struct udevice *dev)
{
struct stm32_sdram_params *params = dev_get_platdata(dev);
struct bank_params *bank_params;
+ struct ofnode_phandle_args args;
+ u32 *syscfg_base;
+ u32 mem_remap;
ofnode bank_node;
char *bank_name;
u8 bank = 0;
+ int ret;
+
+ mem_remap = dev_read_u32_default(dev, "st,mem_remap", NOT_FOUND);
+ if (mem_remap != NOT_FOUND) {
+ ret = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
+ &args);
+ if (ret) {
+ debug("%s: can't find syscon device (%d)\n", __func__,
+ ret);
+ return ret;
+ }
+
+ syscfg_base = (u32 *)ofnode_get_addr(args.node);
+
+ /* set memory mapping selection */
+ clrsetbits_le32(syscfg_base, MEM_MODE_MASK, mem_remap);
+ } else {
+ debug("%s: cannot find st,mem_remap property\n", __func__);
+ }
dev_for_each_subnode(bank_node, dev) {
/* extract the bank index from DT */
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 122b8e786a..7b20b47964 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -529,7 +529,7 @@ config STI_ASC_SERIAL
on STiH410 SoC. This is a basic implementation, it supports
following baudrate 9600, 19200, 38400, 57600 and 115200.
-config STM32X7_SERIAL
+config STM32_SERIAL
bool "STMicroelectronics STM32 SoCs on-chip UART"
depends on DM_SERIAL && (STM32F4 || STM32F7 || STM32H7)
help
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 7adcee3e10..5ef603ab15 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -44,7 +44,7 @@ obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o
obj-$(CONFIG_STI_ASC_SERIAL) += serial_sti_asc.o
obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o
-obj-$(CONFIG_STM32X7_SERIAL) += serial_stm32x7.o
+obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o
obj-$(CONFIG_BCM283X_MU_SERIAL) += serial_bcm283x_mu.o
obj-$(CONFIG_MSM_SERIAL) += serial_msm.o
obj-$(CONFIG_MVEBU_A3700_UART) += serial_mvebu_a3700.o
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index 382f8ba5b5..536d30f66a 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -265,11 +265,9 @@ static int _lpuart32_serial_getc(struct lpuart_serial_platdata *plat)
lpuart_read32(plat->flags, &base->data, &val);
- if (plat->devtype & DEV_MX7ULP) {
- lpuart_read32(plat->flags, &base->stat, &stat);
- if (stat & STAT_OR)
- lpuart_write32(plat->flags, &base->stat, STAT_OR);
- }
+ lpuart_read32(plat->flags, &base->stat, &stat);
+ if (stat & STAT_OR)
+ lpuart_write32(plat->flags, &base->stat, STAT_OR);
return val & 0x3ff;
}
@@ -280,10 +278,8 @@ static void _lpuart32_serial_putc(struct lpuart_serial_platdata *plat,
struct lpuart_fsl_reg32 *base = plat->reg;
u32 stat;
- if (plat->devtype & DEV_MX7ULP) {
- if (c == '\n')
- serial_putc('\r');
- }
+ if (c == '\n')
+ serial_putc('\r');
while (true) {
lpuart_read32(plat->flags, &base->stat, &stat);
@@ -330,7 +326,7 @@ static int _lpuart32_serial_init(struct lpuart_serial_platdata *plat)
lpuart_write32(plat->flags, &base->match, 0);
- if (plat->devtype & DEV_MX7ULP) {
+ if (plat->devtype == DEV_MX7ULP) {
_lpuart32_serial_setbrg_7ulp(plat, gd->baudrate);
} else {
/* provide data bits, parity, stop bit, etc */
@@ -347,7 +343,7 @@ static int lpuart_serial_setbrg(struct udevice *dev, int baudrate)
struct lpuart_serial_platdata *plat = dev->platdata;
if (is_lpuart32(dev)) {
- if (plat->devtype & DEV_MX7ULP)
+ if (plat->devtype == DEV_MX7ULP)
_lpuart32_serial_setbrg_7ulp(plat, baudrate);
else
_lpuart32_serial_setbrg(plat, baudrate);
diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c
index c793ba6e90..286b954fdd 100644
--- a/drivers/serial/serial_stm32.c
+++ b/drivers/serial/serial_stm32.c
@@ -1,102 +1,141 @@
/*
- * (C) Copyright 2015
- * Kamil Lulko, <kamil.lulko@gmail.com>
+ * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <clk.h>
#include <dm.h>
#include <asm/io.h>
#include <serial.h>
#include <asm/arch/stm32.h>
-#include <dm/platform_data/serial_stm32.h>
-
-struct stm32_usart {
- u32 sr;
- u32 dr;
- u32 brr;
- u32 cr1;
- u32 cr2;
- u32 cr3;
- u32 gtpr;
-};
-
-#define USART_CR1_RE (1 << 2)
-#define USART_CR1_TE (1 << 3)
-#define USART_CR1_UE (1 << 13)
-
-#define USART_SR_FLAG_RXNE (1 << 5)
-#define USART_SR_FLAG_TXE (1 << 7)
-
-#define USART_BRR_F_MASK 0xF
-#define USART_BRR_M_SHIFT 4
-#define USART_BRR_M_MASK 0xFFF0
+#include "serial_stm32.h"
DECLARE_GLOBAL_DATA_PTR;
static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
{
- struct stm32_serial_platdata *plat = dev->platdata;
- struct stm32_usart *const usart = plat->base;
- u32 clock, int_div, frac_div, tmp;
-
- if (((u32)usart & STM32_BUS_MASK) == STM32_APB1PERIPH_BASE)
- clock = clock_get(CLOCK_APB1);
- else if (((u32)usart & STM32_BUS_MASK) == STM32_APB2PERIPH_BASE)
- clock = clock_get(CLOCK_APB2);
- else
- return -EINVAL;
+ struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+ bool stm32f4 = plat->uart_info->stm32f4;
+ fdt_addr_t base = plat->base;
+ u32 int_div, mantissa, fraction, oversampling;
+
+ int_div = DIV_ROUND_CLOSEST(plat->clock_rate, baudrate);
+
+ if (int_div < 16) {
+ oversampling = 8;
+ setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
+ } else {
+ oversampling = 16;
+ clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
+ }
+
+ mantissa = (int_div / oversampling) << USART_BRR_M_SHIFT;
+ fraction = int_div % oversampling;
- int_div = (25 * clock) / (4 * baudrate);
- tmp = ((int_div / 100) << USART_BRR_M_SHIFT) & USART_BRR_M_MASK;
- frac_div = int_div - (100 * (tmp >> USART_BRR_M_SHIFT));
- tmp |= (((frac_div * 16) + 50) / 100) & USART_BRR_F_MASK;
- writel(tmp, &usart->brr);
+ writel(mantissa | fraction, base + BRR_OFFSET(stm32f4));
return 0;
}
static int stm32_serial_getc(struct udevice *dev)
{
- struct stm32_serial_platdata *plat = dev->platdata;
- struct stm32_usart *const usart = plat->base;
+ struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+ bool stm32f4 = plat->uart_info->stm32f4;
+ fdt_addr_t base = plat->base;
- if ((readl(&usart->sr) & USART_SR_FLAG_RXNE) == 0)
+ if ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_RXNE) == 0)
return -EAGAIN;
- return readl(&usart->dr);
+ return readl(base + RDR_OFFSET(stm32f4));
}
static int stm32_serial_putc(struct udevice *dev, const char c)
{
- struct stm32_serial_platdata *plat = dev->platdata;
- struct stm32_usart *const usart = plat->base;
+ struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+ bool stm32f4 = plat->uart_info->stm32f4;
+ fdt_addr_t base = plat->base;
- if ((readl(&usart->sr) & USART_SR_FLAG_TXE) == 0)
+ if ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_TXE) == 0)
return -EAGAIN;
- writel(c, &usart->dr);
+ writel(c, base + TDR_OFFSET(stm32f4));
return 0;
}
static int stm32_serial_pending(struct udevice *dev, bool input)
{
- struct stm32_serial_platdata *plat = dev->platdata;
- struct stm32_usart *const usart = plat->base;
+ struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+ bool stm32f4 = plat->uart_info->stm32f4;
+ fdt_addr_t base = plat->base;
if (input)
- return readl(&usart->sr) & USART_SR_FLAG_RXNE ? 1 : 0;
+ return readl(base + ISR_OFFSET(stm32f4)) &
+ USART_SR_FLAG_RXNE ? 1 : 0;
else
- return readl(&usart->sr) & USART_SR_FLAG_TXE ? 0 : 1;
+ return readl(base + ISR_OFFSET(stm32f4)) &
+ USART_SR_FLAG_TXE ? 0 : 1;
}
static int stm32_serial_probe(struct udevice *dev)
{
- struct stm32_serial_platdata *plat = dev->platdata;
- struct stm32_usart *const usart = plat->base;
- setbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE);
+ struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+ struct clk clk;
+ fdt_addr_t base = plat->base;
+ int ret;
+ bool stm32f4;
+ u8 uart_enable_bit;
+
+ plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev);
+ stm32f4 = plat->uart_info->stm32f4;
+ uart_enable_bit = plat->uart_info->uart_enable_bit;
+
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_enable(&clk);
+ if (ret) {
+ dev_err(dev, "failed to enable clock\n");
+ return ret;
+ }
+
+ plat->clock_rate = clk_get_rate(&clk);
+ if (plat->clock_rate < 0) {
+ clk_disable(&clk);
+ return plat->clock_rate;
+ };
+
+ /* Disable uart-> disable overrun-> enable uart */
+ clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
+ BIT(uart_enable_bit));
+ if (plat->uart_info->has_overrun_disable)
+ setbits_le32(base + CR3_OFFSET(stm32f4), USART_CR3_OVRDIS);
+ if (plat->uart_info->has_fifo)
+ setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_FIFOEN);
+ setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
+ BIT(uart_enable_bit));
+
+ return 0;
+}
+
+static const struct udevice_id stm32_serial_id[] = {
+ { .compatible = "st,stm32-uart", .data = (ulong)&stm32f4_info},
+ { .compatible = "st,stm32f7-uart", .data = (ulong)&stm32f7_info},
+ { .compatible = "st,stm32h7-uart", .data = (ulong)&stm32h7_info},
+ {}
+};
+
+static int stm32_serial_ofdata_to_platdata(struct udevice *dev)
+{
+ struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+
+ plat->base = devfdt_get_addr(dev);
+ if (plat->base == FDT_ADDR_T_NONE)
+ return -EINVAL;
return 0;
}
@@ -111,6 +150,9 @@ static const struct dm_serial_ops stm32_serial_ops = {
U_BOOT_DRIVER(serial_stm32) = {
.name = "serial_stm32",
.id = UCLASS_SERIAL,
+ .of_match = of_match_ptr(stm32_serial_id),
+ .ofdata_to_platdata = of_match_ptr(stm32_serial_ofdata_to_platdata),
+ .platdata_auto_alloc_size = sizeof(struct stm32x7_serial_platdata),
.ops = &stm32_serial_ops,
.probe = stm32_serial_probe,
.flags = DM_FLAG_PRE_RELOC,
diff --git a/drivers/serial/serial_stm32x7.h b/drivers/serial/serial_stm32.h
index f7dca39103..d08ba1f55f 100644
--- a/drivers/serial/serial_stm32x7.h
+++ b/drivers/serial/serial_stm32.h
@@ -5,8 +5,8 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef _SERIAL_STM32_X7_
-#define _SERIAL_STM32_X7_
+#ifndef _SERIAL_STM32_
+#define _SERIAL_STM32_
#define CR1_OFFSET(x) (x ? 0x0c : 0x00)
#define CR3_OFFSET(x) (x ? 0x14 : 0x08)
diff --git a/drivers/serial/serial_stm32x7.c b/drivers/serial/serial_stm32x7.c
deleted file mode 100644
index d1580e3cb5..0000000000
--- a/drivers/serial/serial_stm32x7.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <clk.h>
-#include <dm.h>
-#include <asm/io.h>
-#include <serial.h>
-#include <asm/arch/stm32.h>
-#include "serial_stm32x7.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
-{
- struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
- bool stm32f4 = plat->uart_info->stm32f4;
- fdt_addr_t base = plat->base;
- u32 int_div, mantissa, fraction, oversampling;
-
- int_div = DIV_ROUND_CLOSEST(plat->clock_rate, baudrate);
-
- if (int_div < 16) {
- oversampling = 8;
- setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
- } else {
- oversampling = 16;
- clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
- }
-
- mantissa = (int_div / oversampling) << USART_BRR_M_SHIFT;
- fraction = int_div % oversampling;
-
- writel(mantissa | fraction, base + BRR_OFFSET(stm32f4));
-
- return 0;
-}
-
-static int stm32_serial_getc(struct udevice *dev)
-{
- struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
- bool stm32f4 = plat->uart_info->stm32f4;
- fdt_addr_t base = plat->base;
-
- if ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_RXNE) == 0)
- return -EAGAIN;
-
- return readl(base + RDR_OFFSET(stm32f4));
-}
-
-static int stm32_serial_putc(struct udevice *dev, const char c)
-{
- struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
- bool stm32f4 = plat->uart_info->stm32f4;
- fdt_addr_t base = plat->base;
-
- if ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_TXE) == 0)
- return -EAGAIN;
-
- writel(c, base + TDR_OFFSET(stm32f4));
-
- return 0;
-}
-
-static int stm32_serial_pending(struct udevice *dev, bool input)
-{
- struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
- bool stm32f4 = plat->uart_info->stm32f4;
- fdt_addr_t base = plat->base;
-
- if (input)
- return readl(base + ISR_OFFSET(stm32f4)) &
- USART_SR_FLAG_RXNE ? 1 : 0;
- else
- return readl(base + ISR_OFFSET(stm32f4)) &
- USART_SR_FLAG_TXE ? 0 : 1;
-}
-
-static int stm32_serial_probe(struct udevice *dev)
-{
- struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
- struct clk clk;
- fdt_addr_t base = plat->base;
- int ret;
- bool stm32f4;
- u8 uart_enable_bit;
-
- plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev);
- stm32f4 = plat->uart_info->stm32f4;
- uart_enable_bit = plat->uart_info->uart_enable_bit;
-
- ret = clk_get_by_index(dev, 0, &clk);
- if (ret < 0)
- return ret;
-
- ret = clk_enable(&clk);
- if (ret) {
- dev_err(dev, "failed to enable clock\n");
- return ret;
- }
-
- plat->clock_rate = clk_get_rate(&clk);
- if (plat->clock_rate < 0) {
- clk_disable(&clk);
- return plat->clock_rate;
- };
-
- /* Disable uart-> disable overrun-> enable uart */
- clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
- BIT(uart_enable_bit));
- if (plat->uart_info->has_overrun_disable)
- setbits_le32(base + CR3_OFFSET(stm32f4), USART_CR3_OVRDIS);
- if (plat->uart_info->has_fifo)
- setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_FIFOEN);
- setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
- BIT(uart_enable_bit));
-
- return 0;
-}
-
-static const struct udevice_id stm32_serial_id[] = {
- { .compatible = "st,stm32-uart", .data = (ulong)&stm32f4_info},
- { .compatible = "st,stm32f7-uart", .data = (ulong)&stm32f7_info},
- { .compatible = "st,stm32h7-uart", .data = (ulong)&stm32h7_info},
- {}
-};
-
-static int stm32_serial_ofdata_to_platdata(struct udevice *dev)
-{
- struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
-
- plat->base = devfdt_get_addr(dev);
- if (plat->base == FDT_ADDR_T_NONE)
- return -EINVAL;
-
- return 0;
-}
-
-static const struct dm_serial_ops stm32_serial_ops = {
- .putc = stm32_serial_putc,
- .pending = stm32_serial_pending,
- .getc = stm32_serial_getc,
- .setbrg = stm32_serial_setbrg,
-};
-
-U_BOOT_DRIVER(serial_stm32) = {
- .name = "serial_stm32x7",
- .id = UCLASS_SERIAL,
- .of_match = of_match_ptr(stm32_serial_id),
- .ofdata_to_platdata = of_match_ptr(stm32_serial_ofdata_to_platdata),
- .platdata_auto_alloc_size = sizeof(struct stm32x7_serial_platdata),
- .ops = &stm32_serial_ops,
- .probe = stm32_serial_probe,
- .flags = DM_FLAG_PRE_RELOC,
-};
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 28ddcf85a3..1e95dc4559 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -233,6 +233,12 @@ config ATCSPI200_SPI
used to access the SPI flash on AE3XX and AE250 platforms embedding
this Andestech IP core.
+config DAVINCI_SPI
+ bool "Davinci & Keystone SPI driver"
+ depends on ARCH_DAVINCI || ARCH_KEYSTONE
+ help
+ Enable the Davinci SPI driver
+
config TI_QSPI
bool "TI QSPI driver"
help
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index eed52c15c8..5dc69a6865 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -20,7 +20,8 @@
DECLARE_GLOBAL_DATA_PTR;
#define RX_BUFFER_SIZE 0x80
-#ifdef CONFIG_MX6SX
+#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
+ defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D)
#define TX_BUFFER_SIZE 0x200
#else
#define TX_BUFFER_SIZE 0x40
@@ -268,7 +269,8 @@ static void qspi_set_lut(struct fsl_qspi_priv *priv)
INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
#endif
-#ifdef CONFIG_MX6SX
+#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
+ defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D)
/*
* To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly.
* So, Use IDATSZ in IPCR to determine the size and here set 0.
@@ -905,6 +907,11 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
qspi->slave.max_write_size = TX_BUFFER_SIZE;
mcr_val = qspi_read32(qspi->priv.flags, &regs->mcr);
+
+ /* Set endianness to LE for i.mx */
+ if (IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7))
+ mcr_val = QSPI_MCR_END_CFD_LE;
+
qspi_write32(qspi->priv.flags, &regs->mcr,
QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
(mcr_val & QSPI_MCR_END_CFD_MASK));
@@ -1023,6 +1030,11 @@ static int fsl_qspi_probe(struct udevice *bus)
}
mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
+
+ /* Set endianness to LE for i.mx */
+ if (IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7))
+ mcr_val = QSPI_MCR_END_CFD_LE;
+
qspi_write32(priv->flags, &priv->regs->mcr,
QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
(mcr_val & QSPI_MCR_END_CFD_MASK));
@@ -1227,6 +1239,8 @@ static const struct dm_spi_ops fsl_qspi_ops = {
static const struct udevice_id fsl_qspi_ids[] = {
{ .compatible = "fsl,vf610-qspi" },
{ .compatible = "fsl,imx6sx-qspi" },
+ { .compatible = "fsl,imx6ul-qspi" },
+ { .compatible = "fsl,imx7d-qspi" },
{ }
};
diff --git a/drivers/spmi/spmi-msm.c b/drivers/spmi/spmi-msm.c
index c226913f9e..dd7a1ead11 100644
--- a/drivers/spmi/spmi-msm.c
+++ b/drivers/spmi/spmi-msm.c
@@ -17,6 +17,10 @@
DECLARE_GLOBAL_DATA_PTR;
+/* PMIC Arbiter configuration registers */
+#define PMIC_ARB_VERSION 0x0000
+#define PMIC_ARB_VERSION_V2_MIN 0x20010000
+
#define ARB_CHANNEL_OFFSET(n) (0x4 * (n))
#define SPMI_CH_OFFSET(chnl) ((chnl) * 0x8000)
@@ -148,6 +152,8 @@ static int msm_spmi_probe(struct udevice *dev)
struct udevice *parent = dev->parent;
struct msm_spmi_priv *priv = dev_get_priv(dev);
int node = dev_of_offset(dev);
+ u32 hw_ver;
+ bool is_v1;
int i;
priv->arb_chnl = devfdt_get_addr(dev);
@@ -155,6 +161,12 @@ static int msm_spmi_probe(struct udevice *dev)
dev_of_offset(parent), node, "reg", 1, NULL, false);
priv->spmi_obs = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
dev_of_offset(parent), node, "reg", 2, NULL, false);
+
+ hw_ver = readl(priv->arb_chnl + PMIC_ARB_VERSION - 0x800);
+ is_v1 = (hw_ver < PMIC_ARB_VERSION_V2_MIN);
+
+ dev_dbg(dev, "PMIC Arb Version-%d (0x%x)\n", (is_v1 ? 1 : 2), hw_ver);
+
if (priv->arb_chnl == FDT_ADDR_T_NONE ||
priv->spmi_core == FDT_ADDR_T_NONE ||
priv->spmi_obs == FDT_ADDR_T_NONE)
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index 2e9598e300..000c288eeb 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -8,10 +8,8 @@ obj-$(CONFIG_SYSRESET) += sysreset-uclass.o
obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o
obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o
-
obj-$(CONFIG_ARCH_ROCKCHIP) += sysreset_rockchip.o
obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
-obj-$(CONFIG_ARCH_SNAPDRAGON) += sysreset_snapdragon.o
obj-$(CONFIG_ARCH_STI) += sysreset_sti.o
obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o
obj-$(CONFIG_ARCH_ASPEED) += sysreset_ast.o
diff --git a/drivers/sysreset/sysreset_snapdragon.c b/drivers/sysreset/sysreset_snapdragon.c
deleted file mode 100644
index 9869813978..0000000000
--- a/drivers/sysreset/sysreset_snapdragon.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Qualcomm APQ8016 reset controller driver
- *
- * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <sysreset.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static int msm_sysreset_request(struct udevice *dev, enum sysreset_t type)
-{
- phys_addr_t addr = devfdt_get_addr(dev);
- if (!addr)
- return -EINVAL;
- writel(0, addr);
- return -EINPROGRESS;
-}
-
-static struct sysreset_ops msm_sysreset_ops = {
- .request = msm_sysreset_request,
-};
-
-static const struct udevice_id msm_sysreset_ids[] = {
- { .compatible = "qcom,pshold" },
- { }
-};
-
-U_BOOT_DRIVER(msm_reset) = {
- .name = "msm_sysreset",
- .id = UCLASS_SYSRESET,
- .of_match = msm_sysreset_ids,
- .ops = &msm_sysreset_ops,
-};
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index e7658b4d95..7de41057ca 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -51,10 +51,14 @@ source "drivers/usb/host/Kconfig"
source "drivers/usb/dwc3/Kconfig"
+source "drivers/usb/musb/Kconfig"
+
source "drivers/usb/musb-new/Kconfig"
source "drivers/usb/emul/Kconfig"
+source "drivers/usb/phy/Kconfig"
+
source "drivers/usb/ulpi/Kconfig"
comment "USB peripherals"
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 102a63b8ee..c387f5e497 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -134,6 +134,14 @@ config USB_FUNCTION_SDP
allows to download images into memory and execute (jump to) them
using the same protocol as implemented by the i.MX family's boot ROM.
+config USB_FUNCTION_ROCKUSB
+ bool "Enable USB rockusb gadget"
+ help
+ Rockusb protocol is widely used by Rockchip SoC based devices. It can
+ read/write info, image to/from devices. This enables the USB part of
+ the rockusb gadget.for more detail about Rockusb protocol, please see
+ doc/README.rockusb
+
endif # USB_GADGET_DOWNLOAD
config USB_ETHER
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index 7258099c1c..ee8bc994c5 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_USB_FUNCTION_DFU) += f_dfu.o
obj-$(CONFIG_USB_FUNCTION_MASS_STORAGE) += f_mass_storage.o
obj-$(CONFIG_USB_FUNCTION_FASTBOOT) += f_fastboot.o
obj-$(CONFIG_USB_FUNCTION_SDP) += f_sdp.o
+obj-$(CONFIG_USB_FUNCTION_ROCKUSB) += f_rockusb.o
endif
endif
ifdef CONFIG_USB_ETHER
diff --git a/drivers/usb/gadget/f_rockusb.c b/drivers/usb/gadget/f_rockusb.c
new file mode 100644
index 0000000000..d5a10f1904
--- /dev/null
+++ b/drivers/usb/gadget/f_rockusb.c
@@ -0,0 +1,718 @@
+/*
+ * (C) Copyright 2017
+ *
+ * Eddie Cai <eddie.cai.linux@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <config.h>
+#include <common.h>
+#include <errno.h>
+#include <malloc.h>
+#include <memalign.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/composite.h>
+#include <linux/compiler.h>
+#include <version.h>
+#include <g_dnl.h>
+#include <asm/arch/f_rockusb.h>
+
+static inline struct f_rockusb *func_to_rockusb(struct usb_function *f)
+{
+ return container_of(f, struct f_rockusb, usb_function);
+}
+
+static struct usb_endpoint_descriptor fs_ep_in = {
+ .bLength = USB_DT_ENDPOINT_SIZE,
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = USB_DIR_IN,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .wMaxPacketSize = cpu_to_le16(64),
+};
+
+static struct usb_endpoint_descriptor fs_ep_out = {
+ .bLength = USB_DT_ENDPOINT_SIZE,
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = USB_DIR_OUT,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .wMaxPacketSize = cpu_to_le16(64),
+};
+
+static struct usb_endpoint_descriptor hs_ep_in = {
+ .bLength = USB_DT_ENDPOINT_SIZE,
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = USB_DIR_IN,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .wMaxPacketSize = cpu_to_le16(512),
+};
+
+static struct usb_endpoint_descriptor hs_ep_out = {
+ .bLength = USB_DT_ENDPOINT_SIZE,
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = USB_DIR_OUT,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .wMaxPacketSize = cpu_to_le16(512),
+};
+
+static struct usb_interface_descriptor interface_desc = {
+ .bLength = USB_DT_INTERFACE_SIZE,
+ .bDescriptorType = USB_DT_INTERFACE,
+ .bInterfaceNumber = 0x00,
+ .bAlternateSetting = 0x00,
+ .bNumEndpoints = 0x02,
+ .bInterfaceClass = ROCKUSB_INTERFACE_CLASS,
+ .bInterfaceSubClass = ROCKUSB_INTERFACE_SUB_CLASS,
+ .bInterfaceProtocol = ROCKUSB_INTERFACE_PROTOCOL,
+};
+
+static struct usb_descriptor_header *rkusb_fs_function[] = {
+ (struct usb_descriptor_header *)&interface_desc,
+ (struct usb_descriptor_header *)&fs_ep_in,
+ (struct usb_descriptor_header *)&fs_ep_out,
+};
+
+static struct usb_descriptor_header *rkusb_hs_function[] = {
+ (struct usb_descriptor_header *)&interface_desc,
+ (struct usb_descriptor_header *)&hs_ep_in,
+ (struct usb_descriptor_header *)&hs_ep_out,
+ NULL,
+};
+
+static const char rkusb_name[] = "Rockchip Rockusb";
+
+static struct usb_string rkusb_string_defs[] = {
+ [0].s = rkusb_name,
+ { } /* end of list */
+};
+
+static struct usb_gadget_strings stringtab_rkusb = {
+ .language = 0x0409, /* en-us */
+ .strings = rkusb_string_defs,
+};
+
+static struct usb_gadget_strings *rkusb_strings[] = {
+ &stringtab_rkusb,
+ NULL,
+};
+
+static struct f_rockusb *rockusb_func;
+static void rx_handler_command(struct usb_ep *ep, struct usb_request *req);
+static int rockusb_tx_write_csw(u32 tag, int residue, u8 status, int size);
+
+struct f_rockusb *get_rkusb(void)
+{
+ struct f_rockusb *f_rkusb = rockusb_func;
+
+ if (!f_rkusb) {
+ f_rkusb = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*f_rkusb));
+ if (!f_rkusb)
+ return 0;
+
+ rockusb_func = f_rkusb;
+ memset(f_rkusb, 0, sizeof(*f_rkusb));
+ }
+
+ if (!f_rkusb->buf_head) {
+ f_rkusb->buf_head = memalign(CONFIG_SYS_CACHELINE_SIZE,
+ RKUSB_BUF_SIZE);
+ if (!f_rkusb->buf_head)
+ return 0;
+
+ f_rkusb->buf = f_rkusb->buf_head;
+ memset(f_rkusb->buf_head, 0, RKUSB_BUF_SIZE);
+ }
+ return f_rkusb;
+}
+
+static struct usb_endpoint_descriptor *rkusb_ep_desc(
+struct usb_gadget *g,
+struct usb_endpoint_descriptor *fs,
+struct usb_endpoint_descriptor *hs)
+{
+ if (gadget_is_dualspeed(g) && g->speed == USB_SPEED_HIGH)
+ return hs;
+ return fs;
+}
+
+static void rockusb_complete(struct usb_ep *ep, struct usb_request *req)
+{
+ int status = req->status;
+
+ if (!status)
+ return;
+ debug("status: %d ep '%s' trans: %d\n", status, ep->name, req->actual);
+}
+
+/* config the rockusb device*/
+static int rockusb_bind(struct usb_configuration *c, struct usb_function *f)
+{
+ int id;
+ struct usb_gadget *gadget = c->cdev->gadget;
+ struct f_rockusb *f_rkusb = func_to_rockusb(f);
+ const char *s;
+
+ id = usb_interface_id(c, f);
+ if (id < 0)
+ return id;
+ interface_desc.bInterfaceNumber = id;
+
+ id = usb_string_id(c->cdev);
+ if (id < 0)
+ return id;
+
+ rkusb_string_defs[0].id = id;
+ interface_desc.iInterface = id;
+
+ f_rkusb->in_ep = usb_ep_autoconfig(gadget, &fs_ep_in);
+ if (!f_rkusb->in_ep)
+ return -ENODEV;
+ f_rkusb->in_ep->driver_data = c->cdev;
+
+ f_rkusb->out_ep = usb_ep_autoconfig(gadget, &fs_ep_out);
+ if (!f_rkusb->out_ep)
+ return -ENODEV;
+ f_rkusb->out_ep->driver_data = c->cdev;
+
+ f->descriptors = rkusb_fs_function;
+
+ if (gadget_is_dualspeed(gadget)) {
+ hs_ep_in.bEndpointAddress = fs_ep_in.bEndpointAddress;
+ hs_ep_out.bEndpointAddress = fs_ep_out.bEndpointAddress;
+ f->hs_descriptors = rkusb_hs_function;
+ }
+
+ s = env_get("serial#");
+ if (s)
+ g_dnl_set_serialnumber((char *)s);
+
+ return 0;
+}
+
+static void rockusb_unbind(struct usb_configuration *c, struct usb_function *f)
+{
+ /* clear the configuration*/
+ memset(rockusb_func, 0, sizeof(*rockusb_func));
+}
+
+static void rockusb_disable(struct usb_function *f)
+{
+ struct f_rockusb *f_rkusb = func_to_rockusb(f);
+
+ usb_ep_disable(f_rkusb->out_ep);
+ usb_ep_disable(f_rkusb->in_ep);
+
+ if (f_rkusb->out_req) {
+ free(f_rkusb->out_req->buf);
+ usb_ep_free_request(f_rkusb->out_ep, f_rkusb->out_req);
+ f_rkusb->out_req = NULL;
+ }
+ if (f_rkusb->in_req) {
+ free(f_rkusb->in_req->buf);
+ usb_ep_free_request(f_rkusb->in_ep, f_rkusb->in_req);
+ f_rkusb->in_req = NULL;
+ }
+ if (f_rkusb->buf_head) {
+ free(f_rkusb->buf_head);
+ f_rkusb->buf_head = NULL;
+ f_rkusb->buf = NULL;
+ }
+}
+
+static struct usb_request *rockusb_start_ep(struct usb_ep *ep)
+{
+ struct usb_request *req;
+
+ req = usb_ep_alloc_request(ep, 0);
+ if (!req)
+ return NULL;
+
+ req->length = EP_BUFFER_SIZE;
+ req->buf = memalign(CONFIG_SYS_CACHELINE_SIZE, EP_BUFFER_SIZE);
+ if (!req->buf) {
+ usb_ep_free_request(ep, req);
+ return NULL;
+ }
+ memset(req->buf, 0, req->length);
+
+ return req;
+}
+
+static int rockusb_set_alt(struct usb_function *f, unsigned int interface,
+ unsigned int alt)
+{
+ int ret;
+ struct usb_composite_dev *cdev = f->config->cdev;
+ struct usb_gadget *gadget = cdev->gadget;
+ struct f_rockusb *f_rkusb = func_to_rockusb(f);
+ const struct usb_endpoint_descriptor *d;
+
+ debug("%s: func: %s intf: %d alt: %d\n",
+ __func__, f->name, interface, alt);
+
+ d = rkusb_ep_desc(gadget, &fs_ep_out, &hs_ep_out);
+ ret = usb_ep_enable(f_rkusb->out_ep, d);
+ if (ret) {
+ printf("failed to enable out ep\n");
+ return ret;
+ }
+
+ f_rkusb->out_req = rockusb_start_ep(f_rkusb->out_ep);
+ if (!f_rkusb->out_req) {
+ printf("failed to alloc out req\n");
+ ret = -EINVAL;
+ goto err;
+ }
+ f_rkusb->out_req->complete = rx_handler_command;
+
+ d = rkusb_ep_desc(gadget, &fs_ep_in, &hs_ep_in);
+ ret = usb_ep_enable(f_rkusb->in_ep, d);
+ if (ret) {
+ printf("failed to enable in ep\n");
+ goto err;
+ }
+
+ f_rkusb->in_req = rockusb_start_ep(f_rkusb->in_ep);
+ if (!f_rkusb->in_req) {
+ printf("failed alloc req in\n");
+ ret = -EINVAL;
+ goto err;
+ }
+ f_rkusb->in_req->complete = rockusb_complete;
+
+ ret = usb_ep_queue(f_rkusb->out_ep, f_rkusb->out_req, 0);
+ if (ret)
+ goto err;
+
+ return 0;
+err:
+ rockusb_disable(f);
+ return ret;
+}
+
+static int rockusb_add(struct usb_configuration *c)
+{
+ struct f_rockusb *f_rkusb = get_rkusb();
+ int status;
+
+ debug("%s: cdev: 0x%p\n", __func__, c->cdev);
+
+ f_rkusb->usb_function.name = "f_rockusb";
+ f_rkusb->usb_function.bind = rockusb_bind;
+ f_rkusb->usb_function.unbind = rockusb_unbind;
+ f_rkusb->usb_function.set_alt = rockusb_set_alt;
+ f_rkusb->usb_function.disable = rockusb_disable;
+ f_rkusb->usb_function.strings = rkusb_strings;
+
+ status = usb_add_function(c, &f_rkusb->usb_function);
+ if (status) {
+ free(f_rkusb);
+ rockusb_func = f_rkusb;
+ }
+ return status;
+}
+
+void rockusb_dev_init(char *dev_type, int dev_index)
+{
+ struct f_rockusb *f_rkusb = get_rkusb();
+
+ f_rkusb->dev_type = dev_type;
+ f_rkusb->dev_index = dev_index;
+}
+
+DECLARE_GADGET_BIND_CALLBACK(usb_dnl_rockusb, rockusb_add);
+
+static int rockusb_tx_write(const char *buffer, unsigned int buffer_size)
+{
+ struct usb_request *in_req = rockusb_func->in_req;
+ int ret;
+
+ memcpy(in_req->buf, buffer, buffer_size);
+ in_req->length = buffer_size;
+ usb_ep_dequeue(rockusb_func->in_ep, in_req);
+ ret = usb_ep_queue(rockusb_func->in_ep, in_req, 0);
+ if (ret)
+ printf("Error %d on queue\n", ret);
+ return 0;
+}
+
+static int rockusb_tx_write_str(const char *buffer)
+{
+ return rockusb_tx_write(buffer, strlen(buffer));
+}
+
+#ifdef DEBUG
+static void printcbw(char *buf)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(struct fsg_bulk_cb_wrap, cbw,
+ sizeof(struct fsg_bulk_cb_wrap));
+
+ memcpy((char *)cbw, buf, USB_BULK_CB_WRAP_LEN);
+
+ debug("cbw: signature:%x\n", cbw->signature);
+ debug("cbw: tag=%x\n", cbw->tag);
+ debug("cbw: data_transfer_length=%d\n", cbw->data_transfer_length);
+ debug("cbw: flags=%x\n", cbw->flags);
+ debug("cbw: lun=%d\n", cbw->lun);
+ debug("cbw: length=%d\n", cbw->length);
+ debug("cbw: ucOperCode=%x\n", cbw->CDB[0]);
+ debug("cbw: ucReserved=%x\n", cbw->CDB[1]);
+ debug("cbw: dwAddress:%x %x %x %x\n", cbw->CDB[5], cbw->CDB[4],
+ cbw->CDB[3], cbw->CDB[2]);
+ debug("cbw: ucReserved2=%x\n", cbw->CDB[6]);
+ debug("cbw: uslength:%x %x\n", cbw->CDB[8], cbw->CDB[7]);
+}
+
+static void printcsw(char *buf)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(struct bulk_cs_wrap, csw,
+ sizeof(struct bulk_cs_wrap));
+ memcpy((char *)csw, buf, USB_BULK_CS_WRAP_LEN);
+ debug("csw: signature:%x\n", csw->signature);
+ debug("csw: tag:%x\n", csw->tag);
+ debug("csw: residue:%x\n", csw->residue);
+ debug("csw: status:%x\n", csw->status);
+}
+#endif
+
+static int rockusb_tx_write_csw(u32 tag, int residue, u8 status, int size)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(struct bulk_cs_wrap, csw,
+ sizeof(struct bulk_cs_wrap));
+ csw->signature = cpu_to_le32(USB_BULK_CS_SIG);
+ csw->tag = tag;
+ csw->residue = cpu_to_be32(residue);
+ csw->status = status;
+#ifdef DEBUG
+ printcsw((char *)&csw);
+#endif
+ return rockusb_tx_write((char *)csw, size);
+}
+
+static unsigned int rx_bytes_expected(struct usb_ep *ep)
+{
+ struct f_rockusb *f_rkusb = get_rkusb();
+ int rx_remain = f_rkusb->dl_size - f_rkusb->dl_bytes;
+ unsigned int rem;
+ unsigned int maxpacket = ep->maxpacket;
+
+ if (rx_remain <= 0)
+ return 0;
+ else if (rx_remain > EP_BUFFER_SIZE)
+ return EP_BUFFER_SIZE;
+
+ rem = rx_remain % maxpacket;
+ if (rem > 0)
+ rx_remain = rx_remain + (maxpacket - rem);
+
+ return rx_remain;
+}
+
+/* usb_request complete call back to handle down load image */
+static void rx_handler_dl_image(struct usb_ep *ep, struct usb_request *req)
+{
+ struct f_rockusb *f_rkusb = get_rkusb();
+ unsigned int transfer_size = 0;
+ const unsigned char *buffer = req->buf;
+ unsigned int buffer_size = req->actual;
+
+ transfer_size = f_rkusb->dl_size - f_rkusb->dl_bytes;
+ if (!f_rkusb->desc) {
+ char *type = f_rkusb->dev_type;
+ int index = f_rkusb->dev_index;
+
+ f_rkusb->desc = blk_get_dev(type, index);
+ if (!f_rkusb->desc ||
+ f_rkusb->desc->type == DEV_TYPE_UNKNOWN) {
+ puts("invalid mmc device\n");
+ rockusb_tx_write_csw(f_rkusb->tag, 0, CSW_FAIL,
+ USB_BULK_CS_WRAP_LEN);
+ return;
+ }
+ }
+
+ if (req->status != 0) {
+ printf("Bad status: %d\n", req->status);
+ rockusb_tx_write_csw(f_rkusb->tag, 0, CSW_FAIL,
+ USB_BULK_CS_WRAP_LEN);
+ return;
+ }
+
+ if (buffer_size < transfer_size)
+ transfer_size = buffer_size;
+
+ memcpy((void *)f_rkusb->buf, buffer, transfer_size);
+ f_rkusb->dl_bytes += transfer_size;
+ int blks = 0, blkcnt = transfer_size / 512;
+
+ debug("dl %x bytes, %x blks, write lba %x, dl_size:%x, dl_bytes:%x, ",
+ transfer_size, blkcnt, f_rkusb->lba, f_rkusb->dl_size,
+ f_rkusb->dl_bytes);
+ blks = blk_dwrite(f_rkusb->desc, f_rkusb->lba, blkcnt, f_rkusb->buf);
+ if (blks != blkcnt) {
+ printf("failed writing to device %s: %d\n", f_rkusb->dev_type,
+ f_rkusb->dev_index);
+ rockusb_tx_write_csw(f_rkusb->tag, 0, CSW_FAIL,
+ USB_BULK_CS_WRAP_LEN);
+ return;
+ }
+ f_rkusb->lba += blkcnt;
+
+ /* Check if transfer is done */
+ if (f_rkusb->dl_bytes >= f_rkusb->dl_size) {
+ req->complete = rx_handler_command;
+ req->length = EP_BUFFER_SIZE;
+ f_rkusb->buf = f_rkusb->buf_head;
+ printf("transfer 0x%x bytes done\n", f_rkusb->dl_size);
+ f_rkusb->dl_size = 0;
+ rockusb_tx_write_csw(f_rkusb->tag, 0, CSW_GOOD,
+ USB_BULK_CS_WRAP_LEN);
+ } else {
+ req->length = rx_bytes_expected(ep);
+ if (f_rkusb->buf == f_rkusb->buf_head)
+ f_rkusb->buf = f_rkusb->buf_head + EP_BUFFER_SIZE;
+ else
+ f_rkusb->buf = f_rkusb->buf_head;
+
+ debug("remain %x bytes, %x sectors\n", req->length,
+ req->length / 512);
+ }
+
+ req->actual = 0;
+ usb_ep_queue(ep, req, 0);
+}
+
+static void cb_test_unit_ready(struct usb_ep *ep, struct usb_request *req)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(struct fsg_bulk_cb_wrap, cbw,
+ sizeof(struct fsg_bulk_cb_wrap));
+
+ memcpy((char *)cbw, req->buf, USB_BULK_CB_WRAP_LEN);
+
+ rockusb_tx_write_csw(cbw->tag, cbw->data_transfer_length,
+ CSW_GOOD, USB_BULK_CS_WRAP_LEN);
+}
+
+static void cb_read_storage_id(struct usb_ep *ep, struct usb_request *req)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(struct fsg_bulk_cb_wrap, cbw,
+ sizeof(struct fsg_bulk_cb_wrap));
+ char emmc_id[] = "EMMC ";
+
+ printf("read storage id\n");
+ memcpy((char *)cbw, req->buf, USB_BULK_CB_WRAP_LEN);
+ rockusb_tx_write_str(emmc_id);
+ rockusb_tx_write_csw(cbw->tag, cbw->data_transfer_length, CSW_GOOD,
+ USB_BULK_CS_WRAP_LEN);
+}
+
+static void cb_write_lba(struct usb_ep *ep, struct usb_request *req)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(struct fsg_bulk_cb_wrap, cbw,
+ sizeof(struct fsg_bulk_cb_wrap));
+ struct f_rockusb *f_rkusb = get_rkusb();
+ int sector_count;
+
+ memcpy((char *)cbw, req->buf, USB_BULK_CB_WRAP_LEN);
+ sector_count = (int)get_unaligned_be16(&cbw->CDB[7]);
+ f_rkusb->lba = get_unaligned_be32(&cbw->CDB[2]);
+ f_rkusb->dl_size = sector_count * 512;
+ f_rkusb->dl_bytes = 0;
+ f_rkusb->tag = cbw->tag;
+ debug("require write %x bytes, %x sectors to lba %x\n",
+ f_rkusb->dl_size, sector_count, f_rkusb->lba);
+
+ if (f_rkusb->dl_size == 0) {
+ rockusb_tx_write_csw(cbw->tag, cbw->data_transfer_length,
+ CSW_FAIL, USB_BULK_CS_WRAP_LEN);
+ } else {
+ req->complete = rx_handler_dl_image;
+ req->length = rx_bytes_expected(ep);
+ }
+}
+
+void __weak rkusb_set_reboot_flag(int flag)
+{
+ struct f_rockusb *f_rkusb = get_rkusb();
+
+ printf("rockkusb set reboot flag: %d\n", f_rkusb->reboot_flag);
+}
+
+static void compl_do_reset(struct usb_ep *ep, struct usb_request *req)
+{
+ struct f_rockusb *f_rkusb = get_rkusb();
+
+ rkusb_set_reboot_flag(f_rkusb->reboot_flag);
+ do_reset(NULL, 0, 0, NULL);
+}
+
+static void cb_reboot(struct usb_ep *ep, struct usb_request *req)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(struct fsg_bulk_cb_wrap, cbw,
+ sizeof(struct fsg_bulk_cb_wrap));
+ struct f_rockusb *f_rkusb = get_rkusb();
+
+ f_rkusb->reboot_flag = 0;
+ memcpy((char *)cbw, req->buf, USB_BULK_CB_WRAP_LEN);
+ f_rkusb->reboot_flag = cbw->CDB[1];
+ rockusb_func->in_req->complete = compl_do_reset;
+ rockusb_tx_write_csw(cbw->tag, cbw->data_transfer_length, CSW_GOOD,
+ USB_BULK_CS_WRAP_LEN);
+}
+
+static void cb_not_support(struct usb_ep *ep, struct usb_request *req)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(struct fsg_bulk_cb_wrap, cbw,
+ sizeof(struct fsg_bulk_cb_wrap));
+
+ memcpy((char *)cbw, req->buf, USB_BULK_CB_WRAP_LEN);
+ printf("Rockusb command %x not support yet\n", cbw->CDB[0]);
+ rockusb_tx_write_csw(cbw->tag, 0, CSW_FAIL, USB_BULK_CS_WRAP_LEN);
+}
+
+static const struct cmd_dispatch_info cmd_dispatch_info[] = {
+ {
+ .cmd = K_FW_TEST_UNIT_READY,
+ .cb = cb_test_unit_ready,
+ },
+ {
+ .cmd = K_FW_READ_FLASH_ID,
+ .cb = cb_read_storage_id,
+ },
+ {
+ .cmd = K_FW_SET_DEVICE_ID,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_TEST_BAD_BLOCK,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_READ_10,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_WRITE_10,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_ERASE_10,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_WRITE_SPARE,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_READ_SPARE,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_ERASE_10_FORCE,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_GET_VERSION,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_LBA_READ_10,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_LBA_WRITE_10,
+ .cb = cb_write_lba,
+ },
+ {
+ .cmd = K_FW_ERASE_SYS_DISK,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_SDRAM_READ_10,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_SDRAM_WRITE_10,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_SDRAM_EXECUTE,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_READ_FLASH_INFO,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_GET_CHIP_VER,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_LOW_FORMAT,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_SET_RESET_FLAG,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_SPI_READ_10,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_SPI_WRITE_10,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_SESSION,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_RESET,
+ .cb = cb_reboot,
+ },
+};
+
+static void rx_handler_command(struct usb_ep *ep, struct usb_request *req)
+{
+ void (*func_cb)(struct usb_ep *ep, struct usb_request *req) = NULL;
+
+ ALLOC_CACHE_ALIGN_BUFFER(struct fsg_bulk_cb_wrap, cbw,
+ sizeof(struct fsg_bulk_cb_wrap));
+ char *cmdbuf = req->buf;
+ int i;
+
+ if (req->status || req->length == 0)
+ return;
+
+ memcpy((char *)cbw, req->buf, USB_BULK_CB_WRAP_LEN);
+#ifdef DEBUG
+ printcbw(req->buf);
+#endif
+
+ for (i = 0; i < ARRAY_SIZE(cmd_dispatch_info); i++) {
+ if (cmd_dispatch_info[i].cmd == cbw->CDB[0]) {
+ func_cb = cmd_dispatch_info[i].cb;
+ break;
+ }
+ }
+
+ if (!func_cb) {
+ printf("unknown command: %s\n", (char *)req->buf);
+ rockusb_tx_write_str("FAILunknown command");
+ } else {
+ if (req->actual < req->length) {
+ u8 *buf = (u8 *)req->buf;
+
+ buf[req->actual] = 0;
+ func_cb(ep, req);
+ } else {
+ puts("buffer overflow\n");
+ rockusb_tx_write_str("FAILbuffer overflow");
+ }
+ }
+
+ *cmdbuf = '\0';
+ req->actual = 0;
+ usb_ep_queue(ep, req, 0);
+}
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index c79f866cf1..90b2f78ec7 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -186,6 +186,12 @@ config USB_EHCI_GENERIC
---help---
Enables support for generic EHCI controller.
+config USB_EHCI_FSL
+ bool "Support for FSL on-chip EHCI USB controller"
+ default n
+ select CONFIG_EHCI_HCD_INIT_AFTER_RESET
+ ---help---
+ Enables support for the on-chip EHCI controller on FSL chips.
endif # USB_EHCI_HCD
config USB_OHCI_HCD
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 62c431b99f..17d1fae382 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -106,14 +106,14 @@ static int ehci_fsl_probe(struct udevice *dev)
ehci = (struct usb_ehci *)priv->hcd_base;
hccr = (struct ehci_hccr *)(&ehci->caplength);
hcor = (struct ehci_hcor *)
- ((u32)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ ((void *)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
if (ehci_fsl_init(priv, ehci, hccr, hcor) < 0)
return -ENXIO;
- debug("ehci-fsl: init hccr %x and hcor %x hc_length %d\n",
- (u32)hccr, (u32)hcor,
- (u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ debug("ehci-fsl: init hccr %p and hcor %p hc_length %d\n",
+ (void *)hccr, (void *)hcor,
+ HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
return ehci_register(dev, hccr, hcor, &fsl_ehci_ops, 0, USB_INIT_HOST);
}
diff --git a/drivers/usb/musb-new/Kconfig b/drivers/usb/musb-new/Kconfig
index caba42c26f..ea5bae260e 100644
--- a/drivers/usb/musb-new/Kconfig
+++ b/drivers/usb/musb-new/Kconfig
@@ -23,6 +23,16 @@ config USB_MUSB_TI
speed USB controller based on the Mentor Graphics
silicon IP.
+config USB_MUSB_OMAP2PLUS
+ tristate "OMAP2430 and onwards"
+ depends on ARCH_OMAP2PLUS
+
+config USB_MUSB_AM35X
+ bool "AM35x"
+
+config USB_MUSB_DSPS
+ bool "TI DSPS platforms"
+
if USB_MUSB_HOST || USB_MUSB_GADGET
config USB_MUSB_PIC32
@@ -41,3 +51,10 @@ config USB_MUSB_SUNXI
used on almost all sunxi boards.
endif
+
+config USB_MUSB_PIO_ONLY
+ bool "Disable DMA (always use PIO)"
+ default y if USB_MUSB_AM35X || USB_MUSB_PIC32 || USB_MUSB_OMAP2PLUS || USB_MUSB_DSPS || USB_MUSB_SUNXI
+ help
+ All data is copied between memory and FIFO by the CPU.
+ DMA controllers are ignored.
diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c
index 7ee44ea919..aedc24b937 100644
--- a/drivers/usb/musb-new/sunxi.c
+++ b/drivers/usb/musb-new/sunxi.c
@@ -312,13 +312,16 @@ static int musb_usb_probe(struct udevice *dev)
{
struct musb_host_data *host = dev_get_priv(dev);
struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
+ void *base = dev_read_addr_ptr(dev);
int ret;
+ if (!base)
+ return -EINVAL;
+
priv->desc_before_addr = true;
#ifdef CONFIG_USB_MUSB_HOST
- host->host = musb_init_controller(&musb_plat, NULL,
- (void *)SUNXI_USB0_BASE);
+ host->host = musb_init_controller(&musb_plat, NULL, base);
if (!host->host)
return -EIO;
@@ -326,7 +329,7 @@ static int musb_usb_probe(struct udevice *dev)
if (!ret)
printf("Allwinner mUSB OTG (Host)\n");
#else
- ret = musb_register(&musb_plat, NULL, (void *)SUNXI_USB0_BASE);
+ ret = musb_register(&musb_plat, NULL, base);
if (!ret)
printf("Allwinner mUSB OTG (Peripheral)\n");
#endif
diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig
new file mode 100644
index 0000000000..4e2be3789c
--- /dev/null
+++ b/drivers/usb/musb/Kconfig
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2017
+# Adam Ford, Logic PD, aford173@gmail.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+comment "Legacy MUSB Support"
+
+config USB_MUSB_HCD
+ bool "Legacy MUSB Host Controller"
+
+config USB_MUSB_UDC
+ bool "Legacy USB Device Controller"
+
+config USB_DAVINCI
+ bool "Legacy MUSB DaVinci"
+
+config USB_OMAP3
+ bool "Legacy MUSB OMAP3 / OMAP4"
+ depends on ARCH_OMAP2PLUS
+
+config USB_DA8XX
+ bool "Legacy MUSB DA8xx/OMAP-L1x"
+ depends on ARCH_DAVINCI
+
+config USB_AM35X
+ bool"Legacy MUSB AM35x"
+ depends on ARCH_OMAP2PLUS && !USB_OMAP3
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
new file mode 100644
index 0000000000..bcc67a0d70
--- /dev/null
+++ b/drivers/usb/phy/Kconfig
@@ -0,0 +1,17 @@
+#
+# (C) Copyright 2017
+# Adam Ford, Logic PD, aford173@gmail.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+comment "USB Phy"
+
+config TWL4030_USB
+ bool "TWL4030 PHY"
+
+config OMAP_USB_PHY
+ bool "OMAP PHY"
+
+config ROCKCHIP_USB2_PHY
+ bool "Rockchip USB2 PHY"
diff --git a/drivers/video/am335x-fb.c b/drivers/video/am335x-fb.c
index a8b3e747a0..a7892f799e 100644
--- a/drivers/video/am335x-fb.c
+++ b/drivers/video/am335x-fb.c
@@ -1,6 +1,6 @@
/*
- * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
- * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ * Copyright (C) 2013-2018 Hannes Schmelzer <oe5hpm@oevsv.at>
+ * B&R Industrial Automation GmbH - http://www.br-automation.com
*
* minimal framebuffer driver for TI's AM335x SoC to be compatible with
* Wolfgang Denk's LCD-Framework (CONFIG_LCD, common/lcd.c)
@@ -12,7 +12,11 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <asm/io.h>
#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
#include <lcd.h>
#include "am335x-fb.h"
@@ -20,6 +24,7 @@
#error "hw-base address of LCD-Controller (LCD_CNTL_BASE) not defined!"
#endif
+#define LCDC_FMAX 200000000
/* LCD Control Register */
#define LCD_CLK_DIVISOR(x) ((x) << 8)
@@ -96,6 +101,7 @@ struct am335x_lcdhw {
};
static struct am335x_lcdhw *lcdhw = (void *)LCD_CNTL_BASE;
+
DECLARE_GLOBAL_DATA_PTR;
int lcd_get_size(int *line_length)
@@ -108,11 +114,16 @@ int am335xfb_init(struct am335x_lcdpanel *panel)
{
u32 raster_ctrl = 0;
- if (0 == gd->fb_base) {
+ struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
+ struct dpll_params dpll_disp = { 1, 0, 1, -1, -1, -1, -1 };
+ unsigned int m, n, d, best_d = 2;
+ int err = 0, err_r = 0;
+
+ if (gd->fb_base == 0) {
printf("ERROR: no valid fb_base stored in GLOBAL_DATA_PTR!\n");
return -1;
}
- if (0 == panel) {
+ if (panel == NULL) {
printf("ERROR: missing ptr to am335x_lcdpanel!\n");
return -1;
}
@@ -132,14 +143,51 @@ int am335xfb_init(struct am335x_lcdpanel *panel)
return -1;
}
+ /* check given clock-frequency */
+ if (panel->pxl_clk > (LCDC_FMAX / 2)) {
+ pr_err("am335x-fb: requested pxl-clk: %d not supported!\n",
+ panel->pxl_clk);
+ return -1;
+ }
+
debug("setting up LCD-Controller for %dx%dx%d (hfp=%d,hbp=%d,hsw=%d / ",
panel->hactive, panel->vactive, panel->bpp,
panel->hfp, panel->hbp, panel->hsw);
- debug("vfp=%d,vbp=%d,vsw=%d / clk-div=%d)\n",
- panel->vfp, panel->vfp, panel->vsw, panel->pxl_clk_div);
+ debug("vfp=%d,vbp=%d,vsw=%d / clk=%d)\n",
+ panel->vfp, panel->vfp, panel->vsw, panel->pxl_clk);
debug("using frambuffer at 0x%08x with size %d.\n",
(unsigned int)gd->fb_base, FBSIZE(panel));
+ /* setup display pll for requested clock frequency */
+ err = panel->pxl_clk;
+ err_r = err;
+
+ for (d = 2; d < 255; d++) {
+ for (m = 2; m < 2047; m++) {
+ if ((V_OSCK * m) < (panel->pxl_clk * d))
+ continue;
+ n = (V_OSCK * m) / (panel->pxl_clk * d);
+ if (n > 127)
+ break;
+ if (((V_OSCK * m) / n) > LCDC_FMAX)
+ break;
+
+ err = abs((V_OSCK * m) / n / d - panel->pxl_clk);
+ if (err < err_r) {
+ err_r = err;
+ dpll_disp.m = m;
+ dpll_disp.n = n;
+ best_d = d;
+ }
+ }
+ }
+ debug("%s: PLL: best error %d Hz (M %d, N %d, DISP %d)\n",
+ __func__, err_r, dpll_disp.m, dpll_disp.n, best_d);
+ do_setup_dpll(&dpll_disp_regs, &dpll_disp);
+
+ /* clock source for LCDC from dispPLL M2 */
+ writel(0x0, &cmdpll->clklcdcpixelclk);
+
/* palette default entry */
memset((void *)gd->fb_base, 0, 0x20);
*(unsigned int *)gd->fb_base = 0x4000;
@@ -147,14 +195,14 @@ int am335xfb_init(struct am335x_lcdpanel *panel)
gd->fb_base += 0x20;
/* turn ON display through powercontrol function if accessible */
- if (0 != panel->panel_power_ctrl)
+ if (panel->panel_power_ctrl != NULL)
panel->panel_power_ctrl(1);
debug("am335x-fb: wait for stable power ...\n");
mdelay(panel->pup_delay);
lcdhw->clkc_enable = LCD_CORECLKEN | LCD_LIDDCLKEN | LCD_DMACLKEN;
lcdhw->raster_ctrl = 0;
- lcdhw->ctrl = LCD_CLK_DIVISOR(panel->pxl_clk_div) | LCD_RASTER_MODE;
+ lcdhw->ctrl = LCD_CLK_DIVISOR(best_d) | LCD_RASTER_MODE;
lcdhw->lcddma_fb0_base = gd->fb_base;
lcdhw->lcddma_fb0_ceiling = gd->fb_base + FBSIZE(panel);
lcdhw->lcddma_fb1_base = gd->fb_base;
diff --git a/drivers/video/am335x-fb.h b/drivers/video/am335x-fb.h
index 3f4b567ce2..f99b341334 100644
--- a/drivers/video/am335x-fb.h
+++ b/drivers/video/am335x-fb.h
@@ -1,6 +1,6 @@
/*
- * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> -
- * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ * Copyright (C) 2013-2018 Hannes Schmelzer <oe5hpm@oevsv.at> -
+ * B&R Industrial Automation GmbH - http://www.br-automation.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -53,7 +53,7 @@ struct am335x_lcdpanel {
unsigned int vfp; /* Vertical front porch */
unsigned int vbp; /* Vertical back porch */
unsigned int vsw; /* Vertical Sync Pulse Width */
- unsigned int pxl_clk_div; /* Pixel clock divider*/
+ unsigned int pxl_clk; /* Pixel clock */
unsigned int pol; /* polarity of sync, clock signals */
unsigned int pup_delay; /*
* time in ms after power on to