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-rw-r--r--drivers/block/Makefile2
-rw-r--r--drivers/clk/mediatek/Makefile1
-rw-r--r--drivers/clk/mediatek/clk-mt8518.c1558
-rw-r--r--drivers/core/regmap.c16
-rw-r--r--drivers/mmc/davinci_mmc.c73
-rw-r--r--drivers/mmc/mtk-sd.c209
-rw-r--r--drivers/mtd/mtdcore.c2
-rw-r--r--drivers/net/phy/Kconfig22
-rw-r--r--drivers/net/ti/cpsw.c3
-rw-r--r--drivers/pci/Makefile4
-rw-r--r--drivers/pinctrl/mediatek/Kconfig4
-rw-r--r--drivers/pinctrl/mediatek/Makefile1
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mt8518.c411
-rw-r--r--drivers/serial/Kconfig2
14 files changed, 2235 insertions, 73 deletions
diff --git a/drivers/block/Makefile b/drivers/block/Makefile
index 3feb0aa997..94ab5c6f90 100644
--- a/drivers/block/Makefile
+++ b/drivers/block/Makefile
@@ -6,7 +6,7 @@
obj-$(CONFIG_$(SPL_)BLK) += blk-uclass.o
ifndef CONFIG_$(SPL_)BLK
-obj-y += blk_legacy.o
+obj-$(CONFIG_HAVE_BLOCK_DEVICE) += blk_legacy.o
endif
ifndef CONFIG_SPL_BUILD
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index a47a5bdbc2..e92bcd4efe 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_ARCH_MEDIATEK) += clk-mtk.o
obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o
obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
+obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o
diff --git a/drivers/clk/mediatek/clk-mt8518.c b/drivers/clk/mediatek/clk-mt8518.c
new file mode 100644
index 0000000000..76f7b3b361
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8518.c
@@ -0,0 +1,1558 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT8518 SoC
+ *
+ * Copyright (C) 2019 BayLibre, SAS
+ * Author: Chen Zhong <chen.zhong@mediatek.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <dt-bindings/clock/mt8518-clk.h>
+
+#include "clk-mtk.h"
+
+#define MT8518_PLL_FMAX (3000UL * MHZ)
+#define MT8518_CON0_RST_BAR BIT(27)
+
+/* apmixedsys */
+#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
+ _pd_shift, _pcw_reg, _pcw_shift) { \
+ .id = _id, \
+ .reg = _reg, \
+ .pwr_reg = _pwr_reg, \
+ .en_mask = _en_mask, \
+ .rst_bar_mask = MT8518_CON0_RST_BAR, \
+ .fmax = MT8518_PLL_FMAX, \
+ .flags = _flags, \
+ .pcwbits = _pcwbits, \
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .pcw_reg = _pcw_reg, \
+ .pcw_shift = _pcw_shift, \
+ }
+
+static const struct mtk_pll_data apmixed_plls[] = {
+ PLL(CLK_APMIXED_ARMPLL, 0x0100, 0x0110, 0x00000001,
+ 0, 21, 0x0104, 24, 0x0104, 0),
+ PLL(CLK_APMIXED_MAINPLL, 0x0120, 0x0130, 0x00000001,
+ HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0),
+ PLL(CLK_APMIXED_UNIVPLL, 0x0140, 0x0150, 0x30000001,
+ HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0),
+ PLL(CLK_APMIXED_MMPLL, 0x0160, 0x0170, 0x00000001,
+ 0, 21, 0x0164, 24, 0x0164, 0),
+ PLL(CLK_APMIXED_APLL1, 0x0180, 0x0190, 0x00000001,
+ 0, 31, 0x0180, 1, 0x0184, 0),
+ PLL(CLK_APMIXED_APLL2, 0x01A0, 0x01B0, 0x00000001,
+ 0, 31, 0x01A0, 1, 0x01A4, 0),
+ PLL(CLK_APMIXED_TVDPLL, 0x01C0, 0x01D0, 0x00000001,
+ 0, 21, 0x01C4, 24, 0x01C4, 0),
+};
+
+/* topckgen */
+#define FACTOR0(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
+
+#define FACTOR1(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
+
+#define FACTOR2(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, 0)
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+ FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 26000000),
+ FIXED_CLK(CLK_TOP_FQ_TRNG_OUT0, CLK_TOP_CLK_NULL, 500000000),
+ FIXED_CLK(CLK_TOP_FQ_TRNG_OUT1, CLK_TOP_CLK_NULL, 500000000),
+ FIXED_CLK(CLK_TOP_CLK32K, CLK_XTAL, 32000),
+};
+
+static const struct mtk_fixed_factor top_fixed_divs[] = {
+ FACTOR2(CLK_TOP_DMPLL, CLK_XTAL, 1, 1),
+ FACTOR0(CLK_TOP_MAINPLL_D4, CLK_APMIXED_MAINPLL, 1, 4),
+ FACTOR0(CLK_TOP_MAINPLL_D8, CLK_APMIXED_MAINPLL, 1, 8),
+ FACTOR0(CLK_TOP_MAINPLL_D16, CLK_APMIXED_MAINPLL, 1, 16),
+ FACTOR0(CLK_TOP_MAINPLL_D11, CLK_APMIXED_MAINPLL, 1, 11),
+ FACTOR0(CLK_TOP_MAINPLL_D22, CLK_APMIXED_MAINPLL, 1, 22),
+ FACTOR0(CLK_TOP_MAINPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
+ FACTOR0(CLK_TOP_MAINPLL_D6, CLK_APMIXED_MAINPLL, 1, 6),
+ FACTOR0(CLK_TOP_MAINPLL_D12, CLK_APMIXED_MAINPLL, 1, 12),
+ FACTOR0(CLK_TOP_MAINPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
+ FACTOR0(CLK_TOP_MAINPLL_D10, CLK_APMIXED_MAINPLL, 1, 10),
+ FACTOR0(CLK_TOP_MAINPLL_D20, CLK_APMIXED_MAINPLL, 1, 20),
+ FACTOR0(CLK_TOP_MAINPLL_D40, CLK_APMIXED_MAINPLL, 1, 40),
+ FACTOR0(CLK_TOP_MAINPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
+ FACTOR0(CLK_TOP_MAINPLL_D14, CLK_APMIXED_MAINPLL, 1, 14),
+ FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2),
+ FACTOR0(CLK_TOP_UNIVPLL_D4, CLK_APMIXED_UNIVPLL, 1, 4),
+ FACTOR0(CLK_TOP_UNIVPLL_D8, CLK_APMIXED_UNIVPLL, 1, 8),
+ FACTOR0(CLK_TOP_UNIVPLL_D16, CLK_APMIXED_UNIVPLL, 1, 16),
+ FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3),
+ FACTOR0(CLK_TOP_UNIVPLL_D6, CLK_APMIXED_UNIVPLL, 1, 6),
+ FACTOR0(CLK_TOP_UNIVPLL_D12, CLK_APMIXED_UNIVPLL, 1, 12),
+ FACTOR0(CLK_TOP_UNIVPLL_D24, CLK_APMIXED_UNIVPLL, 1, 24),
+ FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5),
+ FACTOR0(CLK_TOP_UNIVPLL_D20, CLK_APMIXED_UNIVPLL, 1, 20),
+ FACTOR0(CLK_TOP_UNIVPLL_D10, CLK_APMIXED_UNIVPLL, 1, 10),
+ FACTOR0(CLK_TOP_MMPLL_D2, CLK_APMIXED_MMPLL, 1, 2),
+ FACTOR0(CLK_TOP_USB20_48M, CLK_APMIXED_UNIVPLL, 1, 26),
+ FACTOR0(CLK_TOP_APLL1, CLK_APMIXED_APLL1, 1, 1),
+ FACTOR1(CLK_TOP_APLL1_D4, CLK_TOP_APLL1, 1, 4),
+ FACTOR0(CLK_TOP_APLL2, CLK_APMIXED_APLL2, 1, 1),
+ FACTOR1(CLK_TOP_APLL2_D2, CLK_TOP_APLL2, 1, 2),
+ FACTOR1(CLK_TOP_APLL2_D3, CLK_TOP_APLL2, 1, 3),
+ FACTOR1(CLK_TOP_APLL2_D4, CLK_TOP_APLL2, 1, 4),
+ FACTOR1(CLK_TOP_APLL2_D8, CLK_TOP_APLL2, 1, 8),
+ FACTOR2(CLK_TOP_CLK26M, CLK_XTAL, 1, 1),
+ FACTOR2(CLK_TOP_CLK26M_D2, CLK_XTAL, 1, 2),
+ FACTOR2(CLK_TOP_CLK26M_D4, CLK_XTAL, 1, 4),
+ FACTOR2(CLK_TOP_CLK26M_D8, CLK_XTAL, 1, 8),
+ FACTOR2(CLK_TOP_CLK26M_D793, CLK_XTAL, 1, 793),
+ FACTOR0(CLK_TOP_TVDPLL, CLK_APMIXED_TVDPLL, 1, 1),
+ FACTOR1(CLK_TOP_TVDPLL_D2, CLK_TOP_TVDPLL, 1, 2),
+ FACTOR1(CLK_TOP_TVDPLL_D4, CLK_TOP_TVDPLL, 1, 4),
+ FACTOR1(CLK_TOP_TVDPLL_D8, CLK_TOP_TVDPLL, 1, 8),
+ FACTOR1(CLK_TOP_TVDPLL_D16, CLK_TOP_TVDPLL, 1, 16),
+ FACTOR1(CLK_TOP_USB20_CLK480M, CLK_TOP_CLK_NULL, 1, 1),
+ FACTOR1(CLK_TOP_RG_APLL1_D2, CLK_TOP_APLL1_SRC_SEL, 1, 2),
+ FACTOR1(CLK_TOP_RG_APLL1_D4, CLK_TOP_APLL1_SRC_SEL, 1, 4),
+ FACTOR1(CLK_TOP_RG_APLL1_D8, CLK_TOP_APLL1_SRC_SEL, 1, 8),
+ FACTOR1(CLK_TOP_RG_APLL1_D16, CLK_TOP_APLL1_SRC_SEL, 1, 16),
+ FACTOR1(CLK_TOP_RG_APLL1_D3, CLK_TOP_APLL1_SRC_SEL, 1, 3),
+ FACTOR1(CLK_TOP_RG_APLL2_D2, CLK_TOP_APLL2_SRC_SEL, 1, 2),
+ FACTOR1(CLK_TOP_RG_APLL2_D4, CLK_TOP_APLL2_SRC_SEL, 1, 4),
+ FACTOR1(CLK_TOP_RG_APLL2_D8, CLK_TOP_APLL2_SRC_SEL, 1, 8),
+ FACTOR1(CLK_TOP_RG_APLL2_D16, CLK_TOP_APLL2_SRC_SEL, 1, 16),
+ FACTOR1(CLK_TOP_RG_APLL2_D3, CLK_TOP_APLL2_SRC_SEL, 1, 3),
+ FACTOR1(CLK_TOP_NFI1X_INFRA_BCLK, CLK_TOP_NFI2X_SEL, 1, 2),
+ FACTOR1(CLK_TOP_AHB_INFRA_D2, CLK_TOP_AXIBUS_SEL, 1, 2),
+};
+
+static const int uart0_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D24
+};
+
+static const int emi1x_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_DMPLL
+};
+
+static const int emi_ddrphy_parents[] = {
+ CLK_TOP_EMI1X_SEL,
+ CLK_TOP_EMI1X_SEL
+};
+
+static const int msdc1_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D6,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D8,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D8,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D16,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MMPLL_D2,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D12
+};
+
+static const int pwm_mm_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D12
+};
+
+static const int pmicspi_parents[] = {
+ CLK_TOP_UNIVPLL_D20,
+ CLK_TOP_USB20_48M,
+ CLK_TOP_UNIVPLL_D16,
+ CLK_TOP_CLK26M,
+ CLK_TOP_CLK26M_D2
+};
+
+static const int nfi2x_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D4,
+ CLK_TOP_MAINPLL_D5,
+ CLK_TOP_MAINPLL_D6,
+ CLK_TOP_MAINPLL_D7,
+ CLK_TOP_MAINPLL_D8,
+ CLK_TOP_MAINPLL_D10,
+ CLK_TOP_MAINPLL_D12
+};
+
+static const int ddrphycfg_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D16
+};
+
+static const int smi_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D4,
+ CLK_TOP_MAINPLL_D7,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D14
+};
+
+static const int usb_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D16,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D20
+};
+
+static const int spinor_parents[] = {
+ CLK_TOP_CLK26M_D2,
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D40,
+ CLK_TOP_UNIVPLL_D24,
+ CLK_TOP_UNIVPLL_D20,
+ CLK_TOP_MAINPLL_D20,
+ CLK_TOP_MAINPLL_D16,
+ CLK_TOP_UNIVPLL_D12
+};
+
+static const int eth_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D40,
+ CLK_TOP_UNIVPLL_D24,
+ CLK_TOP_UNIVPLL_D20,
+ CLK_TOP_MAINPLL_D20
+};
+
+static const int aud1_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL1_SRC_SEL
+};
+
+static const int aud2_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL2_SRC_SEL
+};
+
+static const int i2c_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_USB20_48M,
+ CLK_TOP_UNIVPLL_D12,
+ CLK_TOP_UNIVPLL_D10,
+ CLK_TOP_UNIVPLL_D8
+};
+
+static const int aud_i2s0_m_parents[] = {
+ CLK_TOP_AUD1,
+ CLK_TOP_AUD2
+};
+
+static const int aud_spdifin_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D2,
+ CLK_TOP_TVDPLL
+};
+
+static const int dbg_atclk_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D5,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D5
+};
+
+static const int png_sys_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D8,
+ CLK_TOP_MAINPLL_D7,
+ CLK_TOP_MAINPLL_D6,
+ CLK_TOP_MAINPLL_D5,
+ CLK_TOP_UNIVPLL_D3
+};
+
+static const int sej_13m_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_CLK26M_D2
+};
+
+static const int imgrz_sys_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D6,
+ CLK_TOP_MAINPLL_D7,
+ CLK_TOP_MAINPLL_D5,
+ CLK_TOP_UNIVPLL_D4,
+ CLK_TOP_UNIVPLL_D10,
+ CLK_TOP_UNIVPLL_D5,
+ CLK_TOP_UNIVPLL_D6
+};
+
+static const int graph_eclk_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D6,
+ CLK_TOP_UNIVPLL_D8,
+ CLK_TOP_UNIVPLL_D16,
+ CLK_TOP_MAINPLL_D7,
+ CLK_TOP_UNIVPLL_D4,
+ CLK_TOP_UNIVPLL_D10,
+ CLK_TOP_UNIVPLL_D24,
+ CLK_TOP_MAINPLL_D8
+};
+
+static const int fdbi_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D12,
+ CLK_TOP_MAINPLL_D14,
+ CLK_TOP_MAINPLL_D16,
+ CLK_TOP_UNIVPLL_D10,
+ CLK_TOP_UNIVPLL_D12,
+ CLK_TOP_UNIVPLL_D16,
+ CLK_TOP_UNIVPLL_D24,
+ CLK_TOP_TVDPLL_D2,
+ CLK_TOP_TVDPLL_D4,
+ CLK_TOP_TVDPLL_D8,
+ CLK_TOP_TVDPLL_D16
+};
+
+static const int faudio_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D24,
+ CLK_TOP_APLL1_D4,
+ CLK_TOP_APLL2_D4
+};
+
+static const int fa2sys_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL1_SRC_SEL,
+ CLK_TOP_RG_APLL1_D2,
+ CLK_TOP_RG_APLL1_D4,
+ CLK_TOP_RG_APLL1_D8,
+ CLK_TOP_RG_APLL1_D16,
+ CLK_TOP_CLK26M_D2,
+ CLK_TOP_RG_APLL1_D3
+};
+
+static const int fa1sys_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL2_SRC_SEL,
+ CLK_TOP_RG_APLL2_D2,
+ CLK_TOP_RG_APLL2_D4,
+ CLK_TOP_RG_APLL2_D8,
+ CLK_TOP_RG_APLL2_D16,
+ CLK_TOP_CLK26M_D2,
+ CLK_TOP_RG_APLL2_D3
+};
+
+static const int fasm_m_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D12,
+ CLK_TOP_UNIVPLL_D6,
+ CLK_TOP_MAINPLL_D7
+};
+
+static const int fecc_ck_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D6,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D4,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D3,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D3
+};
+
+static const int pe2_mac_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D11,
+ CLK_TOP_MAINPLL_D16,
+ CLK_TOP_UNIVPLL_D12,
+ CLK_TOP_UNIVPLL_D10
+};
+
+static const int cmsys_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D5,
+ CLK_TOP_UNIVPLL_D6,
+ CLK_TOP_MAINPLL_D5,
+ CLK_TOP_APLL2,
+ CLK_TOP_APLL2_D2,
+ CLK_TOP_APLL2_D4,
+ CLK_TOP_APLL2_D3
+};
+
+static const int gcpu_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D4,
+ CLK_TOP_MAINPLL_D5,
+ CLK_TOP_MAINPLL_D6,
+ CLK_TOP_MAINPLL_D7,
+ CLK_TOP_UNIVPLL_D4,
+ CLK_TOP_UNIVPLL_D10,
+ CLK_TOP_UNIVPLL_D3
+};
+
+static const int spis_ck_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D12,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D8,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D6,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D5,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D4,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D4,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D3
+};
+
+static const int apll1_ref_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL
+};
+
+static const int int_32k_parents[] = {
+ CLK_TOP_CLK32K,
+ CLK_TOP_CLK26M_D793
+};
+
+static const int apll1_src_parents[] = {
+ CLK_TOP_APLL1,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL
+};
+
+static const int apll2_src_parents[] = {
+ CLK_TOP_APLL2,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL
+};
+
+static const int faud_intbus_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D11,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D10,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_RG_APLL2_D8,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M_D2,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_RG_APLL1_D8,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D20
+};
+
+static const int axibus_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D11,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D12,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D10,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M_D2,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_APLL2_D8
+};
+
+static const int hapll1_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL1_SRC_SEL,
+ CLK_TOP_RG_APLL1_D2,
+ CLK_TOP_RG_APLL1_D4,
+ CLK_TOP_RG_APLL1_D8,
+ CLK_TOP_RG_APLL1_D16,
+ CLK_TOP_CLK26M_D2,
+ CLK_TOP_CLK26M_D8,
+ CLK_TOP_RG_APLL1_D3
+};
+
+static const int hapll2_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL2_SRC_SEL,
+ CLK_TOP_RG_APLL2_D2,
+ CLK_TOP_RG_APLL2_D4,
+ CLK_TOP_RG_APLL2_D8,
+ CLK_TOP_RG_APLL2_D16,
+ CLK_TOP_CLK26M_D2,
+ CLK_TOP_CLK26M_D4,
+ CLK_TOP_RG_APLL2_D3
+};
+
+static const int spinfi_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D24,
+ CLK_TOP_UNIVPLL_D20,
+ CLK_TOP_MAINPLL_D22,
+ CLK_TOP_UNIVPLL_D16,
+ CLK_TOP_MAINPLL_D16,
+ CLK_TOP_UNIVPLL_D12,
+ CLK_TOP_UNIVPLL_D10,
+ CLK_TOP_MAINPLL_D11
+};
+
+static const int msdc0_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D6,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D8,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D8,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D16,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D12,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_APMIXED_MMPLL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MMPLL_D2
+};
+
+static const int msdc0_clk50_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D6,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D8,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D8,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D6
+};
+
+static const int msdc2_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D6,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D8,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D8,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D16,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MMPLL_D2,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D12,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_APMIXED_MMPLL
+};
+
+static const int disp_dpi_ck_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_TVDPLL_D2,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_TVDPLL_D4,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_TVDPLL_D8,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_TVDPLL_D16
+};
+
+static const struct mtk_composite top_muxes[] = {
+ /* CLK_MUX_SEL0 */
+ MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
+ MUX(CLK_TOP_EMI1X_SEL, emi1x_parents, 0x000, 1, 1),
+ MUX(CLK_TOP_EMI_DDRPHY_SEL, emi_ddrphy_parents, 0x000, 2, 1),
+ MUX(CLK_TOP_MSDC1_SEL, msdc1_parents, 0x000, 4, 8),
+ MUX(CLK_TOP_PWM_MM_SEL, pwm_mm_parents, 0x000, 18, 1),
+ MUX(CLK_TOP_UART1_SEL, uart0_parents, 0x000, 19, 1),
+ MUX(CLK_TOP_SPM_52M_SEL, uart0_parents, 0x000, 22, 1),
+ MUX(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x000, 23, 3),
+ /* CLK_MUX_SEL1 */
+ MUX(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0x004, 0, 3),
+ MUX(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x004, 15, 1),
+ MUX(CLK_TOP_SMI_SEL, smi_parents, 0x004, 16, 4),
+ MUX(CLK_TOP_USB_SEL, usb_parents, 0x004, 20, 3),
+ /* CLK_MUX_SEL8 */
+ MUX(CLK_TOP_SPINOR_SEL, spinor_parents, 0x040, 0, 3),
+ MUX(CLK_TOP_ETH_SEL, eth_parents, 0x040, 6, 3),
+ MUX(CLK_TOP_AUD1_SEL, aud1_parents, 0x040, 22, 1),
+ MUX(CLK_TOP_AUD2_SEL, aud2_parents, 0x040, 23, 1),
+ MUX(CLK_TOP_I2C_SEL, i2c_parents, 0x040, 28, 3),
+ /* CLK_SEL_9 */
+ MUX(CLK_TOP_AUD_I2S0_M_SEL, aud_i2s0_m_parents, 0x044, 12, 1),
+ MUX(CLK_TOP_AUD_I2S3_M_SEL, aud_i2s0_m_parents, 0x044, 15, 1),
+ MUX(CLK_TOP_AUD_I2S4_M_SEL, aud_i2s0_m_parents, 0x044, 16, 1),
+ MUX(CLK_TOP_AUD_I2S6_M_SEL, aud_i2s0_m_parents, 0x044, 18, 1),
+ /* CLK_MUX_SEL13 */
+ MUX(CLK_TOP_PWM_SEL, pwm_mm_parents, 0x07c, 0, 1),
+ MUX(CLK_TOP_AUD_SPDIFIN_SEL, aud_spdifin_parents, 0x07c, 2, 2),
+ MUX(CLK_TOP_UART2_SEL, uart0_parents, 0x07c, 4, 1),
+ MUX(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents, 0x07c, 7, 3),
+ MUX(CLK_TOP_PNG_SYS_SEL, png_sys_parents, 0x07c, 16, 3),
+ MUX(CLK_TOP_SEJ_13M_SEL, sej_13m_parents, 0x07c, 22, 1),
+ /* CLK_MUX_SEL14 */
+ MUX(CLK_TOP_IMGRZ_SYS_SEL, imgrz_sys_parents, 0xc0, 0, 3),
+ MUX(CLK_TOP_GRAPH_ECLK_SEL, graph_eclk_parents, 0xc0, 8, 4),
+ MUX(CLK_TOP_FDBI_SEL, fdbi_parents, 0xc0, 12, 4),
+ MUX(CLK_TOP_FAUDIO_SEL, faudio_parents, 0xc0, 16, 2),
+ MUX(CLK_TOP_FA2SYS_SEL, fa2sys_parents, 0xc0, 24, 3),
+ MUX(CLK_TOP_FA1SYS_SEL, fa1sys_parents, 0xc0, 27, 3),
+ MUX(CLK_TOP_FASM_M_SEL, fasm_m_parents, 0xc0, 30, 2),
+ /* CLK_MUX_SEL15 */
+ MUX(CLK_TOP_FASM_H_SEL, fasm_m_parents, 0xC4, 0, 2),
+ MUX(CLK_TOP_FASM_L_SEL, fasm_m_parents, 0xC4, 2, 2),
+ MUX(CLK_TOP_FECC_CK_SEL, fecc_ck_parents, 0xC4, 18, 6),
+ MUX(CLK_TOP_PE2_MAC_SEL, pe2_mac_parents, 0xC4, 24, 3),
+ MUX(CLK_TOP_CMSYS_SEL, cmsys_parents, 0xC4, 28, 3),
+ /* CLK_MUX_SEL16 */
+ MUX(CLK_TOP_GCPU_SEL, gcpu_parents, 0xC8, 0, 3),
+ MUX(CLK_TOP_SPIS_CK_SEL, spis_ck_parents, 0xC8, 4, 8),
+ /* CLK_MUX_SEL17 */
+ MUX(CLK_TOP_APLL1_REF_SEL, apll1_ref_parents, 0xCC, 6, 3),
+ MUX(CLK_TOP_APLL2_REF_SEL, apll1_ref_parents, 0xCC, 9, 3),
+ MUX(CLK_TOP_INT_32K_SEL, int_32k_parents, 0xCC, 12, 1),
+ MUX(CLK_TOP_APLL1_SRC_SEL, apll1_src_parents, 0xCC, 13, 2),
+ MUX(CLK_TOP_APLL2_SRC_SEL, apll2_src_parents, 0xCC, 15, 2),
+ /* CLK_MUX_SEL19 */
+ MUX(CLK_TOP_FAUD_INTBUS_SEL, faud_intbus_parents, 0xD4, 8, 8),
+ MUX(CLK_TOP_AXIBUS_SEL, axibus_parents, 0xD4, 24, 8),
+ /* CLK_MUX_SEL21 */
+ MUX(CLK_TOP_HAPLL1_SEL, hapll1_parents, 0xDC, 0, 4),
+ MUX(CLK_TOP_HAPLL2_SEL, hapll2_parents, 0xDC, 4, 4),
+ MUX(CLK_TOP_SPINFI_SEL, spinfi_parents, 0xDC, 8, 4),
+ /* CLK_MUX_SEL22 */
+ MUX(CLK_TOP_MSDC0_SEL, msdc0_parents, 0xF4, 0, 8),
+ MUX(CLK_TOP_MSDC0_CLK50_SEL, msdc0_clk50_parents, 0xF4, 8, 6),
+ MUX(CLK_TOP_MSDC2_SEL, msdc2_parents, 0xF4, 15, 8),
+ MUX(CLK_TOP_MSDC2_CLK50_SEL, msdc0_clk50_parents, 0xF4, 23, 6),
+ /* CLK_MUX_SEL23 */
+ MUX(CLK_TOP_DISP_DPI_CK_SEL, disp_dpi_ck_parents, 0xF8, 0, 6),
+ MUX(CLK_TOP_SPI1_SEL, spis_ck_parents, 0xF8, 6, 8),
+ MUX(CLK_TOP_SPI2_SEL, spis_ck_parents, 0xF8, 14, 8),
+ MUX(CLK_TOP_SPI3_SEL, spis_ck_parents, 0xF8, 22, 8),
+};
+
+static const struct mtk_gate_regs top0_cg_regs = {
+ .set_ofs = 0x50,
+ .clr_ofs = 0x80,
+ .sta_ofs = 0x20,
+};
+
+static const struct mtk_gate_regs top1_cg_regs = {
+ .set_ofs = 0x54,
+ .clr_ofs = 0x84,
+ .sta_ofs = 0x24,
+};
+
+static const struct mtk_gate_regs top2_cg_regs = {
+ .set_ofs = 0x6c,
+ .clr_ofs = 0x9c,
+ .sta_ofs = 0x3c,
+};
+
+static const struct mtk_gate_regs top3_cg_regs = {
+ .set_ofs = 0x44,
+ .clr_ofs = 0x44,
+ .sta_ofs = 0x44,
+};
+
+static const struct mtk_gate_regs top4_cg_regs = {
+ .set_ofs = 0xa0,
+ .clr_ofs = 0xb0,
+ .sta_ofs = 0x70,
+};
+
+static const struct mtk_gate_regs top5_cg_regs = {
+ .set_ofs = 0x120,
+ .clr_ofs = 0x140,
+ .sta_ofs = 0xe0,
+};
+
+static const struct mtk_gate_regs top6_cg_regs = {
+ .set_ofs = 0x128,
+ .clr_ofs = 0x148,
+ .sta_ofs = 0xe8,
+};
+
+static const struct mtk_gate_regs top7_cg_regs = {
+ .set_ofs = 0x12c,
+ .clr_ofs = 0x14c,
+ .sta_ofs = 0xec,
+};
+
+#define GATE_TOP0(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top0_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP1(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top1_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP2(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top2_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP2_I(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top2_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP3(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top3_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP4(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top4_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP5(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top5_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP5_I(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top5_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP6(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top6_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP7(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top7_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+ }
+
+static const struct mtk_gate top_clks[] = {
+ /* TOP0 */
+ GATE_TOP0(CLK_TOP_PWM_MM, CLK_TOP_PWM_MM_SEL, 0),
+ GATE_TOP0(CLK_TOP_SMI, CLK_TOP_SMI_SEL, 9),
+ GATE_TOP0(CLK_TOP_SPI2, CLK_TOP_SPI2_SEL, 10),
+ GATE_TOP0(CLK_TOP_SPI3, CLK_TOP_SPI3_SEL, 11),
+ GATE_TOP0(CLK_TOP_SPINFI, CLK_TOP_SPINFI_SEL, 12),
+ GATE_TOP0(CLK_TOP_26M_DEBUG, CLK_TOP_CLK26M, 16),
+ GATE_TOP0(CLK_TOP_USB_48M_DEBUG, CLK_TOP_USB20_48M, 17),
+ GATE_TOP0(CLK_TOP_52M_DEBUG, CLK_TOP_UNIVPLL_D24, 18),
+ GATE_TOP0(CLK_TOP_32K_DEBUG, CLK_TOP_INT_32K_SEL, 19),
+ /* TOP1 */
+ GATE_TOP1(CLK_TOP_THERM, CLK_TOP_AXIBUS_SEL, 1),
+ GATE_TOP1(CLK_TOP_APDMA, CLK_TOP_AXIBUS_SEL, 2),
+ GATE_TOP1(CLK_TOP_I2C0, CLK_TOP_AHB_INFRA_D2, 3),
+ GATE_TOP1(CLK_TOP_I2C1, CLK_TOP_AHB_INFRA_D2, 4),
+ GATE_TOP1(CLK_TOP_AUXADC1, CLK_TOP_CLK26M, 5),
+ GATE_TOP1(CLK_TOP_NFI, CLK_TOP_NFI1X_INFRA_BCLK, 6),
+ GATE_TOP1(CLK_TOP_NFIECC, CLK_TOP_AXIBUS_SEL, 7),
+ GATE_TOP1(CLK_TOP_DEBUGSYS, CLK_TOP_DBG_ATCLK_SEL, 8),
+ GATE_TOP1(CLK_TOP_PWM, CLK_TOP_AXIBUS_SEL, 9),
+ GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
+ GATE_TOP1(CLK_TOP_UART1, CLK_TOP_UART1_SEL, 11),
+ GATE_TOP1(CLK_TOP_USB, CLK_TOP_USB_B, 13),
+ GATE_TOP1(CLK_TOP_FLASHIF_26M, CLK_TOP_CLK26M, 14),
+ GATE_TOP1(CLK_TOP_AUXADC2, CLK_TOP_CLK26M, 15),
+ GATE_TOP1(CLK_TOP_I2C2, CLK_TOP_AHB_INFRA_D2, 16),
+ GATE_TOP1(CLK_TOP_MSDC0, CLK_TOP_MSDC0_SEL, 17),
+ GATE_TOP1(CLK_TOP_MSDC1, CLK_TOP_MSDC1_SEL, 18),
+ GATE_TOP1(CLK_TOP_NFI2X, CLK_TOP_NFI2X_SEL, 19),
+ GATE_TOP1(CLK_TOP_MEMSLP_DLYER, CLK_TOP_CLK26M, 22),
+ GATE_TOP1(CLK_TOP_SPI, CLK_TOP_SPI1_SEL, 23),
+ GATE_TOP1(CLK_TOP_APXGPT, CLK_TOP_CLK26M, 24),
+ GATE_TOP1(CLK_TOP_PMICWRAP_MD, CLK_TOP_CLK26M, 27),
+ GATE_TOP1(CLK_TOP_PMICWRAP_CONN, CLK_TOP_PMICSPI_SEL, 28),
+ GATE_TOP1(CLK_TOP_PMIC_SYSCK, CLK_TOP_CLK26M, 29),
+ GATE_TOP1(CLK_TOP_AUX_ADC, CLK_TOP_CLK26M, 30),
+ GATE_TOP1(CLK_TOP_AUX_TP, CLK_TOP_CLK26M, 31),
+ /* TOP2 */
+ GATE_TOP2(CLK_TOP_RBIST, CLK_TOP_UNIVPLL_D12, 1),
+ GATE_TOP2(CLK_TOP_NFI_BUS, CLK_TOP_AXIBUS_SEL, 2),
+ GATE_TOP2(CLK_TOP_GCE, CLK_TOP_AXIBUS_SEL, 4),
+ GATE_TOP2(CLK_TOP_TRNG, CLK_TOP_AXIBUS_SEL, 5),
+ GATE_TOP2(CLK_TOP_PWM_B, CLK_TOP_PWM_SEL, 8),
+ GATE_TOP2(CLK_TOP_PWM1_FB, CLK_TOP_PWM_SEL, 9),
+ GATE_TOP2(CLK_TOP_PWM2_FB, CLK_TOP_PWM_SEL, 10),
+ GATE_TOP2(CLK_TOP_PWM3_FB, CLK_TOP_PWM_SEL, 11),
+ GATE_TOP2(CLK_TOP_PWM4_FB, CLK_TOP_PWM_SEL, 12),
+ GATE_TOP2(CLK_TOP_PWM5_FB, CLK_TOP_PWM_SEL, 13),
+ GATE_TOP2(CLK_TOP_FLASHIF_FREERUN, CLK_TOP_AXIBUS_SEL, 15),
+ GATE_TOP2(CLK_TOP_CQDMA, CLK_TOP_AXIBUS_SEL, 17),
+ GATE_TOP2(CLK_TOP_66M_ETH, CLK_TOP_AXIBUS_SEL, 19),
+ GATE_TOP2(CLK_TOP_133M_ETH, CLK_TOP_AXIBUS_SEL, 20),
+ GATE_TOP2(CLK_TOP_FLASHIF_AXI, CLK_TOP_SPI1_SEL, 23),
+ GATE_TOP2(CLK_TOP_USBIF, CLK_TOP_AXIBUS_SEL, 24),
+ GATE_TOP2(CLK_TOP_UART2, CLK_TOP_RG_UART2, 25),
+ GATE_TOP2(CLK_TOP_GCPU_B, CLK_TOP_AXIBUS_SEL, 27),
+ GATE_TOP2_I(CLK_TOP_MSDC0_B, CLK_TOP_MSDC0, 28),
+ GATE_TOP2_I(CLK_TOP_MSDC1_B, CLK_TOP_MSDC1, 29),
+ GATE_TOP2_I(CLK_TOP_MSDC2_B, CLK_TOP_MSDC2, 30),
+ GATE_TOP2(CLK_TOP_USB_B, CLK_TOP_USB_SEL, 31),
+ /* TOP3 */
+ GATE_TOP3(CLK_TOP_APLL12_DIV0, CLK_TOP_APLL12_CK_DIV0, 0),
+ GATE_TOP3(CLK_TOP_APLL12_DIV3, CLK_TOP_APLL12_CK_DIV3, 3),
+ GATE_TOP3(CLK_TOP_APLL12_DIV4, CLK_TOP_APLL12_CK_DIV4, 4),
+ GATE_TOP3(CLK_TOP_APLL12_DIV6, CLK_TOP_APLL12_CK_DIV6, 8),
+ /* TOP4 */
+ GATE_TOP4(CLK_TOP_SPINOR, CLK_TOP_SPINOR_SEL, 0),
+ GATE_TOP4(CLK_TOP_MSDC2, CLK_TOP_MSDC2_SEL, 1),
+ GATE_TOP4(CLK_TOP_ETH, CLK_TOP_ETH_SEL, 2),
+ GATE_TOP4(CLK_TOP_AUD1, CLK_TOP_AUD1_SEL, 8),
+ GATE_TOP4(CLK_TOP_AUD2, CLK_TOP_AUD2_SEL, 9),
+ GATE_TOP4(CLK_TOP_I2C, CLK_TOP_I2C_SEL, 12),
+ GATE_TOP4(CLK_TOP_PWM_INFRA, CLK_TOP_PWM_SEL, 13),
+ GATE_TOP4(CLK_TOP_AUD_SPDIF_IN, CLK_TOP_AUD_SPDIFIN_SEL, 14),
+ GATE_TOP4(CLK_TOP_RG_UART2, CLK_TOP_UART2_SEL, 15),
+ GATE_TOP4(CLK_TOP_DBG_AT, CLK_TOP_DBG_ATCLK_SEL, 17),
+ /* TOP5 */
+ GATE_TOP5_I(CLK_TOP_IMGRZ_SYS, CLK_TOP_IMGRZ_SYS_SEL, 0),
+ GATE_TOP5_I(CLK_TOP_PNG_SYS, CLK_TOP_PNG_SYS_SEL, 1),
+ GATE_TOP5_I(CLK_TOP_GRAPH_E, CLK_TOP_GRAPH_ECLK_SEL, 2),
+ GATE_TOP5_I(CLK_TOP_FDBI, CLK_TOP_FDBI_SEL, 3),
+ GATE_TOP5_I(CLK_TOP_FAUDIO, CLK_TOP_FAUDIO_SEL, 4),
+ GATE_TOP5_I(CLK_TOP_FAUD_INTBUS, CLK_TOP_FAUD_INTBUS_SEL, 5),
+ GATE_TOP5_I(CLK_TOP_HAPLL1, CLK_TOP_HAPLL1_SEL, 6),
+ GATE_TOP5_I(CLK_TOP_HAPLL2, CLK_TOP_HAPLL2_SEL, 7),
+ GATE_TOP5_I(CLK_TOP_FA2SYS, CLK_TOP_FA2SYS_SEL, 8),
+ GATE_TOP5_I(CLK_TOP_FA1SYS, CLK_TOP_FA1SYS_SEL, 9),
+ GATE_TOP5_I(CLK_TOP_FASM_L, CLK_TOP_FASM_L_SEL, 10),
+ GATE_TOP5_I(CLK_TOP_FASM_M, CLK_TOP_FASM_M_SEL, 11),
+ GATE_TOP5_I(CLK_TOP_FASM_H, CLK_TOP_FASM_H_SEL, 12),
+ GATE_TOP5_I(CLK_TOP_FECC, CLK_TOP_FECC_CK_SEL, 23),
+ GATE_TOP5_I(CLK_TOP_PE2_MAC, CLK_TOP_PE2_MAC_SEL, 24),
+ GATE_TOP5_I(CLK_TOP_CMSYS, CLK_TOP_CMSYS_SEL, 25),
+ GATE_TOP5_I(CLK_TOP_GCPU, CLK_TOP_GCPU_SEL, 26),
+ GATE_TOP5(CLK_TOP_SPIS, CLK_TOP_SPIS_CK_SEL, 27),
+ /* TOP6 */
+ GATE_TOP6(CLK_TOP_I2C3, CLK_TOP_AHB_INFRA_D2, 0),
+ GATE_TOP6(CLK_TOP_SPI_SLV_B, CLK_TOP_SPIS_CK_SEL, 1),
+ GATE_TOP6(CLK_TOP_SPI_SLV_BUS, CLK_TOP_AXIBUS_SEL, 2),
+ GATE_TOP6(CLK_TOP_PCIE_MAC_BUS, CLK_TOP_AXIBUS_SEL, 3),
+ GATE_TOP6(CLK_TOP_CMSYS_BUS, CLK_TOP_AXIBUS_SEL, 4),
+ GATE_TOP6(CLK_TOP_ECC_B, CLK_TOP_AXIBUS_SEL, 5),
+ GATE_TOP6(CLK_TOP_PCIE_PHY_BUS, CLK_TOP_CLK26M, 6),
+ GATE_TOP6(CLK_TOP_PCIE_AUX, CLK_TOP_CLK26M, 7),
+ /* TOP7 */
+ GATE_TOP7(CLK_TOP_DISP_DPI, CLK_TOP_DISP_DPI_CK_SEL, 0),
+};
+
+static const struct mtk_clk_tree mt8518_clk_tree = {
+ .xtal_rate = 26 * MHZ,
+ .xtal2_rate = 26 * MHZ,
+ .fdivs_offs = CLK_TOP_DMPLL,
+ .muxes_offs = CLK_TOP_UART0_SEL,
+ .plls = apmixed_plls,
+ .fclks = top_fixed_clks,
+ .fdivs = top_fixed_divs,
+ .muxes = top_muxes,
+};
+
+static int mt8518_apmixedsys_probe(struct udevice *dev)
+{
+ return mtk_common_clk_init(dev, &mt8518_clk_tree);
+}
+
+static int mt8518_topckgen_probe(struct udevice *dev)
+{
+ return mtk_common_clk_init(dev, &mt8518_clk_tree);
+}
+
+static int mt8518_topckgen_cg_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt8518_clk_tree, top_clks);
+}
+
+static const struct udevice_id mt8518_apmixed_compat[] = {
+ { .compatible = "mediatek,mt8518-apmixedsys", },
+ { }
+};
+
+static const struct udevice_id mt8518_topckgen_compat[] = {
+ { .compatible = "mediatek,mt8518-topckgen", },
+ { }
+};
+
+static const struct udevice_id mt8518_topckgen_cg_compat[] = {
+ { .compatible = "mediatek,mt8518-topckgen-cg", },
+ { }
+};
+
+U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+ .name = "mt8518-apmixedsys",
+ .id = UCLASS_CLK,
+ .of_match = mt8518_apmixed_compat,
+ .probe = mt8518_apmixedsys_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_apmixedsys_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen) = {
+ .name = "mt8518-topckgen",
+ .id = UCLASS_CLK,
+ .of_match = mt8518_topckgen_compat,
+ .probe = mt8518_topckgen_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_topckgen_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen_cg) = {
+ .name = "mt8518-topckgen-cg",
+ .id = UCLASS_CLK,
+ .of_match = mt8518_topckgen_cg_compat,
+ .probe = mt8518_topckgen_cg_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .ops = &mtk_clk_gate_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c
index e9e55c9d16..a974744a61 100644
--- a/drivers/core/regmap.c
+++ b/drivers/core/regmap.c
@@ -134,7 +134,7 @@ int regmap_init_mem_index(ofnode node, struct regmap **mapp, int index)
ret = init_range(node, map->ranges, addr_len, size_len, index);
if (ret)
- return ret;
+ goto err;
if (ofnode_read_bool(node, "little-endian"))
map->endianness = REGMAP_LITTLE_ENDIAN;
@@ -147,6 +147,10 @@ int regmap_init_mem_index(ofnode node, struct regmap **mapp, int index)
*mapp = map;
+ return 0;
+err:
+ regmap_uninit(map);
+
return ret;
}
@@ -158,6 +162,7 @@ int regmap_init_mem(ofnode node, struct regmap **mapp)
int addr_len, size_len, both_len;
int len;
int index;
+ int ret;
addr_len = ofnode_read_simple_addr_cells(ofnode_get_parent(node));
if (addr_len < 0) {
@@ -200,10 +205,9 @@ int regmap_init_mem(ofnode node, struct regmap **mapp)
for (range = map->ranges, index = 0; count > 0;
count--, range++, index++) {
- int ret = init_range(node, range, addr_len, size_len, index);
-
+ ret = init_range(node, range, addr_len, size_len, index);
if (ret)
- return ret;
+ goto err;
}
if (ofnode_read_bool(node, "little-endian"))
@@ -218,6 +222,10 @@ int regmap_init_mem(ofnode node, struct regmap **mapp)
*mapp = map;
return 0;
+err:
+ regmap_uninit(map);
+
+ return ret;
}
#endif
diff --git a/drivers/mmc/davinci_mmc.c b/drivers/mmc/davinci_mmc.c
index 0d63279db0..c3f7b57665 100644
--- a/drivers/mmc/davinci_mmc.c
+++ b/drivers/mmc/davinci_mmc.c
@@ -26,22 +26,12 @@
#define clear_bit(addr, val) set_val((addr), (get_val(addr) & ~(val)))
#ifdef CONFIG_DM_MMC
-struct davinci_of_data {
- const char *name;
- u8 version;
-};
-
/* Davinci MMC board definitions */
struct davinci_mmc_priv {
struct davinci_mmc_regs *reg_base; /* Register base address */
uint input_clk; /* Input clock to MMC controller */
- uint version; /* MMC Controller version */
struct gpio_desc cd_gpio; /* Card Detect GPIO */
struct gpio_desc wp_gpio; /* Write Protect GPIO */
-};
-
-struct davinci_mmc_plat
-{
struct mmc_config cfg;
struct mmc mmc;
};
@@ -173,7 +163,7 @@ davinci_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *
/* Clear status registers */
mmcstatus = get_val(&regs->mmcst0);
- fifo_words = (host->version == MMC_CTLR_VERSION_2) ? 16 : 8;
+ fifo_words = 16;
fifo_bytes = fifo_words << 2;
/* Wait for any previous busy signal to be cleared */
@@ -211,8 +201,7 @@ davinci_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *
set_val(&regs->mmcfifoctl,
(MMCFIFOCTL_FIFOLEV | MMCFIFOCTL_FIFORST));
- if (host->version == MMC_CTLR_VERSION_2)
- cmddata |= MMCCMD_DMATRIG;
+ cmddata |= MMCCMD_DMATRIG;
cmddata |= MMCCMD_WDATX;
if (data->flags == MMC_DATA_READ) {
@@ -491,21 +480,18 @@ int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host)
static int davinci_mmc_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
- struct davinci_mmc_plat *plat = dev_get_platdata(dev);
struct davinci_mmc_priv *priv = dev_get_priv(dev);
- struct mmc_config *cfg = &plat->cfg;
- struct davinci_of_data *data =
- (struct davinci_of_data *)dev_get_driver_data(dev);
+ struct mmc_config *cfg = &priv->cfg;
+#ifdef CONFIG_SPL_BUILD
+ int ret;
+#endif
+
cfg->f_min = 200000;
cfg->f_max = 25000000;
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
cfg->host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */
cfg->b_max = DAVINCI_MAX_BLOCKS;
-
- if (data) {
- cfg->name = data->name;
- priv->version = data->version;
- }
+ cfg->name = "da830-mmc";
priv->reg_base = (struct davinci_mmc_regs *)dev_read_addr(dev);
priv->input_clk = clk_get(DAVINCI_MMCSD_CLKID);
@@ -516,40 +502,34 @@ static int davinci_mmc_probe(struct udevice *dev)
gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
#endif
- upriv->mmc = &plat->mmc;
+ upriv->mmc = &priv->mmc;
+
+#ifdef CONFIG_SPL_BUILD
+ /*
+ * FIXME This is a temporary workaround to enable the driver model in
+ * SPL on omapl138-lcdk. For some reason the bind() callback is not
+ * being called in SPL for MMC which breaks the mmc boot - the hack
+ * is to call mmc_bind() from probe(). We also don't have full DT
+ * support in SPL, hence the hard-coded base register address.
+ */
+ priv->reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE;
+ ret = mmc_bind(dev, &priv->mmc, &priv->cfg);
+ if (ret)
+ return ret;
+#endif
return davinci_dm_mmc_init(dev);
}
static int davinci_mmc_bind(struct udevice *dev)
{
- struct davinci_mmc_plat *plat = dev_get_platdata(dev);
+ struct davinci_mmc_priv *priv = dev_get_priv(dev);
- return mmc_bind(dev, &plat->mmc, &plat->cfg);
+ return mmc_bind(dev, &priv->mmc, &priv->cfg);
}
-
-const struct davinci_of_data davinci_mmc_host_info[] = {
- {
- .name = "dm6441-mmc",
- .version = MMC_CTLR_VERSION_1,
- },
- {
- .name = "da830-mmc",
- .version = MMC_CTLR_VERSION_2,
- },
- {},
-};
-
static const struct udevice_id davinci_mmc_ids[] = {
- {
- .compatible = "ti,dm6441-mmc",
- .data = (ulong) &davinci_mmc_host_info[MMC_CTLR_VERSION_1]
- },
- {
- .compatible = "ti,da830-mmc",
- .data = (ulong) &davinci_mmc_host_info[MMC_CTLR_VERSION_2]
- },
+ { .compatible = "ti,da830-mmc" },
{},
};
@@ -562,7 +542,6 @@ U_BOOT_DRIVER(davinci_mmc_drv) = {
#endif
.probe = davinci_mmc_probe,
.ops = &davinci_mmc_ops,
- .platdata_auto_alloc_size = sizeof(struct davinci_mmc_plat),
.priv_auto_alloc_size = sizeof(struct davinci_mmc_priv),
};
#endif
diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
index ffd647fac7..eaa584a4df 100644
--- a/drivers/mmc/mtk-sd.c
+++ b/drivers/mmc/mtk-sd.c
@@ -125,6 +125,9 @@
#define MSDC_PAD_TUNE_DATWRDLY_M 0x1f
#define MSDC_PAD_TUNE_DATWRDLY_S 0
+#define PAD_CMD_TUNE_RX_DLY3 0x3E
+#define PAD_CMD_TUNE_RX_DLY3_S 1
+
/* EMMC50_CFG0 */
#define EMMC50_CFG_CFCSTS_SEL BIT(4)
@@ -209,7 +212,8 @@ struct mtk_sd_regs {
u32 eco_ver;
u32 reserved6[27];
u32 pad_ds_tune;
- u32 reserved7[31];
+ u32 pad_cmd_tune;
+ u32 reserved7[30];
u32 emmc50_cfg0;
u32 reserved8[7];
u32 sdc_fifo_cfg;
@@ -240,6 +244,7 @@ struct msdc_plat {
struct msdc_tune_para {
u32 iocon;
u32 pad_tune;
+ u32 pad_cmd_tune;
};
struct msdc_host {
@@ -364,6 +369,8 @@ static u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
case MMC_CMD_WRITE_SINGLE_BLOCK:
case MMC_CMD_READ_SINGLE_BLOCK:
case SD_CMD_APP_SEND_SCR:
+ case MMC_CMD_SEND_TUNING_BLOCK:
+ case MMC_CMD_SEND_TUNING_BLOCK_HS200:
dtype = 1;
break;
case SD_CMD_SWITCH_FUNC: /* same as MMC_CMD_SWITCH */
@@ -469,6 +476,14 @@ static int msdc_start_command(struct msdc_host *host, struct mmc_cmd *cmd,
if (!msdc_cmd_is_ready(host))
return -EIO;
+ if ((readl(&host->base->msdc_fifocs) &
+ MSDC_FIFOCS_TXCNT_M) >> MSDC_FIFOCS_TXCNT_S ||
+ (readl(&host->base->msdc_fifocs) &
+ MSDC_FIFOCS_RXCNT_M) >> MSDC_FIFOCS_RXCNT_S) {
+ pr_err("TX/RX FIFO non-empty before start of IO. Reset\n");
+ msdc_reset_hw(host);
+ }
+
msdc_fifo_clr(host);
host->last_resp_type = cmd->resp_type;
@@ -652,14 +667,22 @@ static int msdc_ops_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
struct mmc_data *data)
{
struct msdc_host *host = dev_get_priv(dev);
- int ret;
+ int cmd_ret, data_ret;
- ret = msdc_start_command(host, cmd, data);
- if (ret)
- return ret;
+ cmd_ret = msdc_start_command(host, cmd, data);
+ if (cmd_ret &&
+ !(cmd_ret == -EIO &&
+ (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
+ cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)))
+ return cmd_ret;
- if (data)
- return msdc_start_data(host, data);
+ if (data) {
+ data_ret = msdc_start_data(host, data);
+ if (cmd_ret)
+ return cmd_ret;
+ else
+ return data_ret;
+ }
return 0;
}
@@ -941,6 +964,56 @@ static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
return delay_phase;
}
+static int hs400_tune_response(struct udevice *dev, u32 opcode)
+{
+ struct msdc_plat *plat = dev_get_platdata(dev);
+ struct msdc_host *host = dev_get_priv(dev);
+ struct mmc *mmc = &plat->mmc;
+ u32 cmd_delay = 0;
+ struct msdc_delay_phase final_cmd_delay = { 0, };
+ u8 final_delay;
+ void __iomem *tune_reg = &host->base->pad_cmd_tune;
+ int cmd_err;
+ int i, j;
+
+ setbits_le32(&host->base->pad_cmd_tune, BIT(0));
+
+ if (mmc->selected_mode == MMC_HS_200 ||
+ mmc->selected_mode == UHS_SDR104)
+ clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
+ host->hs200_cmd_int_delay <<
+ MSDC_PAD_TUNE_CMDRRDLY_S);
+
+ if (host->r_smpl)
+ clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
+ else
+ setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
+
+ for (i = 0; i < PAD_DELAY_MAX; i++) {
+ clrsetbits_le32(tune_reg, PAD_CMD_TUNE_RX_DLY3,
+ i << PAD_CMD_TUNE_RX_DLY3_S);
+
+ for (j = 0; j < 3; j++) {
+ mmc_send_tuning(mmc, opcode, &cmd_err);
+ if (!cmd_err) {
+ cmd_delay |= (1 << i);
+ } else {
+ cmd_delay &= ~(1 << i);
+ break;
+ }
+ }
+ }
+
+ final_cmd_delay = get_best_delay(host, cmd_delay);
+ clrsetbits_le32(tune_reg, PAD_CMD_TUNE_RX_DLY3,
+ final_cmd_delay.final_phase <<
+ PAD_CMD_TUNE_RX_DLY3_S);
+ final_delay = final_cmd_delay.final_phase;
+
+ dev_err(dev, "Final cmd pad delay: %x\n", final_delay);
+ return final_delay == 0xff ? -EIO : 0;
+}
+
static int msdc_tune_response(struct udevice *dev, u32 opcode)
{
struct msdc_plat *plat = dev_get_platdata(dev);
@@ -1132,34 +1205,138 @@ skip_fall:
return final_delay == 0xff ? -EIO : 0;
}
+/*
+ * MSDC IP which supports data tune + async fifo can do CMD/DAT tune
+ * together, which can save the tuning time.
+ */
+static int msdc_tune_together(struct udevice *dev, u32 opcode)
+{
+ struct msdc_plat *plat = dev_get_platdata(dev);
+ struct msdc_host *host = dev_get_priv(dev);
+ struct mmc *mmc = &plat->mmc;
+ u32 rise_delay = 0, fall_delay = 0;
+ struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
+ u8 final_delay, final_maxlen;
+ void __iomem *tune_reg = &host->base->pad_tune;
+ int i, ret;
+
+ if (host->dev_comp->pad_tune0)
+ tune_reg = &host->base->pad_tune0;
+
+ clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
+ clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
+
+ for (i = 0; i < PAD_DELAY_MAX; i++) {
+ clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
+ i << MSDC_PAD_TUNE_CMDRDLY_S);
+ clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
+ i << MSDC_PAD_TUNE_DATRRDLY_S);
+
+ ret = mmc_send_tuning(mmc, opcode, NULL);
+ if (!ret)
+ rise_delay |= (1 << i);
+ }
+
+ final_rise_delay = get_best_delay(host, rise_delay);
+ if (final_rise_delay.maxlen >= 12 ||
+ (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
+ goto skip_fall;
+
+ setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
+ setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
+
+ for (i = 0; i < PAD_DELAY_MAX; i++) {
+ clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
+ i << MSDC_PAD_TUNE_CMDRDLY_S);
+ clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
+ i << MSDC_PAD_TUNE_DATRRDLY_S);
+
+ ret = mmc_send_tuning(mmc, opcode, NULL);
+ if (!ret)
+ fall_delay |= (1 << i);
+ }
+
+ final_fall_delay = get_best_delay(host, fall_delay);
+
+skip_fall:
+ final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
+ if (final_maxlen == final_rise_delay.maxlen) {
+ clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
+ clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
+ clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
+ final_rise_delay.final_phase <<
+ MSDC_PAD_TUNE_CMDRDLY_S);
+ clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
+ final_rise_delay.final_phase <<
+ MSDC_PAD_TUNE_DATRRDLY_S);
+ final_delay = final_rise_delay.final_phase;
+ } else {
+ setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
+ setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
+ clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
+ final_fall_delay.final_phase <<
+ MSDC_PAD_TUNE_CMDRDLY_S);
+ clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
+ final_fall_delay.final_phase <<
+ MSDC_PAD_TUNE_DATRRDLY_S);
+ final_delay = final_fall_delay.final_phase;
+ }
+
+ dev_err(dev, "Final pad delay: %x\n", final_delay);
+
+ return final_delay == 0xff ? -EIO : 0;
+}
+
static int msdc_execute_tuning(struct udevice *dev, uint opcode)
{
struct msdc_plat *plat = dev_get_platdata(dev);
struct msdc_host *host = dev_get_priv(dev);
struct mmc *mmc = &plat->mmc;
- int ret;
+ int ret = 0;
+
+ if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
+ ret = msdc_tune_together(dev, opcode);
+ if (ret == -EIO) {
+ dev_err(dev, "Tune fail!\n");
+ return ret;
+ }
- if (mmc->selected_mode == MMC_HS_400) {
- writel(host->hs400_ds_delay, &host->base->pad_ds_tune);
- /* for hs400 mode it must be set to 0 */
- clrbits_le32(&host->base->patch_bit2, MSDC_PB2_CFGCRCSTS);
- host->hs400_mode = true;
+ if (mmc->selected_mode == MMC_HS_400) {
+ clrbits_le32(&host->base->msdc_iocon,
+ MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
+ clrsetbits_le32(&host->base->pad_tune,
+ MSDC_PAD_TUNE_DATRRDLY_M, 0);
+
+ writel(host->hs400_ds_delay, &host->base->pad_ds_tune);
+ /* for hs400 mode it must be set to 0 */
+ clrbits_le32(&host->base->patch_bit2,
+ MSDC_PB2_CFGCRCSTS);
+ host->hs400_mode = true;
+ }
+ goto tune_done;
}
- ret = msdc_tune_response(dev, opcode);
+ if (mmc->selected_mode == MMC_HS_400)
+ ret = hs400_tune_response(dev, opcode);
+ else
+ ret = msdc_tune_response(dev, opcode);
if (ret == -EIO) {
dev_err(dev, "Tune response fail!\n");
return ret;
}
- if (!host->hs400_mode) {
+ if (mmc->selected_mode != MMC_HS_400) {
ret = msdc_tune_data(dev, opcode);
- if (ret == -EIO)
+ if (ret == -EIO) {
dev_err(dev, "Tune data fail!\n");
+ return ret;
+ }
}
+tune_done:
host->saved_tune_para.iocon = readl(&host->base->msdc_iocon);
host->saved_tune_para.pad_tune = readl(&host->base->pad_tune);
+ host->saved_tune_para.pad_cmd_tune = readl(&host->base->pad_cmd_tune);
return ret;
}
diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c
index 89ac8229f5..dd04d676d5 100644
--- a/drivers/mtd/mtdcore.c
+++ b/drivers/mtd/mtdcore.c
@@ -76,8 +76,6 @@ static struct class mtd_class = {
.resume = mtd_cls_resume,
};
#else
-struct mtd_info *mtd_table[MAX_MTD_DEVICES];
-
#define MAX_IDR_ID 64
struct idr_layer {
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 30bd8e7653..bcea8a0c3e 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -100,6 +100,28 @@ config PHY_BROADCOM
config PHY_CORTINA
bool "Cortina Ethernet PHYs support"
+choice
+ prompt "Location of the Cortina firmware"
+ default SYS_CORTINA_FW_IN_NOR
+ depends on PHY_CORTINA
+
+config SYS_CORTINA_FW_IN_MMC
+ bool "Cortina firmware in MMC"
+
+config SYS_CORTINA_FW_IN_NAND
+ bool "Cortina firmware in NAND flash"
+
+config SYS_CORTINA_FW_IN_NOR
+ bool "Cortina firmware in NOR flash"
+
+config SYS_CORTINA_FW_IN_REMOTE
+ bool "Cortina firmware in remote device"
+
+config SYS_CORTINA_FW_IN_SPIFLASH
+ bool "Cortina firmware in SPI flash"
+
+endchoice
+
config PHY_DAVICOM
bool "Davicom Ethernet PHYs support"
diff --git a/drivers/net/ti/cpsw.c b/drivers/net/ti/cpsw.c
index 93d53612b5..57625623c2 100644
--- a/drivers/net/ti/cpsw.c
+++ b/drivers/net/ti/cpsw.c
@@ -1224,6 +1224,9 @@ static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
int ret;
data = calloc(1, sizeof(struct cpsw_platform_data));
+ if (!data)
+ return -ENOMEM;
+
pdata->priv_pdata = data;
pdata->iobase = dev_read_addr(dev);
data->version = CPSW_CTRL_VERSION_2;
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 219473aa79..da8b826d69 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -4,12 +4,12 @@
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
ifneq ($(CONFIG_DM_PCI),)
-obj-y += pci_rom.o
+obj-$(CONFIG_DM_VIDEO) += pci_rom.o
obj-$(CONFIG_PCI) += pci-uclass.o pci_auto.o
obj-$(CONFIG_DM_PCI_COMPAT) += pci_compat.o
obj-$(CONFIG_PCI_SANDBOX) += pci_sandbox.o
obj-$(CONFIG_SANDBOX) += pci-emul-uclass.o
-obj-$(CONFIG_X86) += pci_x86.o
+obj-$(CONFIG_X86) += pci_x86.o pci_rom.o
else
obj-$(CONFIG_PCI) += pci.o pci_auto_old.o
endif
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 9930ca1faf..22ee62362b 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -16,4 +16,8 @@ config PINCTRL_MT8516
bool "MT8516 SoC pinctrl driver"
select PINCTRL_MTK
+config PINCTRL_MT8518
+ bool "MT8518 SoC pinctrl driver"
+ select PINCTRL_MTK
+
endif
diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
index c4f29088d2..0ab7b1595b 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o
obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o
+obj-$(CONFIG_PINCTRL_MT8518) += pinctrl-mt8518.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8518.c b/drivers/pinctrl/mediatek/pinctrl-mt8518.c
new file mode 100644
index 0000000000..8d2cd948f6
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8518.c
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee <mingming.lee@mediatek.com>
+ */
+
+#include <dm.h>
+
+#include "pinctrl-mtk-common.h"
+
+#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 16, false)
+
+static const struct mtk_pin_field_calc mt8518_pin_mode_range[] = {
+ PIN_FIELD_CALC(0, 119, 0x300, 0x10, 0, 3, 15, false),
+};
+
+static const struct mtk_pin_field_calc mt8518_pin_dir_range[] = {
+ PIN_FIELD(0, 119, 0x0, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8518_pin_di_range[] = {
+ PIN_FIELD(0, 119, 0x200, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8518_pin_do_range[] = {
+ PIN_FIELD(0, 119, 0x100, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8518_pin_ies_range[] = {
+ PIN_FIELD(0, 2, 0x900, 0x10, 0, 1),
+ PIN_FIELD(3, 3, 0x920, 0x10, 9, 1),
+ PIN_FIELD(4, 4, 0x920, 0x10, 8, 1),
+ PIN_FIELD(5, 5, 0x920, 0x10, 7, 1),
+ PIN_FIELD(6, 6, 0x920, 0x10, 6, 1),
+ PIN_FIELD(7, 7, 0x920, 0x10, 10, 1),
+ PIN_FIELD(8, 8, 0x920, 0x10, 1, 1),
+ PIN_FIELD(9, 9, 0x920, 0x10, 0, 1),
+ PIN_FIELD(10, 10, 0x920, 0x10, 5, 1),
+ PIN_FIELD(11, 11, 0x920, 0x10, 4, 1),
+ PIN_FIELD(12, 12, 0x920, 0x10, 3, 1),
+ PIN_FIELD(13, 13, 0x920, 0x10, 2, 1),
+ PIN_FIELD(14, 14, 0x900, 0x10, 1, 1),
+ PIN_FIELD(15, 15, 0x900, 0x10, 2, 1),
+ PIN_FIELD(16, 16, 0x900, 0x10, 3, 1),
+ PIN_FIELD(17, 20, 0x900, 0x10, 4, 1),
+ PIN_FIELD(21, 22, 0x900, 0x10, 5, 1),
+ PIN_FIELD(23, 27, 0x910, 0x10, 15, 1),
+ PIN_FIELD(28, 28, 0x900, 0x10, 6, 1),
+ PIN_FIELD(29, 29, 0x930, 0x10, 2, 1),
+ PIN_FIELD(30, 30, 0x930, 0x10, 1, 1),
+ PIN_FIELD(31, 31, 0x930, 0x10, 6, 1),
+ PIN_FIELD(32, 32, 0x930, 0x10, 5, 1),
+ PIN_FIELD(33, 33, 0x930, 0x10, 4, 1),
+ PIN_FIELD(34, 35, 0x930, 0x10, 3, 1),
+ PIN_FIELD(36, 39, 0x900, 0x10, 7, 1),
+ PIN_FIELD(40, 41, 0x900, 0x10, 8, 1),
+ PIN_FIELD(42, 44, 0x900, 0x10, 9, 1),
+ PIN_FIELD(45, 47, 0x900, 0x10, 10, 1),
+ PIN_FIELD(48, 51, 0x900, 0x10, 11, 1),
+ PIN_FIELD(52, 55, 0x900, 0x10, 12, 1),
+ PIN_FIELD(56, 56, 0x900, 0x10, 13, 1),
+ PIN_FIELD(57, 57, 0x900, 0x10, 14, 1),
+ PIN_FIELD(58, 58, 0x900, 0x10, 15, 1),
+ PIN_FIELD(59, 60, 0x910, 0x10, 0, 1),
+
+ PIN_FIELD(61, 61, 0x910, 0x10, 1, 1),
+ PIN_FIELD(62, 62, 0x910, 0x10, 2, 1),
+ PIN_FIELD(63, 69, 0x910, 0x10, 3, 1),
+ PIN_FIELD(70, 70, 0x910, 0x10, 4, 1),
+ PIN_FIELD(71, 76, 0x910, 0x10, 5, 1),
+ PIN_FIELD(77, 80, 0x910, 0x10, 6, 1),
+ PIN_FIELD(81, 87, 0x910, 0x10, 7, 1),
+ PIN_FIELD(88, 97, 0x910, 0x10, 8, 1),
+ PIN_FIELD(98, 103, 0x910, 0x10, 9, 1),
+ PIN_FIELD(104, 107, 0x910, 0x10, 10, 1),
+ PIN_FIELD(108, 109, 0x910, 0x10, 11, 1),
+ PIN_FIELD(110, 111, 0x910, 0x10, 12, 1),
+ PIN_FIELD(112, 113, 0x910, 0x10, 13, 1),
+ PIN_FIELD(114, 114, 0x920, 0x10, 12, 1),
+ PIN_FIELD(115, 115, 0x920, 0x10, 11, 1),
+ PIN_FIELD(116, 116, 0x930, 0x10, 0, 1),
+ PIN_FIELD(117, 117, 0x920, 0x10, 15, 1),
+ PIN_FIELD(118, 118, 0x920, 0x10, 14, 1),
+ PIN_FIELD(119, 119, 0x920, 0x10, 13, 1),
+};
+
+static const struct mtk_pin_field_calc mt8518_pin_smt_range[] = {
+ PIN_FIELD(0, 2, 0xA00, 0x10, 0, 1),
+ PIN_FIELD(3, 3, 0xA20, 0x10, 9, 1),
+ PIN_FIELD(4, 4, 0xA20, 0x10, 8, 1),
+ PIN_FIELD(5, 5, 0xA20, 0x10, 7, 1),
+ PIN_FIELD(6, 6, 0xA20, 0x10, 6, 1),
+ PIN_FIELD(7, 7, 0xA20, 0x10, 10, 1),
+ PIN_FIELD(8, 8, 0xA20, 0x10, 1, 1),
+ PIN_FIELD(9, 9, 0xA20, 0x10, 0, 1),
+ PIN_FIELD(10, 10, 0xA20, 0x10, 5, 1),
+ PIN_FIELD(11, 11, 0xA20, 0x10, 4, 1),
+ PIN_FIELD(12, 12, 0xA20, 0x10, 3, 1),
+ PIN_FIELD(13, 13, 0xA20, 0x10, 2, 1),
+ PIN_FIELD(14, 14, 0xA00, 0x10, 1, 1),
+ PIN_FIELD(15, 15, 0xA00, 0x10, 2, 1),
+ PIN_FIELD(16, 16, 0xA00, 0x10, 3, 1),
+ PIN_FIELD(17, 20, 0xA00, 0x10, 4, 1),
+ PIN_FIELD(21, 22, 0xA00, 0x10, 5, 1),
+ PIN_FIELD(23, 27, 0xA10, 0x10, 15, 1),
+ PIN_FIELD(28, 28, 0xA00, 0x10, 6, 1),
+ PIN_FIELD(29, 29, 0xA30, 0x10, 2, 1),
+ PIN_FIELD(30, 30, 0xA30, 0x10, 1, 1),
+ PIN_FIELD(31, 31, 0xA30, 0x10, 6, 1),
+ PIN_FIELD(32, 32, 0xA30, 0x10, 5, 1),
+ PIN_FIELD(33, 33, 0xA30, 0x10, 4, 1),
+ PIN_FIELD(34, 35, 0xA30, 0x10, 3, 1),
+ PIN_FIELD(36, 39, 0xA00, 0x10, 7, 1),
+ PIN_FIELD(40, 41, 0xA00, 0x10, 8, 1),
+ PIN_FIELD(42, 44, 0xA00, 0x10, 9, 1),
+ PIN_FIELD(45, 47, 0xA00, 0x10, 10, 1),
+ PIN_FIELD(48, 51, 0xA00, 0x10, 11, 1),
+ PIN_FIELD(52, 55, 0xA00, 0x10, 12, 1),
+ PIN_FIELD(56, 56, 0xA00, 0x10, 13, 1),
+ PIN_FIELD(57, 57, 0xA00, 0x10, 14, 1),
+ PIN_FIELD(58, 58, 0xA00, 0x10, 15, 1),
+ PIN_FIELD(59, 60, 0xA10, 0x10, 0, 1),
+
+ PIN_FIELD(61, 61, 0xA10, 0x10, 1, 1),
+ PIN_FIELD(62, 62, 0xA10, 0x10, 2, 1),
+ PIN_FIELD(63, 69, 0xA10, 0x10, 3, 1),
+ PIN_FIELD(70, 70, 0xA10, 0x10, 4, 1),
+ PIN_FIELD(71, 76, 0xA10, 0x10, 5, 1),
+ PIN_FIELD(77, 80, 0xA10, 0x10, 6, 1),
+ PIN_FIELD(81, 87, 0xA10, 0x10, 7, 1),
+ PIN_FIELD(88, 97, 0xA10, 0x10, 8, 1),
+ PIN_FIELD(98, 103, 0xA10, 0x10, 9, 1),
+ PIN_FIELD(104, 107, 0xA10, 0x10, 10, 1),
+ PIN_FIELD(108, 109, 0xA10, 0x10, 11, 1),
+ PIN_FIELD(110, 111, 0xA10, 0x10, 12, 1),
+ PIN_FIELD(112, 113, 0xA10, 0x10, 13, 1),
+ PIN_FIELD(114, 114, 0xA20, 0x10, 12, 1),
+ PIN_FIELD(115, 115, 0xA20, 0x10, 11, 1),
+ PIN_FIELD(116, 116, 0xA30, 0x10, 0, 1),
+ PIN_FIELD(117, 117, 0xA20, 0x10, 15, 1),
+ PIN_FIELD(118, 118, 0xA20, 0x10, 14, 1),
+ PIN_FIELD(119, 119, 0xA20, 0x10, 13, 1),
+};
+
+static const struct mtk_pin_field_calc mt8518_pin_pullen_range[] = {
+ PIN_FIELD(14, 15, 0x500, 0x10, 14, 1),
+ PIN_FIELD(16, 28, 0x510, 0x10, 0, 1),
+ PIN_FIELD(36, 47, 0x520, 0x10, 4, 1),
+ PIN_FIELD(48, 63, 0x530, 0x10, 0, 1),
+ PIN_FIELD(64, 79, 0x540, 0x10, 0, 1),
+ PIN_FIELD(80, 95, 0x550, 0x10, 0, 1),
+ PIN_FIELD(96, 111, 0x560, 0x10, 0, 1),
+ PIN_FIELD(112, 113, 0x570, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8518_pin_pullsel_range[] = {
+ PIN_FIELD(14, 15, 0x600, 0x10, 14, 1),
+ PIN_FIELD(16, 28, 0x610, 0x10, 0, 1),
+ PIN_FIELD(36, 47, 0x620, 0x10, 4, 1),
+ PIN_FIELD(48, 63, 0x630, 0x10, 0, 1),
+ PIN_FIELD(64, 79, 0x640, 0x10, 0, 1),
+ PIN_FIELD(80, 95, 0x650, 0x10, 0, 1),
+ PIN_FIELD(96, 111, 0x660, 0x10, 0, 1),
+ PIN_FIELD(112, 113, 0x670, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8518_pin_drv_range[] = {
+ PIN_FIELD(0, 2, 0xd70, 0x10, 8, 4),
+ PIN_FIELD(3, 6, 0xd70, 0x10, 0, 4),
+ PIN_FIELD(7, 7, 0xd70, 0x10, 4, 4),
+ PIN_FIELD(8, 8, 0xd60, 0x10, 8, 4),
+ PIN_FIELD(9, 9, 0xd60, 0x10, 12, 4),
+ PIN_FIELD(10, 13, 0xd70, 0x10, 0, 4),
+ PIN_FIELD(14, 14, 0xd50, 0x10, 8, 4),
+ PIN_FIELD(15, 15, 0xd20, 0x10, 4, 4),
+ PIN_FIELD(16, 16, 0xd50, 0x10, 8, 4),
+ PIN_FIELD(17, 20, 0xd20, 0x10, 12, 4),
+ PIN_FIELD(23, 27, 0xd30, 0x10, 8, 4),
+ PIN_FIELD(28, 28, 0xd10, 0x10, 0, 4),
+ PIN_FIELD(29, 29, 0xd40, 0x10, 12, 4),
+ PIN_FIELD(30, 30, 0xd50, 0x10, 0, 4),
+ PIN_FIELD(31, 35, 0xd50, 0x10, 4, 4),
+ PIN_FIELD(36, 41, 0xd00, 0x10, 0, 4),
+ PIN_FIELD(42, 47, 0xd00, 0x10, 4, 4),
+ PIN_FIELD(48, 51, 0xd00, 0x10, 8, 4),
+ PIN_FIELD(52, 55, 0xd10, 0x10, 12, 4),
+ PIN_FIELD(56, 56, 0xdb0, 0x10, 4, 4),
+ PIN_FIELD(57, 58, 0xd00, 0x10, 8, 4),
+ PIN_FIELD(59, 62, 0xd00, 0x10, 12, 4),
+ PIN_FIELD(63, 68, 0xd90, 0x10, 12, 4),
+ PIN_FIELD(69, 69, 0xda0, 0x10, 0, 4),
+ PIN_FIELD(70, 70, 0xda0, 0x10, 12, 4),
+ PIN_FIELD(71, 73, 0xd80, 0x10, 12, 4),
+ PIN_FIELD(74, 76, 0xd90, 0x10, 0, 4),
+ PIN_FIELD(77, 80, 0xd20, 0x10, 0, 4),
+ PIN_FIELD(81, 87, 0xd80, 0x10, 8, 4),
+ PIN_FIELD(88, 97, 0xd30, 0x10, 0, 4),
+ PIN_FIELD(98, 103, 0xd10, 0x10, 4, 4),
+ PIN_FIELD(104, 105, 0xd40, 0x10, 8, 4),
+ PIN_FIELD(106, 107, 0xd10, 0x10, 8, 4),
+ PIN_FIELD(114, 114, 0xd50, 0x10, 12, 4),
+ PIN_FIELD(115, 115, 0xd60, 0x10, 0, 4),
+ PIN_FIELD(116, 119, 0xd60, 0x10, 4, 4),
+};
+
+static const struct mtk_pin_reg_calc mt8518_reg_cals[] = {
+ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8518_pin_mode_range),
+ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8518_pin_dir_range),
+ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8518_pin_di_range),
+ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8518_pin_do_range),
+ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8518_pin_ies_range),
+ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8518_pin_smt_range),
+ [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt8518_pin_pullsel_range),
+ [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt8518_pin_pullen_range),
+ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8518_pin_drv_range),
+};
+
+static const struct mtk_pin_desc mt8518_pins[] = {
+ MTK_PIN(0, "NFI_NCEB0", DRV_GRP4),
+ MTK_PIN(1, "NFI_NREB", DRV_GRP4),
+ MTK_PIN(2, "NFI_NRNB", DRV_GRP4),
+ MTK_PIN(3, "MSDC0_DAT7", DRV_GRP4),
+ MTK_PIN(4, "MSDC0_DAT6", DRV_GRP4),
+ MTK_PIN(5, "MSDC0_DAT5", DRV_GRP4),
+ MTK_PIN(6, "MSDC0_DAT4", DRV_GRP4),
+ MTK_PIN(7, "MSDC0_RSTB", DRV_GRP4),
+ MTK_PIN(8, "MSDC0_CMD", DRV_GRP4),
+ MTK_PIN(9, "MSDC0_CLK", DRV_GRP4),
+ MTK_PIN(10, "MSDC0_DAT3", DRV_GRP4),
+ MTK_PIN(11, "MSDC0_DAT2", DRV_GRP4),
+ MTK_PIN(12, "MSDC0_DAT1", DRV_GRP4),
+ MTK_PIN(13, "MSDC0_DAT0", DRV_GRP4),
+ MTK_PIN(14, "RTC32K_CK", DRV_GRP2),
+ MTK_PIN(15, "WATCHDOG", DRV_GRP2),
+ MTK_PIN(16, "SUSPEND", DRV_GRP2),
+ MTK_PIN(17, "JTMS", DRV_GRP2),
+ MTK_PIN(18, "JTCK", DRV_GRP2),
+ MTK_PIN(19, "JTDI", DRV_GRP2),
+ MTK_PIN(20, "JTDO", DRV_GRP2),
+ MTK_PIN(21, "SDA3", DRV_GRP2),
+ MTK_PIN(22, "SCL3", DRV_GRP2),
+ MTK_PIN(23, "PWRAP_SPI_CLK", DRV_GRP2),
+ MTK_PIN(24, "PWRAP_SPI_CSN", DRV_GRP2),
+ MTK_PIN(25, "PWRAP_SPI_MOSI", DRV_GRP2),
+ MTK_PIN(26, "PWRAP_SPI_MISO", DRV_GRP2),
+ MTK_PIN(27, "PWRAP_INT", DRV_GRP2),
+ MTK_PIN(28, "EINT22", DRV_GRP2),
+ MTK_PIN(29, "MSDC2_CMD", DRV_GRP4),
+ MTK_PIN(30, "MSDC2_CLK", DRV_GRP4),
+ MTK_PIN(31, "MSDC2_DAT0", DRV_GRP4),
+ MTK_PIN(32, "MSDC2_DAT1", DRV_GRP4),
+ MTK_PIN(33, "MSDC2_DAT2", DRV_GRP4),
+ MTK_PIN(34, "MSDC2_DAT3", DRV_GRP4),
+ MTK_PIN(35, "MSDC2_DS", DRV_GRP4),
+ MTK_PIN(36, "EINT0", DRV_GRP0),
+ MTK_PIN(37, "EINT1", DRV_GRP0),
+ MTK_PIN(38, "EINT2", DRV_GRP0),
+ MTK_PIN(39, "EINT3", DRV_GRP0),
+ MTK_PIN(40, "EINT4", DRV_GRP0),
+ MTK_PIN(41, "EINT5", DRV_GRP0),
+ MTK_PIN(42, "EINT6", DRV_GRP0),
+ MTK_PIN(43, "EINT7", DRV_GRP0),
+ MTK_PIN(44, "EINT8", DRV_GRP0),
+ MTK_PIN(45, "EINT9", DRV_GRP0),
+ MTK_PIN(46, "EINT10", DRV_GRP0),
+ MTK_PIN(47, "EINT11", DRV_GRP0),
+ MTK_PIN(48, "EINT12", DRV_GRP0),
+ MTK_PIN(49, "EINT13", DRV_GRP0),
+ MTK_PIN(50, "EINT14", DRV_GRP0),
+ MTK_PIN(51, "EINT15", DRV_GRP0),
+ MTK_PIN(52, "URXD1", DRV_GRP0),
+ MTK_PIN(53, "UTXD1", DRV_GRP0),
+ MTK_PIN(54, "URTS1", DRV_GRP0),
+ MTK_PIN(55, "UCTS1", DRV_GRP0),
+ MTK_PIN(56, "IR", DRV_GRP0),
+ MTK_PIN(57, "EINT16", DRV_GRP0),
+ MTK_PIN(58, "EINT17", DRV_GRP0),
+ MTK_PIN(59, "EINT18", DRV_GRP0),
+ MTK_PIN(60, "EINT19", DRV_GRP0),
+ MTK_PIN(61, "EINT20", DRV_GRP0),
+ MTK_PIN(62, "EINT21", DRV_GRP0),
+ MTK_PIN(63, "I2SO_MCLK", DRV_GRP0),
+ MTK_PIN(64, "I2SO_BCK", DRV_GRP0),
+ MTK_PIN(65, "I2SO_LRCK", DRV_GRP0),
+ MTK_PIN(66, "I2SO_D0", DRV_GRP0),
+ MTK_PIN(67, "I2SO_D1", DRV_GRP0),
+ MTK_PIN(68, "I2SO_D2", DRV_GRP0),
+ MTK_PIN(69, "I2SO_D3", DRV_GRP0),
+ MTK_PIN(70, "SPDIF_IN0", DRV_GRP0),
+ MTK_PIN(71, "DMIC_CLK0", DRV_GRP0),
+ MTK_PIN(72, "DMIC_CLK1", DRV_GRP0),
+ MTK_PIN(73, "DMIC_DAT0", DRV_GRP0),
+ MTK_PIN(74, "DMIC_DAT1", DRV_GRP0),
+ MTK_PIN(75, "DMIC_DAT2", DRV_GRP0),
+ MTK_PIN(76, "DMIC_DAT3", DRV_GRP0),
+ MTK_PIN(77, "TDM_MCLK", DRV_GRP0),
+ MTK_PIN(78, "TDM_BCK", DRV_GRP0),
+ MTK_PIN(79, "TDM_LRCK", DRV_GRP0),
+ MTK_PIN(80, "TDM_DI", DRV_GRP0),
+ MTK_PIN(81, "I2SIN_D0", DRV_GRP0),
+ MTK_PIN(82, "I2SIN_D1", DRV_GRP0),
+ MTK_PIN(83, "I2SIN_D2", DRV_GRP0),
+ MTK_PIN(84, "I2SIN_D3", DRV_GRP0),
+ MTK_PIN(85, "I2SIN_MCLK", DRV_GRP0),
+ MTK_PIN(86, "I2SIN_BCK", DRV_GRP0),
+ MTK_PIN(87, "I2SIN_LRCK", DRV_GRP0),
+ MTK_PIN(88, "SPI1_CS", DRV_GRP0),
+ MTK_PIN(89, "SPI1_CK", DRV_GRP0),
+ MTK_PIN(90, "SPI1_MI", DRV_GRP0),
+ MTK_PIN(91, "SPI1_MO", DRV_GRP0),
+ MTK_PIN(92, "SPI2_CS", DRV_GRP0),
+ MTK_PIN(93, "SPI2_CK", DRV_GRP0),
+ MTK_PIN(94, "SPI2_MI0", DRV_GRP0),
+ MTK_PIN(95, "SPI2_MI1", DRV_GRP0),
+ MTK_PIN(96, "SPI2_MI2", DRV_GRP0),
+ MTK_PIN(97, "SPI2_MI3", DRV_GRP0),
+ MTK_PIN(98, "SW_RESET_DSP", DRV_GRP0),
+ MTK_PIN(99, "GPIO1", DRV_GRP0),
+ MTK_PIN(100, "GPIO2", DRV_GRP0),
+ MTK_PIN(101, "GPIO3", DRV_GRP0),
+ MTK_PIN(102, "GPIO4", DRV_GRP0),
+ MTK_PIN(103, "RTC32K_DSP", DRV_GRP0),
+ MTK_PIN(104, "URXD0", DRV_GRP2),
+ MTK_PIN(105, "UTXD0", DRV_GRP2),
+ MTK_PIN(106, "URXD2", DRV_GRP2),
+ MTK_PIN(107, "UTXD2", DRV_GRP2),
+ MTK_PIN(108, "SDA1", DRV_GRP4),
+ MTK_PIN(109, "SCL1", DRV_GRP4),
+ MTK_PIN(110, "SDA0", DRV_GRP4),
+ MTK_PIN(111, "SCL0", DRV_GRP4),
+ MTK_PIN(112, "SDA2", DRV_GRP4),
+ MTK_PIN(113, "SCL2", DRV_GRP4),
+ MTK_PIN(114, "MSDC1_CMD", DRV_GRP4),
+ MTK_PIN(115, "MSDC1_CLK", DRV_GRP4),
+ MTK_PIN(116, "MSDC1_DAT0", DRV_GRP4),
+ MTK_PIN(117, "MSDC1_DAT1", DRV_GRP4),
+ MTK_PIN(118, "MSDC1_DAT2", DRV_GRP4),
+ MTK_PIN(119, "MSDC1_DAT3", DRV_GRP4),
+};
+
+/* List all groups consisting of these pins dedicated to the enablement of
+ * certain hardware block and the corresponding mode for all of the pins.
+ * The hardware probably has multiple combinations of these pinouts.
+ */
+
+/* UART */
+static int mt8518_uart0_0_rxd_txd_pins[] = { 104, 105, };
+static int mt8518_uart0_0_rxd_txd_funcs[] = { 1, 1, };
+static int mt8518_uart1_0_rxd_txd_pins[] = { 52, 53, };
+static int mt8518_uart1_0_rxd_txd_funcs[] = { 1, 1, };
+static int mt8518_uart2_0_rxd_txd_pins[] = { 106, 107, };
+static int mt8518_uart2_0_rxd_txd_funcs[] = { 1, 1, };
+
+/* Joint those groups owning the same capability in user point of view which
+ * allows that people tend to use through the device tree.
+ */
+static const char *const mt8518_uart_groups[] = { "uart0_0_rxd_txd",
+ "uart1_0_rxd_txd",
+ "uart2_0_rxd_txd", };
+
+/* MMC0 */
+static int mt8518_msdc0_pins[] = { 3, 4, 5, 6, 7, 8, 9, 10, 11,
+ 12, 13, };
+static int mt8518_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
+
+static const struct mtk_group_desc mt8518_groups[] = {
+ PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8518_uart0_0_rxd_txd),
+ PINCTRL_PIN_GROUP("uart1_0_rxd_txd", mt8518_uart1_0_rxd_txd),
+ PINCTRL_PIN_GROUP("uart2_0_rxd_txd", mt8518_uart2_0_rxd_txd),
+
+ PINCTRL_PIN_GROUP("msdc0", mt8518_msdc0),
+};
+
+static const char *const mt8518_msdc_groups[] = { "msdc0" };
+
+static const struct mtk_function_desc mt8518_functions[] = {
+ {"uart", mt8518_uart_groups, ARRAY_SIZE(mt8518_uart_groups)},
+ {"msdc", mt8518_msdc_groups, ARRAY_SIZE(mt8518_msdc_groups)},
+};
+
+static struct mtk_pinctrl_soc mt8518_data = {
+ .name = "mt8518_pinctrl",
+ .reg_cal = mt8518_reg_cals,
+ .pins = mt8518_pins,
+ .npins = ARRAY_SIZE(mt8518_pins),
+ .grps = mt8518_groups,
+ .ngrps = ARRAY_SIZE(mt8518_groups),
+ .funcs = mt8518_functions,
+ .nfuncs = ARRAY_SIZE(mt8518_functions),
+};
+
+static int mtk_pinctrl_mt8518_probe(struct udevice *dev)
+{
+ return mtk_pinctrl_common_probe(dev, &mt8518_data);
+}
+
+static const struct udevice_id mt8518_pctrl_match[] = {
+ { .compatible = "mediatek,mt8518-pinctrl" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(mt8518_pinctrl) = {
+ .name = "mt8518_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = mt8518_pctrl_match,
+ .ops = &mtk_pinctrl_ops,
+ .probe = mtk_pinctrl_mt8518_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_pinctrl_priv),
+};
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index d36a0108ea..ece7d87d4c 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -145,7 +145,7 @@ config SPL_DM_SERIAL
config TPL_DM_SERIAL
bool "Enable Driver Model for serial drivers in TPL"
- depends on DM_SERIAL
+ depends on DM_SERIAL && TPL_DM
default y if TPL && DM_SERIAL
help
Enable driver model for serial in TPL. This replaces
generated by cgit (git 2.34.1) at 2025-01-12 05:57:49 +0000