diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/i2c/Kconfig | 6 | ||||
| -rw-r--r-- | drivers/i2c/Makefile | 1 | ||||
| -rw-r--r-- | drivers/i2c/imx_lpi2c.c | 462 |
3 files changed, 469 insertions, 0 deletions
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 39f62daf5d..8ac7aaf2d2 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -109,6 +109,12 @@ config SYS_I2C_INTEL the I2C API meaning that any I2C operations will immediately fail for now. +config SYS_I2C_IMX_LPI2C + bool "NXP i.MX LPI2C driver" + depends on ARCH_MX7ULP + help + Add support for the NXP i.MX LPI2C driver. + config SYS_I2C_MXC bool "NXP i.MX I2C driver" depends on MX6 diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 7c86198863..446af225bc 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o obj-$(CONFIG_SYS_I2C_INTEL) += intel_i2c.o +obj-$(CONFIG_SYS_I2C_IMX_LPI2C) += imx_lpi2c.o obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o diff --git a/drivers/i2c/imx_lpi2c.c b/drivers/i2c/imx_lpi2c.c new file mode 100644 index 0000000000..f792d4432d --- /dev/null +++ b/drivers/i2c/imx_lpi2c.c @@ -0,0 +1,462 @@ +/* + * Copyright 2016 Freescale Semiconductors, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/imx_lpi2c.h> +#include <asm/arch/sys_proto.h> +#include <dm.h> +#include <fdtdec.h> +#include <i2c.h> + +DECLARE_GLOBAL_DATA_PTR; +#define LPI2C_FIFO_SIZE 4 +#define LPI2C_TIMEOUT_MS 100 + +/* Weak linked function for overridden by some SoC power function */ +int __weak init_i2c_power(unsigned i2c_num) +{ + return 0; +} + +static int imx_lpci2c_check_busy_bus(struct udevice *bus) +{ + struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)dev_get_addr(bus); + lpi2c_status_t result = LPI2C_SUCESS; + u32 status; + + status = readl(®s->msr); + + if ((status & LPI2C_MSR_BBF_MASK) && !(status & LPI2C_MSR_MBF_MASK)) + result = LPI2C_BUSY; + + return result; +} + +static int imx_lpci2c_check_clear_error(struct udevice *bus) +{ + struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)dev_get_addr(bus); + lpi2c_status_t result = LPI2C_SUCESS; + u32 val, status; + + status = readl(®s->msr); + /* errors to check for */ + status &= LPI2C_MSR_NDF_MASK | LPI2C_MSR_ALF_MASK | + LPI2C_MSR_FEF_MASK | LPI2C_MSR_PLTF_MASK; + + if (status) { + if (status & LPI2C_MSR_PLTF_MASK) + result = LPI2C_PIN_LOW_TIMEOUT_ERR; + else if (status & LPI2C_MSR_ALF_MASK) + result = LPI2C_ARB_LOST_ERR; + else if (status & LPI2C_MSR_NDF_MASK) + result = LPI2C_NAK_ERR; + else if (status & LPI2C_MSR_FEF_MASK) + result = LPI2C_FIFO_ERR; + + /* clear status flags */ + writel(0x7f00, ®s->msr); + /* reset fifos */ + val = readl(®s->mcr); + val |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK; + writel(val, ®s->mcr); + } + + return result; +} + +static int bus_i2c_wait_for_tx_ready(struct udevice *bus) +{ + struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)dev_get_addr(bus); + lpi2c_status_t result = LPI2C_SUCESS; + u32 txcount = 0; + ulong start_time = get_timer(0); + + do { + txcount = LPI2C_MFSR_TXCOUNT(readl(®s->mfsr)); + txcount = LPI2C_FIFO_SIZE - txcount; + result = imx_lpci2c_check_clear_error(bus); + if (result) { + debug("i2c: wait for tx ready: result 0x%x\n", result); + return result; + } + if (get_timer(start_time) > LPI2C_TIMEOUT_MS) { + debug("i2c: wait for tx ready: timeout\n"); + return -1; + } + } while (!txcount); + + return result; +} + +static int bus_i2c_send(struct udevice *bus, u8 *txbuf, int len) +{ + struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)dev_get_addr(bus); + lpi2c_status_t result = LPI2C_SUCESS; + + /* empty tx */ + if (!len) + return result; + + while (len--) { + result = bus_i2c_wait_for_tx_ready(bus); + if (result) { + debug("i2c: send wait fot tx ready: %d\n", result); + return result; + } + writel(*txbuf++, ®s->mtdr); + } + + return result; +} + +static int bus_i2c_receive(struct udevice *bus, u8 *rxbuf, int len) +{ + struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)dev_get_addr(bus); + lpi2c_status_t result = LPI2C_SUCESS; + u32 val; + ulong start_time = get_timer(0); + + /* empty read */ + if (!len) + return result; + + result = bus_i2c_wait_for_tx_ready(bus); + if (result) { + debug("i2c: receive wait fot tx ready: %d\n", result); + return result; + } + + /* clear all status flags */ + writel(0x7f00, ®s->msr); + /* send receive command */ + val = LPI2C_MTDR_CMD(0x1) | LPI2C_MTDR_DATA(len - 1); + writel(val, ®s->mtdr); + + while (len--) { + do { + result = imx_lpci2c_check_clear_error(bus); + if (result) { + debug("i2c: receive check clear error: %d\n", result); + return result; + } + if (get_timer(start_time) > LPI2C_TIMEOUT_MS) { + debug("i2c: receive mrdr: timeout\n"); + return -1; + } + val = readl(®s->mrdr); + } while (val & LPI2C_MRDR_RXEMPTY_MASK); + *rxbuf++ = LPI2C_MRDR_DATA(val); + } + + return result; +} + +static int bus_i2c_start(struct udevice *bus, u8 addr, u8 dir) +{ + struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)dev_get_addr(bus); + lpi2c_status_t result = LPI2C_SUCESS; + u32 val; + + result = imx_lpci2c_check_busy_bus(bus); + if (result) { + debug("i2c: start check busy bus: 0x%x\n", result); + return result; + } + /* clear all status flags */ + writel(0x7f00, ®s->msr); + /* turn off auto-stop condition */ + val = readl(®s->mcfgr1) & ~LPI2C_MCFGR1_AUTOSTOP_MASK; + writel(val, ®s->mcfgr1); + /* wait tx fifo ready */ + result = bus_i2c_wait_for_tx_ready(bus); + if (result) { + debug("i2c: start wait for tx ready: 0x%x\n", result); + return result; + } + /* issue start command */ + val = LPI2C_MTDR_CMD(0x4) | (addr << 0x1) | dir; + writel(val, ®s->mtdr); + + return result; +} +static int bus_i2c_stop(struct udevice *bus) +{ + struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)dev_get_addr(bus); + lpi2c_status_t result = LPI2C_SUCESS; + u32 status; + + result = bus_i2c_wait_for_tx_ready(bus); + if (result) { + debug("i2c: stop wait for tx ready: 0x%x\n", result); + return result; + } + + /* send stop command */ + writel(LPI2C_MTDR_CMD(0x2), ®s->mtdr); + + while (result == LPI2C_SUCESS) { + status = readl(®s->msr); + result = imx_lpci2c_check_clear_error(bus); + /* stop detect flag */ + if (status & LPI2C_MSR_SDF_MASK) { + /* clear stop flag */ + status &= LPI2C_MSR_SDF_MASK; + writel(status, ®s->msr); + break; + } + } + + return result; +} + +static int bus_i2c_read(struct udevice *bus, u32 chip, u8 *buf, int len) +{ + lpi2c_status_t result = LPI2C_SUCESS; + + result = bus_i2c_start(bus, chip, 1); + if (result) + return result; + result = bus_i2c_receive(bus, buf, len); + if (result) + return result; + result = bus_i2c_stop(bus); + if (result) + return result; + + return result; +} + +static int bus_i2c_write(struct udevice *bus, u32 chip, u8 *buf, int len) +{ + lpi2c_status_t result = LPI2C_SUCESS; + + result = bus_i2c_start(bus, chip, 0); + if (result) + return result; + result = bus_i2c_send(bus, buf, len); + if (result) + return result; + result = bus_i2c_stop(bus); + if (result) + return result; + + return result; +} + + +static int bus_i2c_set_bus_speed(struct udevice *bus, int speed) +{ + struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)dev_get_addr(bus); + u32 val; + u32 preescale = 0, best_pre = 0, clkhi = 0; + u32 best_clkhi = 0, abs_error = 0, rate; + u32 error = 0xffffffff; + u32 clock_rate; + bool mode; + int i; + + clock_rate = imx_get_i2cclk(bus->seq + 4); + if (!clock_rate) + return -EPERM; + + mode = (readl(®s->mcr) & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT; + /* disable master mode */ + val = readl(®s->mcr) & ~LPI2C_MCR_MEN_MASK; + writel(val | LPI2C_MCR_MEN(0), ®s->mcr); + + for (preescale = 1; (preescale <= 128) && + (error != 0); preescale = 2 * preescale) { + for (clkhi = 1; clkhi < 32; clkhi++) { + if (clkhi == 1) + rate = (clock_rate / preescale) / (1 + 3 + 2 + 2 / preescale); + else + rate = (clock_rate / preescale / (3 * clkhi + 2 + 2 / preescale)); + + abs_error = speed > rate ? speed - rate : rate - speed; + + if (abs_error < error) { + best_pre = preescale; + best_clkhi = clkhi; + error = abs_error; + if (abs_error == 0) + break; + } + } + } + + /* Standard, fast, fast mode plus and ultra-fast transfers. */ + val = LPI2C_MCCR0_CLKHI(best_clkhi); + if (best_clkhi < 2) + val |= LPI2C_MCCR0_CLKLO(3) | LPI2C_MCCR0_SETHOLD(2) | LPI2C_MCCR0_DATAVD(1); + else + val |= LPI2C_MCCR0_CLKLO(2 * best_clkhi) | LPI2C_MCCR0_SETHOLD(best_clkhi) | + LPI2C_MCCR0_DATAVD(best_clkhi / 2); + writel(val, ®s->mccr0); + + for (i = 0; i < 8; i++) { + if (best_pre == (1 << i)) { + best_pre = i; + break; + } + } + + val = readl(®s->mcfgr1) & ~LPI2C_MCFGR1_PRESCALE_MASK; + writel(val | LPI2C_MCFGR1_PRESCALE(best_pre), ®s->mcfgr1); + + if (mode) { + val = readl(®s->mcr) & ~LPI2C_MCR_MEN_MASK; + writel(val | LPI2C_MCR_MEN(1), ®s->mcr); + } + + return 0; +} + +static int bus_i2c_init(struct udevice *bus, int speed) +{ + struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)dev_get_addr(bus); + u32 val; + int ret; + + /* reset peripheral */ + writel(LPI2C_MCR_RST_MASK, ®s->mcr); + writel(0x0, ®s->mcr); + /* Disable Dozen mode */ + writel(LPI2C_MCR_DBGEN(0) | LPI2C_MCR_DOZEN(1), ®s->mcr); + /* host request disable, active high, external pin */ + val = readl(®s->mcfgr0); + val &= (~(LPI2C_MCFGR0_HREN_MASK | LPI2C_MCFGR0_HRPOL_MASK | + LPI2C_MCFGR0_HRSEL_MASK)); + val |= LPI2C_MCFGR0_HRPOL(0x1); + writel(val, ®s->mcfgr0); + /* pincfg and ignore ack */ + val = readl(®s->mcfgr1); + val &= ~(LPI2C_MCFGR1_PINCFG_MASK | LPI2C_MCFGR1_IGNACK_MASK); + val |= LPI2C_MCFGR1_PINCFG(0x0); /* 2 pin open drain */ + val |= LPI2C_MCFGR1_IGNACK(0x0); /* ignore nack */ + writel(val, ®s->mcfgr1); + + ret = bus_i2c_set_bus_speed(bus, speed); + + /* enable lpi2c in master mode */ + val = readl(®s->mcr) & ~LPI2C_MCR_MEN_MASK; + writel(val | LPI2C_MCR_MEN(1), ®s->mcr); + + debug("i2c : controller bus %d, speed %d:\n", bus->seq, speed); + + return ret; +} + +static int imx_lpi2c_probe_chip(struct udevice *bus, u32 chip, + u32 chip_flags) +{ + lpi2c_status_t result = LPI2C_SUCESS; + + result = bus_i2c_start(bus, chip, 0); + if (result) { + bus_i2c_stop(bus); + bus_i2c_init(bus, 100000); + return result; + } + + result = bus_i2c_stop(bus); + if (result) { + bus_i2c_init(bus, 100000); + return -result; + } + + return result; +} + +static int imx_lpi2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) +{ + int ret = 0; + + for (; nmsgs > 0; nmsgs--, msg++) { + debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); + if (msg->flags & I2C_M_RD) + ret = bus_i2c_read(bus, msg->addr, msg->buf, + msg->len); + else { + ret = bus_i2c_write(bus, msg->addr, msg->buf, + msg->len); + if (ret) + break; + } + } + + if (ret) + debug("i2c_write: error sending\n"); + + return ret; +} + +static int imx_lpi2c_set_bus_speed(struct udevice *bus, unsigned int speed) +{ + return bus_i2c_set_bus_speed(bus, speed); +} + +static int imx_lpi2c_probe(struct udevice *bus) +{ + struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus); + fdt_addr_t addr; + int ret; + + i2c_bus->driver_data = dev_get_driver_data(bus); + + addr = dev_get_addr(bus); + if (addr == FDT_ADDR_T_NONE) + return -ENODEV; + + i2c_bus->base = addr; + i2c_bus->index = bus->seq; + i2c_bus->bus = bus; + + /* power up i2c resource */ + ret = init_i2c_power(bus->seq + 4); + if (ret) { + debug("init_i2c_power err = %d\n", ret); + return ret; + } + + /* Enable clk, only i2c4-7 can be handled by A7 core */ + ret = enable_i2c_clk(1, bus->seq + 4); + if (ret < 0) + return ret; + + ret = bus_i2c_init(bus, 100000); + if (ret < 0) + return ret; + + debug("i2c : controller bus %d at %lu , speed %d: ", + bus->seq, i2c_bus->base, + i2c_bus->speed); + + return 0; +} + +static const struct dm_i2c_ops imx_lpi2c_ops = { + .xfer = imx_lpi2c_xfer, + .probe_chip = imx_lpi2c_probe_chip, + .set_bus_speed = imx_lpi2c_set_bus_speed, +}; + +static const struct udevice_id imx_lpi2c_ids[] = { + { .compatible = "fsl,imx7ulp-lpi2c", }, + {} +}; + +U_BOOT_DRIVER(imx_lpi2c) = { + .name = "imx_lpi2c", + .id = UCLASS_I2C, + .of_match = imx_lpi2c_ids, + .probe = imx_lpi2c_probe, + .priv_auto_alloc_size = sizeof(struct imx_lpi2c_bus), + .ops = &imx_lpi2c_ops, +}; |