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-rw-r--r--drivers/dfu/dfu.c3
-rw-r--r--drivers/gpio/Makefile4
-rw-r--r--drivers/gpio/tegra_gpio.c27
-rw-r--r--drivers/serial/ns16550.c2
-rw-r--r--drivers/serial/serial_sh.c2
-rw-r--r--drivers/serial/serial_sh.h5
-rw-r--r--drivers/serial/serial_uniphier.c64
-rw-r--r--drivers/usb/gadget/f_fastboot.c83
-rw-r--r--drivers/usb/host/Kconfig10
-rw-r--r--drivers/usb/host/Makefile1
-rw-r--r--drivers/usb/host/ehci-uniphier.c25
-rw-r--r--drivers/usb/host/xhci-exynos5.c2
-rw-r--r--drivers/usb/host/xhci-uniphier.c85
-rw-r--r--drivers/usb/musb-new/omap2430.c16
14 files changed, 258 insertions, 71 deletions
diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c
index ad0a7e7c25..0560afa9ff 100644
--- a/drivers/dfu/dfu.c
+++ b/drivers/dfu/dfu.c
@@ -55,6 +55,9 @@ int dfu_init_env_entities(char *interface, char *devstr)
char *env_bkp;
int ret;
+#ifdef CONFIG_SET_DFU_ALT_INFO
+ set_dfu_alt_info(interface, devstr);
+#endif
str_env = getenv("dfu_alt_info");
if (!str_env) {
error("\"dfu_alt_info\" env variable not defined!\n");
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index aa11f15423..fe9a3b2396 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -8,6 +8,10 @@
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_DM_GPIO) += gpio-uclass.o
endif
+/* TODO(sjg@chromium.org): Only tegra supports driver model in SPL */
+ifdef CONFIG_TEGRA_GPIO
+obj-$(CONFIG_DM_GPIO) += gpio-uclass.o
+endif
obj-$(CONFIG_AT91_GPIO) += at91_gpio.o
obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o
diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c
index 43928b8812..f870cdbddf 100644
--- a/drivers/gpio/tegra_gpio.c
+++ b/drivers/gpio/tegra_gpio.c
@@ -132,21 +132,6 @@ static void set_level(unsigned gpio, int high)
writel(u, &bank->gpio_out[GPIO_PORT(gpio)]);
}
-/* set GPIO pin 'gpio' as an output, with polarity 'value' */
-int tegra_spl_gpio_direction_output(int gpio, int value)
-{
- /* Configure as a GPIO */
- set_config(gpio, 1);
-
- /* Configure GPIO output value. */
- set_level(gpio, value);
-
- /* Configure GPIO direction as output. */
- set_direction(gpio, 1);
-
- return 0;
-}
-
/*
* Generic_GPIO primitives.
*/
@@ -338,12 +323,19 @@ static int gpio_tegra_bind(struct udevice *parent)
int bank_count;
int bank;
int ret;
- int len;
/* If this is a child device, there is nothing to do here */
if (plat)
return 0;
+ /* TODO(sjg@chromium.org): Remove once SPL supports device tree */
+#ifdef CONFIG_SPL_BUILD
+ ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
+ bank_count = TEGRA_GPIO_BANKS;
+#else
+ {
+ int len;
+
/*
* This driver does not make use of interrupts, other than to figure
* out the number of GPIO banks
@@ -353,6 +345,8 @@ static int gpio_tegra_bind(struct udevice *parent)
bank_count = len / 3 / sizeof(u32);
ctlr = (struct gpio_ctlr *)fdtdec_get_addr(gd->fdt_blob,
parent->of_offset, "reg");
+ }
+#endif
for (bank = 0; bank < bank_count; bank++) {
int port;
@@ -388,4 +382,5 @@ U_BOOT_DRIVER(gpio_tegra) = {
.probe = gpio_tegra_probe,
.priv_auto_alloc_size = sizeof(struct tegra_port_info),
.ops = &gpio_tegra_ops,
+ .flags = DM_FLAG_PRE_RELOC,
};
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index eb00f1ca8a..03beab5a14 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -80,7 +80,7 @@ static inline int serial_in_shift(unsigned char *addr, int shift)
#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN)
return in_be32(addr);
#elif defined(CONFIG_SYS_BIG_ENDIAN)
- return readb(addr + (1 << reg_shift) - 1);
+ return readb(addr + (1 << shift) - 1);
#else
return readb(addr);
#endif
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index 3641c9f834..8693c1ed14 100644
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -69,7 +69,7 @@ sh_serial_setbrg_generic(struct uart_port *port, int clk, int baudrate)
if (port->clk_mode == EXT_CLK) {
unsigned short dl = DL_VALUE(baudrate, clk);
sci_out(port, DL, dl);
- /* Need wait: Clock * 1/dl × 1/16 */
+ /* Need wait: Clock * 1/dl * 1/16 */
udelay((1000000 * dl * 16 / clk) * 1000 + 1);
} else {
sci_out(port, SCBRR, SCBRR_VALUE(baudrate, clk));
diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index 528aa7351d..941e6eda4c 100644
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -227,7 +227,8 @@ struct uart_port {
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
# define SCIF_ORER 0x0001
-# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
+# define SCSCR_INIT(port) (port->clk_mode == EXT_CLK ? 0x32 : 0x30)
+ /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
#else
# error CPU subtype not defined
#endif
@@ -742,7 +743,7 @@ static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
#define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */
-#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) /* Internal Clock */
+#define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */
#else /* Generic SH */
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
#endif
diff --git a/drivers/serial/serial_uniphier.c b/drivers/serial/serial_uniphier.c
index e8a1608b99..a6bd27facf 100644
--- a/drivers/serial/serial_uniphier.c
+++ b/drivers/serial/serial_uniphier.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2012-2014 Panasonic Corporation
+ * Copyright (C) 2012-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
@@ -13,31 +13,25 @@
#include <serial.h>
#include <fdtdec.h>
-#define UART_REG(x) \
- u8 x; \
- u8 postpad_##x[3];
-
/*
* Note: Register map is slightly different from that of 16550.
*/
struct uniphier_serial {
- UART_REG(rbr); /* 0x00 */
- UART_REG(ier); /* 0x04 */
- UART_REG(iir); /* 0x08 */
- UART_REG(fcr); /* 0x0c */
- u8 mcr; /* 0x10 */
- u8 lcr;
- u16 __postpad;
- UART_REG(lsr); /* 0x14 */
- UART_REG(msr); /* 0x18 */
- u32 __none1;
- u32 __none2;
- u16 dlr;
- u16 __postpad2;
+ u32 rx; /* In: Receive buffer */
+#define tx rx /* Out: Transmit buffer */
+ u32 ier; /* Interrupt Enable Register */
+ u32 iir; /* In: Interrupt ID Register */
+ u32 char_fcr; /* Charactor / FIFO Control Register */
+ u32 lcr_mcr; /* Line/Modem Control Register */
+#define LCR_SHIFT 8
+#define LCR_MASK (0xff << (LCR_SHIFT))
+ u32 lsr; /* In: Line Status Register */
+ u32 msr; /* In: Modem Status Register */
+ u32 __rsv0;
+ u32 __rsv1;
+ u32 dlr; /* Divisor Latch Register */
};
-#define thr rbr
-
struct uniphier_serial_private_data {
struct uniphier_serial __iomem *membase;
};
@@ -52,11 +46,9 @@ static int uniphier_serial_setbrg(struct udevice *dev, int baudrate)
const unsigned int mode_x_div = 16;
unsigned int divisor;
- writeb(UART_LCR_WLEN8, &port->lcr);
-
divisor = DIV_ROUND_CLOSEST(plat->uartclk, mode_x_div * baudrate);
- writew(divisor, &port->dlr);
+ writel(divisor, &port->dlr);
return 0;
}
@@ -65,20 +57,20 @@ static int uniphier_serial_getc(struct udevice *dev)
{
struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
- if (!(readb(&port->lsr) & UART_LSR_DR))
+ if (!(readl(&port->lsr) & UART_LSR_DR))
return -EAGAIN;
- return readb(&port->rbr);
+ return readl(&port->rx);
}
static int uniphier_serial_putc(struct udevice *dev, const char c)
{
struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
- if (!(readb(&port->lsr) & UART_LSR_THRE))
+ if (!(readl(&port->lsr) & UART_LSR_THRE))
return -EAGAIN;
- writeb(c, &port->thr);
+ writel(c, &port->tx);
return 0;
}
@@ -88,21 +80,29 @@ static int uniphier_serial_pending(struct udevice *dev, bool input)
struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
if (input)
- return readb(&port->lsr) & UART_LSR_DR;
+ return readl(&port->lsr) & UART_LSR_DR;
else
- return !(readb(&port->lsr) & UART_LSR_THRE);
+ return !(readl(&port->lsr) & UART_LSR_THRE);
}
static int uniphier_serial_probe(struct udevice *dev)
{
+ u32 tmp;
struct uniphier_serial_private_data *priv = dev_get_priv(dev);
struct uniphier_serial_platform_data *plat = dev_get_platdata(dev);
+ struct uniphier_serial __iomem *port;
- priv->membase = map_sysmem(plat->base, sizeof(struct uniphier_serial));
-
- if (!priv->membase)
+ port = map_sysmem(plat->base, sizeof(struct uniphier_serial));
+ if (!port)
return -ENOMEM;
+ priv->membase = port;
+
+ tmp = readl(&port->lcr_mcr);
+ tmp &= ~LCR_MASK;
+ tmp |= UART_LCR_WLEN8 << LCR_SHIFT;
+ writel(tmp, &port->lcr_mcr);
+
return 0;
}
diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c
index 310175acfe..751ec9e010 100644
--- a/drivers/usb/gadget/f_fastboot.c
+++ b/drivers/usb/gadget/f_fastboot.c
@@ -55,6 +55,7 @@ static inline struct f_fastboot *func_to_fastboot(struct usb_function *f)
static struct f_fastboot *fastboot_func;
static unsigned int download_size;
static unsigned int download_bytes;
+static bool is_high_speed;
static struct usb_endpoint_descriptor fs_ep_in = {
.bLength = USB_DT_ENDPOINT_SIZE,
@@ -136,6 +137,7 @@ static int fastboot_bind(struct usb_configuration *c, struct usb_function *f)
int id;
struct usb_gadget *gadget = c->cdev->gadget;
struct f_fastboot *f_fb = func_to_fastboot(f);
+ const char *s;
/* DYNAMIC interface numbers assignments */
id = usb_interface_id(c, f);
@@ -161,6 +163,10 @@ static int fastboot_bind(struct usb_configuration *c, struct usb_function *f)
hs_ep_out.bEndpointAddress = fs_ep_out.bEndpointAddress;
+ s = getenv("serial#");
+ if (s)
+ g_dnl_set_serialnumber((char *)s);
+
return 0;
}
@@ -219,10 +225,13 @@ static int fastboot_set_alt(struct usb_function *f,
__func__, f->name, interface, alt);
/* make sure we don't enable the ep twice */
- if (gadget->speed == USB_SPEED_HIGH)
+ if (gadget->speed == USB_SPEED_HIGH) {
ret = usb_ep_enable(f_fb->out_ep, &hs_ep_out);
- else
+ is_high_speed = true;
+ } else {
ret = usb_ep_enable(f_fb->out_ep, &fs_ep_out);
+ is_high_speed = false;
+ }
if (ret) {
puts("failed to enable out ep\n");
return ret;
@@ -370,13 +379,20 @@ static void cb_getvar(struct usb_ep *ep, struct usb_request *req)
fastboot_tx_write_str(response);
}
-static unsigned int rx_bytes_expected(void)
+static unsigned int rx_bytes_expected(unsigned int maxpacket)
{
int rx_remain = download_size - download_bytes;
+ int rem = 0;
if (rx_remain < 0)
return 0;
if (rx_remain > EP_BUFFER_SIZE)
return EP_BUFFER_SIZE;
+ if (rx_remain < maxpacket) {
+ rx_remain = maxpacket;
+ } else if (rx_remain % maxpacket != 0) {
+ rem = rx_remain % maxpacket;
+ rx_remain = rx_remain + (maxpacket - rem);
+ }
return rx_remain;
}
@@ -388,6 +404,7 @@ static void rx_handler_dl_image(struct usb_ep *ep, struct usb_request *req)
const unsigned char *buffer = req->buf;
unsigned int buffer_size = req->actual;
unsigned int pre_dot_num, now_dot_num;
+ unsigned int max;
if (req->status != 0) {
printf("Bad status: %d\n", req->status);
@@ -425,7 +442,9 @@ static void rx_handler_dl_image(struct usb_ep *ep, struct usb_request *req)
printf("\ndownloading of %d bytes finished\n", download_bytes);
} else {
- req->length = rx_bytes_expected();
+ max = is_high_speed ? hs_ep_out.wMaxPacketSize :
+ fs_ep_out.wMaxPacketSize;
+ req->length = rx_bytes_expected(max);
if (req->length < ep->maxpacket)
req->length = ep->maxpacket;
}
@@ -438,6 +457,7 @@ static void cb_download(struct usb_ep *ep, struct usb_request *req)
{
char *cmd = req->buf;
char response[RESPONSE_LEN];
+ unsigned int max;
strsep(&cmd, ":");
download_size = simple_strtoul(cmd, NULL, 16);
@@ -453,7 +473,9 @@ static void cb_download(struct usb_ep *ep, struct usb_request *req)
} else {
sprintf(response, "DATA%08x", download_size);
req->complete = rx_handler_dl_image;
- req->length = rx_bytes_expected();
+ max = is_high_speed ? hs_ep_out.wMaxPacketSize :
+ fs_ep_out.wMaxPacketSize;
+ req->length = rx_bytes_expected(max);
if (req->length < ep->maxpacket)
req->length = ep->maxpacket;
}
@@ -513,6 +535,50 @@ static void cb_flash(struct usb_ep *ep, struct usb_request *req)
}
#endif
+static void cb_oem(struct usb_ep *ep, struct usb_request *req)
+{
+ char *cmd = req->buf;
+#ifdef CONFIG_FASTBOOT_FLASH
+ if (strncmp("format", cmd + 4, 6) == 0) {
+ char cmdbuf[32];
+ sprintf(cmdbuf, "gpt write mmc %x $partitions",
+ CONFIG_FASTBOOT_FLASH_MMC_DEV);
+ if (run_command(cmdbuf, 0))
+ fastboot_tx_write_str("FAIL");
+ else
+ fastboot_tx_write_str("OKAY");
+ } else
+#endif
+ if (strncmp("unlock", cmd + 4, 8) == 0) {
+ fastboot_tx_write_str("FAILnot implemented");
+ }
+ else {
+ fastboot_tx_write_str("FAILunknown oem command");
+ }
+}
+
+#ifdef CONFIG_FASTBOOT_FLASH
+static void cb_erase(struct usb_ep *ep, struct usb_request *req)
+{
+ char *cmd = req->buf;
+ char response[RESPONSE_LEN];
+
+ strsep(&cmd, ":");
+ if (!cmd) {
+ error("missing partition name");
+ fastboot_tx_write_str("FAILmissing partition name");
+ return;
+ }
+
+ strcpy(response, "FAILno flash device defined");
+
+#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV
+ fb_mmc_erase(cmd, response);
+#endif
+ fastboot_tx_write_str(response);
+}
+#endif
+
struct cmd_dispatch_info {
char *cmd;
void (*cb)(struct usb_ep *ep, struct usb_request *req);
@@ -539,8 +605,15 @@ static const struct cmd_dispatch_info cmd_dispatch_info[] = {
{
.cmd = "flash",
.cb = cb_flash,
+ }, {
+ .cmd = "erase",
+ .cb = cb_erase,
},
#endif
+ {
+ .cmd = "oem",
+ .cb = cb_oem,
+ },
};
static void rx_handler_command(struct usb_ep *ep, struct usb_request *req)
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 30d1457638..24a595fb42 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -17,6 +17,14 @@ config USB_XHCI
if USB_XHCI_HCD
+config USB_XHCI_UNIPHIER
+ bool "Support for Panasonic UniPhier on-chip xHCI USB controller"
+ depends on ARCH_UNIPHIER
+ default y
+ ---help---
+ Enables support for the on-chip xHCI controller on Panasonic
+ UniPhier SoCs.
+
endif
config USB_EHCI_HCD
@@ -47,7 +55,7 @@ if USB_EHCI_HCD
config USB_EHCI_UNIPHIER
bool "Support for Panasonic UniPhier on-chip EHCI USB controller"
- depends on ARCH_UNIPHIER
+ depends on ARCH_UNIPHIER && OF_CONTROL
default y
---help---
Enables support for the on-chip EHCI controller on Panasonic
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 66d6e9a6d2..eb6f34b53c 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -48,6 +48,7 @@ obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
+obj-$(CONFIG_USB_XHCI_UNIPHIER) += xhci-uniphier.o
# designware
obj-$(CONFIG_USB_DWC2) += dwc2.o
diff --git a/drivers/usb/host/ehci-uniphier.c b/drivers/usb/host/ehci-uniphier.c
index 32a4375279..b5ec296918 100644
--- a/drivers/usb/host/ehci-uniphier.c
+++ b/drivers/usb/host/ehci-uniphier.c
@@ -7,12 +7,12 @@
#include <common.h>
#include <linux/err.h>
+#include <asm/io.h>
#include <usb.h>
-#include <asm/arch/ehci-uniphier.h>
+#include <mach/mio-regs.h>
+#include <fdtdec.h>
#include "ehci.h"
-#ifdef CONFIG_OF_CONTROL
-#include <fdtdec.h>
DECLARE_GLOBAL_DATA_PTR;
#define FDT gd->fdt_blob
@@ -35,18 +35,19 @@ static int get_uniphier_ehci_base(int index, struct ehci_hccr **base)
return -ENODEV; /* not found */
}
-#else
-static int get_uniphier_ehci_base(int index, struct ehci_hccr **base)
+
+static void uniphier_ehci_reset(int index, int on)
{
- *base = (struct ehci_hccr *)uniphier_ehci_platdata[index].base;
- return 0;
+ u32 tmp;
+
+ tmp = readl(MIO_USB_RSTCTRL(index));
+ if (on)
+ tmp &= ~MIO_USB_RSTCTRL_XRST;
+ else
+ tmp |= MIO_USB_RSTCTRL_XRST;
+ writel(tmp, MIO_USB_RSTCTRL(index));
}
-#endif
-/*
- * Create the appropriate control structures to manage
- * a new EHCI host controller.
- */
int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr,
struct ehci_hcor **hcor)
{
diff --git a/drivers/usb/host/xhci-exynos5.c b/drivers/usb/host/xhci-exynos5.c
index a77c8bc919..3f86fdca89 100644
--- a/drivers/usb/host/xhci-exynos5.c
+++ b/drivers/usb/host/xhci-exynos5.c
@@ -182,7 +182,7 @@ static void exynos5_usb3_phy_exit(struct exynos_usb3_phy *phy)
set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_DISABLE);
}
-void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
+static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
{
clrsetbits_le32(&dwc3_reg->g_ctl,
DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
diff --git a/drivers/usb/host/xhci-uniphier.c b/drivers/usb/host/xhci-uniphier.c
new file mode 100644
index 0000000000..08b15e0ad1
--- /dev/null
+++ b/drivers/usb/host/xhci-uniphier.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) 2015 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <usb.h>
+#include <fdtdec.h>
+#include "xhci.h"
+
+static int get_uniphier_xhci_base(int index, struct xhci_hccr **base)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ int node_list[2];
+ fdt_addr_t addr;
+ int count;
+
+ count = fdtdec_find_aliases_for_id(gd->fdt_blob, "usb",
+ COMPAT_PANASONIC_XHCI, node_list,
+ ARRAY_SIZE(node_list));
+
+ if (index >= count)
+ return -ENODEV;
+
+ addr = fdtdec_get_addr(gd->fdt_blob, node_list[index], "reg");
+ if (addr == FDT_ADDR_T_NONE)
+ return -ENODEV;
+
+ *base = (struct xhci_hccr *)addr;
+
+ return 0;
+}
+
+#define USB3_RST_CTRL 0x00100040
+#define IOMMU_RST_N (1 << 5)
+#define LINK_RST_N (1 << 4)
+
+static void uniphier_xhci_reset(void __iomem *base, int on)
+{
+ u32 tmp;
+
+ tmp = readl(base + USB3_RST_CTRL);
+
+ if (on)
+ tmp &= ~(IOMMU_RST_N | LINK_RST_N);
+ else
+ tmp |= IOMMU_RST_N | LINK_RST_N;
+
+ writel(tmp, base + USB3_RST_CTRL);
+}
+
+int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
+{
+ int ret;
+ struct xhci_hccr *cr;
+ struct xhci_hcor *or;
+
+ ret = get_uniphier_xhci_base(index, &cr);
+ if (ret < 0)
+ return ret;
+
+ uniphier_xhci_reset(cr, 0);
+
+ or = (void *)cr + HC_LENGTH(xhci_readl(&cr->cr_capbase));
+
+ *hccr = cr;
+ *hcor = or;
+
+ return 0;
+}
+
+void xhci_hcd_stop(int index)
+{
+ int ret;
+ struct xhci_hccr *cr;
+
+ ret = get_uniphier_xhci_base(index, &cr);
+ if (ret < 0)
+ return;
+
+ uniphier_xhci_reset(cr, 1);
+}
diff --git a/drivers/usb/musb-new/omap2430.c b/drivers/usb/musb-new/omap2430.c
index 98f4830912..31a280edba 100644
--- a/drivers/usb/musb-new/omap2430.c
+++ b/drivers/usb/musb-new/omap2430.c
@@ -321,6 +321,7 @@ static int omap2430_musb_init(struct musb *musb)
{
u32 l;
int status = 0;
+ unsigned long int start;
#ifndef __UBOOT__
struct device *dev = musb->controller;
struct omap2430_glue *glue = dev_get_drvdata(dev->parent);
@@ -331,6 +332,21 @@ static int omap2430_musb_init(struct musb *musb)
(struct omap_musb_board_data *)musb->controller;
#endif
+ /* Reset the controller */
+ musb_writel(musb->mregs, OTG_SYSCONFIG, SOFTRST);
+
+ start = get_timer(0);
+
+ while (1) {
+ l = musb_readl(musb->mregs, OTG_SYSCONFIG);
+ if ((l & SOFTRST) == 0)
+ break;
+
+ if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
+ dev_err(musb->controller, "MUSB reset is taking too long\n");
+ return -ENODEV;
+ }
+ }
#ifndef __UBOOT__
/* We require some kind of external transceiver, hooked
generated by cgit (git 2.34.1) at 2024-12-25 01:34:59 +0000