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-rw-r--r--drivers/adc/stm32-adc-core.c3
-rw-r--r--drivers/adc/stm32-adc.c13
-rw-r--r--drivers/clk/clk_stm32mp1.c10
-rw-r--r--drivers/gpio/Kconfig4
-rw-r--r--drivers/gpio/Makefile2
-rw-r--r--drivers/gpio/stm32_gpio.c (renamed from drivers/gpio/stm32f7_gpio.c)8
-rw-r--r--drivers/i2c/stm32f7_i2c.c12
-rw-r--r--drivers/mailbox/Kconfig7
-rw-r--r--drivers/mailbox/Makefile1
-rw-r--r--drivers/mailbox/stm32-ipcc.c167
-rw-r--r--drivers/misc/stm32mp_fuse.c1
-rw-r--r--drivers/mmc/stm32_sdmmc2.c3
-rw-r--r--drivers/mtd/nand/raw/stm32_fmc2_nand.c93
-rw-r--r--drivers/pinctrl/pinctrl_stm32.c36
-rw-r--r--drivers/power/pmic/stpmic1.c11
-rw-r--r--drivers/power/regulator/stm32-vrefbuf.c2
-rw-r--r--drivers/power/regulator/stpmic1.c1
-rw-r--r--drivers/ram/stm32mp1/stm32mp1_ram.c5
-rw-r--r--drivers/serial/serial_stm32.c4
-rw-r--r--drivers/spi/stm32_qspi.c24
-rw-r--r--drivers/spi/stm32_spi.c11
-rw-r--r--drivers/sysreset/sysreset_syscon.c6
22 files changed, 305 insertions, 119 deletions
diff --git a/drivers/adc/stm32-adc-core.c b/drivers/adc/stm32-adc-core.c
index a9aa143bfe..04b6a8a2f5 100644
--- a/drivers/adc/stm32-adc-core.c
+++ b/drivers/adc/stm32-adc-core.c
@@ -60,7 +60,8 @@ static int stm32h7_adc_clk_sel(struct udevice *dev,
{
u32 ckmode, presc;
unsigned long rate;
- int i, div;
+ unsigned int i;
+ int div;
/* stm32h7 bus clock is common for all ADC instances (mandatory) */
if (!clk_valid(&common->bclk)) {
diff --git a/drivers/adc/stm32-adc.c b/drivers/adc/stm32-adc.c
index e108062f2f..029338e4af 100644
--- a/drivers/adc/stm32-adc.c
+++ b/drivers/adc/stm32-adc.c
@@ -163,15 +163,16 @@ static int stm32_adc_chan_of_init(struct udevice *dev)
struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
struct stm32_adc *adc = dev_get_priv(dev);
u32 chans[STM32_ADC_CH_MAX];
- int i, num_channels, ret;
+ unsigned int i, num_channels;
+ int ret;
/* Retrieve single ended channels listed in device tree */
- num_channels = dev_read_size(dev, "st,adc-channels");
- if (num_channels < 0) {
- dev_err(dev, "can't get st,adc-channels: %d\n", num_channels);
- return num_channels;
+ ret = dev_read_size(dev, "st,adc-channels");
+ if (ret < 0) {
+ dev_err(dev, "can't get st,adc-channels: %d\n", ret);
+ return ret;
}
- num_channels /= sizeof(u32);
+ num_channels = ret / sizeof(u32);
if (num_channels > adc->cfg->max_channels) {
dev_err(dev, "too many st,adc-channels: %d\n", num_channels);
diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
index f295e4864b..6ffa05b8fd 100644
--- a/drivers/clk/clk_stm32mp1.c
+++ b/drivers/clk/clk_stm32mp1.c
@@ -805,10 +805,11 @@ static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
const struct stm32mp1_clk_sel *sel = priv->data->sel;
int i;
int s, p;
+ unsigned int idx;
- for (i = 0; i < ARRAY_SIZE(stm32mp1_clks); i++)
- if (stm32mp1_clks[i][0] == id)
- return stm32mp1_clks[i][1];
+ for (idx = 0; idx < ARRAY_SIZE(stm32mp1_clks); idx++)
+ if (stm32mp1_clks[idx][0] == id)
+ return stm32mp1_clks[idx][1];
i = stm32mp1_clk_get_id(priv, id);
if (i < 0)
@@ -1542,8 +1543,7 @@ static void stgen_config(struct stm32mp1_clk_priv *priv)
u32 stgenc, cntfid0;
ulong rate;
- stgenc = (u32)syscon_get_first_range(STM32MP_SYSCON_STGEN);
-
+ stgenc = STM32_STGEN_BASE;
cntfid0 = readl(stgenc + STGENC_CNTFID0);
p = stm32mp1_clk_get_parent(priv, STGEN_K);
rate = stm32mp1_clk_get(priv, p);
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index fa1c99700f..068c6d02d8 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -265,13 +265,13 @@ config PIC32_GPIO
help
Say yes here to support Microchip PIC32 GPIOs.
-config STM32F7_GPIO
+config STM32_GPIO
bool "ST STM32 GPIO driver"
depends on DM_GPIO && (STM32 || ARCH_STM32MP)
default y
help
Device model driver support for STM32 GPIO controller. It should be
- usable on many stm32 families like stm32f4 & stm32H7.
+ usable on many stm32 families like stm32f4/f7/h7 and stm32mp1.
Tested on STM32F7.
config MVEBU_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 7337153e0e..4a8aa0ff6f 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -47,7 +47,7 @@ obj-$(CONFIG_ADI_GPIO2) += adi_gpio2.o
obj-$(CONFIG_TCA642X) += tca642x.o
obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o
obj-$(CONFIG_LPC32XX_GPIO) += lpc32xx_gpio.o
-obj-$(CONFIG_STM32F7_GPIO) += stm32f7_gpio.o
+obj-$(CONFIG_STM32_GPIO) += stm32_gpio.o
obj-$(CONFIG_GPIO_UNIPHIER) += gpio-uniphier.o
obj-$(CONFIG_ZYNQ_GPIO) += zynq_gpio.o
obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o
diff --git a/drivers/gpio/stm32f7_gpio.c b/drivers/gpio/stm32_gpio.c
index 5c9f2fe64d..302a434947 100644
--- a/drivers/gpio/stm32f7_gpio.c
+++ b/drivers/gpio/stm32_gpio.c
@@ -27,7 +27,7 @@
int stm32_offset_to_index(struct udevice *dev, unsigned int offset)
{
struct stm32_gpio_priv *priv = dev_get_priv(dev);
- int idx = 0;
+ unsigned int idx = 0;
int i;
for (i = 0; i < STM32_GPIOS_PER_BANK; i++) {
@@ -210,15 +210,9 @@ static int gpio_stm32_probe(struct udevice *dev)
return 0;
}
-static const struct udevice_id stm32_gpio_ids[] = {
- { .compatible = "st,stm32-gpio" },
- { }
-};
-
U_BOOT_DRIVER(gpio_stm32) = {
.name = "gpio_stm32",
.id = UCLASS_GPIO,
- .of_match = stm32_gpio_ids,
.probe = gpio_stm32_probe,
#ifndef CONFIG_SPL_BUILD
.ops = &gpio_stm32_ops,
diff --git a/drivers/i2c/stm32f7_i2c.c b/drivers/i2c/stm32f7_i2c.c
index 50c4fd0de2..2b18735fea 100644
--- a/drivers/i2c/stm32f7_i2c.c
+++ b/drivers/i2c/stm32f7_i2c.c
@@ -519,13 +519,13 @@ static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup,
/* Compute possible values for PRESC, SCLDEL and SDADEL */
for (p = 0; p < STM32_PRESC_MAX; p++) {
for (l = 0; l < STM32_SCLDEL_MAX; l++) {
- u32 scldel = (l + 1) * (p + 1) * i2cclk;
+ int scldel = (l + 1) * (p + 1) * i2cclk;
if (scldel < scldel_min)
continue;
for (a = 0; a < STM32_SDADEL_MAX; a++) {
- u32 sdadel = (a * (p + 1) + 1) * i2cclk;
+ int sdadel = (a * (p + 1) + 1) * i2cclk;
if (((sdadel >= sdadel_min) &&
(sdadel <= sdadel_max)) &&
@@ -613,10 +613,12 @@ static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup,
if ((tscl >= clk_min) && (tscl <= clk_max) &&
(tscl_h >= i2c_specs[setup->speed].h_min) &&
(i2cclk < tscl_h)) {
- int clk_error = tscl - i2cbus;
+ u32 clk_error;
- if (clk_error < 0)
- clk_error = -clk_error;
+ if (tscl > i2cbus)
+ clk_error = tscl - i2cbus;
+ else
+ clk_error = i2cbus - tscl;
if (clk_error < clk_error_prev) {
clk_error_prev = clk_error;
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index 2836ee4a7b..11bf5522db 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -24,6 +24,13 @@ config TEGRA_HSP
This enables support for the NVIDIA Tegra HSP Hw module, which
implements doorbells, mailboxes, semaphores, and shared interrupts.
+config STM32_IPCC
+ bool "Enable STM32 IPCC controller support"
+ depends on DM_MAILBOX && ARCH_STM32MP
+ help
+ This enables support for the STM32MP IPCC Hw module, which
+ implements doorbells between 2 processors.
+
config K3_SEC_PROXY
bool "Texas Instruments K3 Secure Proxy Driver"
depends on DM_MAILBOX && ARCH_K3
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index cd237698ba..a753cc4e68 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -6,5 +6,6 @@
obj-$(CONFIG_$(SPL_)DM_MAILBOX) += mailbox-uclass.o
obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox.o
obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox-test.o
+obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o
obj-$(CONFIG_TEGRA_HSP) += tegra-hsp.o
obj-$(CONFIG_K3_SEC_PROXY) += k3-sec-proxy.o
diff --git a/drivers/mailbox/stm32-ipcc.c b/drivers/mailbox/stm32-ipcc.c
new file mode 100644
index 0000000000..c3df9678a7
--- /dev/null
+++ b/drivers/mailbox/stm32-ipcc.c
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <mailbox-uclass.h>
+#include <asm/io.h>
+
+/*
+ * IPCC has one set of registers per CPU
+ * IPCC_PROC_OFFST allows to define cpu registers set base address
+ * according to the assigned proc_id.
+ */
+
+#define IPCC_PROC_OFFST 0x010
+
+#define IPCC_XSCR 0x008
+#define IPCC_XTOYSR 0x00c
+
+#define IPCC_HWCFGR 0x3f0
+#define IPCFGR_CHAN_MASK GENMASK(7, 0)
+
+#define RX_BIT_CHAN(chan) BIT(chan)
+#define TX_BIT_SHIFT 16
+#define TX_BIT_CHAN(chan) BIT(TX_BIT_SHIFT + (chan))
+
+#define STM32_MAX_PROCS 2
+
+struct stm32_ipcc {
+ void __iomem *reg_base;
+ void __iomem *reg_proc;
+ u32 proc_id;
+ u32 n_chans;
+};
+
+static int stm32_ipcc_request(struct mbox_chan *chan)
+{
+ struct stm32_ipcc *ipcc = dev_get_priv(chan->dev);
+
+ debug("%s(chan=%p)\n", __func__, chan);
+
+ if (chan->id >= ipcc->n_chans) {
+ debug("%s failed to request channel: %ld\n",
+ __func__, chan->id);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int stm32_ipcc_free(struct mbox_chan *chan)
+{
+ debug("%s(chan=%p)\n", __func__, chan);
+
+ return 0;
+}
+
+static int stm32_ipcc_send(struct mbox_chan *chan, const void *data)
+{
+ struct stm32_ipcc *ipcc = dev_get_priv(chan->dev);
+
+ debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
+
+ if (readl(ipcc->reg_proc + IPCC_XTOYSR) & BIT(chan->id))
+ return -EBUSY;
+
+ /* set channel n occupied */
+ setbits_le32(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan->id));
+
+ return 0;
+}
+
+static int stm32_ipcc_recv(struct mbox_chan *chan, void *data)
+{
+ struct stm32_ipcc *ipcc = dev_get_priv(chan->dev);
+ u32 val;
+ int proc_offset;
+
+ debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
+
+ /* read 'channel occupied' status from other proc */
+ proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST;
+ val = readl(ipcc->reg_proc + proc_offset + IPCC_XTOYSR);
+
+ if (!(val & BIT(chan->id)))
+ return -ENODATA;
+
+ setbits_le32(ipcc->reg_proc + IPCC_XSCR, RX_BIT_CHAN(chan->id));
+
+ return 0;
+}
+
+static int stm32_ipcc_probe(struct udevice *dev)
+{
+ struct stm32_ipcc *ipcc = dev_get_priv(dev);
+ fdt_addr_t addr;
+ const fdt32_t *cell;
+ struct clk clk;
+ int len, ret;
+
+ debug("%s(dev=%p)\n", __func__, dev);
+
+ addr = dev_read_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ ipcc->reg_base = (void __iomem *)addr;
+
+ /* proc_id */
+ cell = dev_read_prop(dev, "st,proc_id", &len);
+ if (len < sizeof(fdt32_t)) {
+ dev_dbg(dev, "Missing st,proc_id\n");
+ return -EINVAL;
+ }
+
+ ipcc->proc_id = fdtdec_get_number(cell, 1);
+
+ if (ipcc->proc_id >= STM32_MAX_PROCS) {
+ dev_err(dev, "Invalid proc_id (%d)\n", ipcc->proc_id);
+ return -EINVAL;
+ }
+
+ ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST;
+
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret)
+ return ret;
+
+ ret = clk_enable(&clk);
+ if (ret)
+ goto clk_free;
+
+ /* get channel number */
+ ipcc->n_chans = readl(ipcc->reg_base + IPCC_HWCFGR);
+ ipcc->n_chans &= IPCFGR_CHAN_MASK;
+
+ return 0;
+
+clk_free:
+ clk_free(&clk);
+
+ return ret;
+}
+
+static const struct udevice_id stm32_ipcc_ids[] = {
+ { .compatible = "st,stm32mp1-ipcc" },
+ { }
+};
+
+struct mbox_ops stm32_ipcc_mbox_ops = {
+ .request = stm32_ipcc_request,
+ .free = stm32_ipcc_free,
+ .send = stm32_ipcc_send,
+ .recv = stm32_ipcc_recv,
+};
+
+U_BOOT_DRIVER(stm32_ipcc) = {
+ .name = "stm32_ipcc",
+ .id = UCLASS_MAILBOX,
+ .of_match = stm32_ipcc_ids,
+ .probe = stm32_ipcc_probe,
+ .priv_auto_alloc_size = sizeof(struct stm32_ipcc),
+ .ops = &stm32_ipcc_mbox_ops,
+};
diff --git a/drivers/misc/stm32mp_fuse.c b/drivers/misc/stm32mp_fuse.c
index 8dc246b0db..801d946b77 100644
--- a/drivers/misc/stm32mp_fuse.c
+++ b/drivers/misc/stm32mp_fuse.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <command.h>
+#include <fuse.h>
#include <misc.h>
#include <errno.h>
#include <dm/device.h>
diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c
index ed31ca126e..867ed569eb 100644
--- a/drivers/mmc/stm32_sdmmc2.c
+++ b/drivers/mmc/stm32_sdmmc2.c
@@ -669,6 +669,7 @@ static int stm32_sdmmc2_probe(struct udevice *dev)
switch (dev_read_u32_default(dev, "bus-width", 1)) {
case 8:
cfg->host_caps |= MMC_MODE_8BIT;
+ /* fall through */
case 4:
cfg->host_caps |= MMC_MODE_4BIT;
break;
@@ -692,7 +693,7 @@ clk_free:
return ret;
}
-int stm32_sdmmc_bind(struct udevice *dev)
+static int stm32_sdmmc_bind(struct udevice *dev)
{
struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c
index 2bb749d7f7..f3179cc21f 100644
--- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c
+++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c
@@ -627,21 +627,16 @@ static void stm32_fmc2_calc_timings(struct nand_chip *chip,
struct stm32_fmc2_timings *tims = &nand->timings;
unsigned long hclk = clk_get_rate(&fmc2->clk);
unsigned long hclkp = FMC2_NSEC_PER_SEC / (hclk / 1000);
- int tar, tclr, thiz, twait, tset_mem, tset_att, thold_mem, thold_att;
-
- tar = hclkp;
- if (tar < sdrt->tAR_min)
- tar = sdrt->tAR_min;
- tims->tar = DIV_ROUND_UP(tar, hclkp) - 1;
- if (tims->tar > FMC2_PCR_TIMING_MASK)
- tims->tar = FMC2_PCR_TIMING_MASK;
-
- tclr = hclkp;
- if (tclr < sdrt->tCLR_min)
- tclr = sdrt->tCLR_min;
- tims->tclr = DIV_ROUND_UP(tclr, hclkp) - 1;
- if (tims->tclr > FMC2_PCR_TIMING_MASK)
- tims->tclr = FMC2_PCR_TIMING_MASK;
+ unsigned long timing, tar, tclr, thiz, twait;
+ unsigned long tset_mem, tset_att, thold_mem, thold_att;
+
+ tar = max_t(unsigned long, hclkp, sdrt->tAR_min);
+ timing = DIV_ROUND_UP(tar, hclkp) - 1;
+ tims->tar = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK);
+
+ tclr = max_t(unsigned long, hclkp, sdrt->tCLR_min);
+ timing = DIV_ROUND_UP(tclr, hclkp) - 1;
+ tims->tclr = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK);
tims->thiz = FMC2_THIZ;
thiz = (tims->thiz + 1) * hclkp;
@@ -651,18 +646,11 @@ static void stm32_fmc2_calc_timings(struct nand_chip *chip,
* tWAIT > tWP
* tWAIT > tREA + tIO
*/
- twait = hclkp;
- if (twait < sdrt->tRP_min)
- twait = sdrt->tRP_min;
- if (twait < sdrt->tWP_min)
- twait = sdrt->tWP_min;
- if (twait < sdrt->tREA_max + FMC2_TIO)
- twait = sdrt->tREA_max + FMC2_TIO;
- tims->twait = DIV_ROUND_UP(twait, hclkp);
- if (tims->twait == 0)
- tims->twait = 1;
- else if (tims->twait > FMC2_PMEM_PATT_TIMING_MASK)
- tims->twait = FMC2_PMEM_PATT_TIMING_MASK;
+ twait = max_t(unsigned long, hclkp, sdrt->tRP_min);
+ twait = max_t(unsigned long, twait, sdrt->tWP_min);
+ twait = max_t(unsigned long, twait, sdrt->tREA_max + FMC2_TIO);
+ timing = DIV_ROUND_UP(twait, hclkp);
+ tims->twait = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
/*
* tSETUP_MEM > tCS - tWAIT
@@ -677,20 +665,15 @@ static void stm32_fmc2_calc_timings(struct nand_chip *chip,
if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
(tset_mem < sdrt->tDS_min - (twait - thiz)))
tset_mem = sdrt->tDS_min - (twait - thiz);
- tims->tset_mem = DIV_ROUND_UP(tset_mem, hclkp);
- if (tims->tset_mem == 0)
- tims->tset_mem = 1;
- else if (tims->tset_mem > FMC2_PMEM_PATT_TIMING_MASK)
- tims->tset_mem = FMC2_PMEM_PATT_TIMING_MASK;
+ timing = DIV_ROUND_UP(tset_mem, hclkp);
+ tims->tset_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
/*
* tHOLD_MEM > tCH
* tHOLD_MEM > tREH - tSETUP_MEM
* tHOLD_MEM > max(tRC, tWC) - (tSETUP_MEM + tWAIT)
*/
- thold_mem = hclkp;
- if (thold_mem < sdrt->tCH_min)
- thold_mem = sdrt->tCH_min;
+ thold_mem = max_t(unsigned long, hclkp, sdrt->tCH_min);
if (sdrt->tREH_min > tset_mem &&
(thold_mem < sdrt->tREH_min - tset_mem))
thold_mem = sdrt->tREH_min - tset_mem;
@@ -700,11 +683,8 @@ static void stm32_fmc2_calc_timings(struct nand_chip *chip,
if ((sdrt->tWC_min > tset_mem + twait) &&
(thold_mem < sdrt->tWC_min - (tset_mem + twait)))
thold_mem = sdrt->tWC_min - (tset_mem + twait);
- tims->thold_mem = DIV_ROUND_UP(thold_mem, hclkp);
- if (tims->thold_mem == 0)
- tims->thold_mem = 1;
- else if (tims->thold_mem > FMC2_PMEM_PATT_TIMING_MASK)
- tims->thold_mem = FMC2_PMEM_PATT_TIMING_MASK;
+ timing = DIV_ROUND_UP(thold_mem, hclkp);
+ tims->thold_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
/*
* tSETUP_ATT > tCS - tWAIT
@@ -726,11 +706,8 @@ static void stm32_fmc2_calc_timings(struct nand_chip *chip,
if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
(tset_att < sdrt->tDS_min - (twait - thiz)))
tset_att = sdrt->tDS_min - (twait - thiz);
- tims->tset_att = DIV_ROUND_UP(tset_att, hclkp);
- if (tims->tset_att == 0)
- tims->tset_att = 1;
- else if (tims->tset_att > FMC2_PMEM_PATT_TIMING_MASK)
- tims->tset_att = FMC2_PMEM_PATT_TIMING_MASK;
+ timing = DIV_ROUND_UP(tset_att, hclkp);
+ tims->tset_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
/*
* tHOLD_ATT > tALH
@@ -745,17 +722,11 @@ static void stm32_fmc2_calc_timings(struct nand_chip *chip,
* tHOLD_ATT > tRC - (tSETUP_ATT + tWAIT)
* tHOLD_ATT > tWC - (tSETUP_ATT + tWAIT)
*/
- thold_att = hclkp;
- if (thold_att < sdrt->tALH_min)
- thold_att = sdrt->tALH_min;
- if (thold_att < sdrt->tCH_min)
- thold_att = sdrt->tCH_min;
- if (thold_att < sdrt->tCLH_min)
- thold_att = sdrt->tCLH_min;
- if (thold_att < sdrt->tCOH_min)
- thold_att = sdrt->tCOH_min;
- if (thold_att < sdrt->tDH_min)
- thold_att = sdrt->tDH_min;
+ thold_att = max_t(unsigned long, hclkp, sdrt->tALH_min);
+ thold_att = max_t(unsigned long, thold_att, sdrt->tCH_min);
+ thold_att = max_t(unsigned long, thold_att, sdrt->tCLH_min);
+ thold_att = max_t(unsigned long, thold_att, sdrt->tCOH_min);
+ thold_att = max_t(unsigned long, thold_att, sdrt->tDH_min);
if ((sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC > tset_mem) &&
(thold_att < sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem))
thold_att = sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem;
@@ -774,11 +745,8 @@ static void stm32_fmc2_calc_timings(struct nand_chip *chip,
if ((sdrt->tWC_min > tset_att + twait) &&
(thold_att < sdrt->tWC_min - (tset_att + twait)))
thold_att = sdrt->tWC_min - (tset_att + twait);
- tims->thold_att = DIV_ROUND_UP(thold_att, hclkp);
- if (tims->thold_att == 0)
- tims->thold_att = 1;
- else if (tims->thold_att > FMC2_PMEM_PATT_TIMING_MASK)
- tims->thold_att = FMC2_PMEM_PATT_TIMING_MASK;
+ timing = DIV_ROUND_UP(thold_att, hclkp);
+ tims->thold_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
}
static int stm32_fmc2_setup_interface(struct mtd_info *mtd, int chipnr,
@@ -932,7 +900,8 @@ static int stm32_fmc2_probe(struct udevice *dev)
struct nand_ecclayout *ecclayout;
struct resource resource;
struct reset_ctl reset;
- int oob_index, chip_cs, mem_region, ret, i;
+ int oob_index, chip_cs, mem_region, ret;
+ unsigned int i;
spin_lock_init(&fmc2->controller.lock);
init_waitqueue_head(&fmc2->controller.wq);
diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c
index 43dbdd9d6a..cdbe463cff 100644
--- a/drivers/pinctrl/pinctrl_stm32.c
+++ b/drivers/pinctrl/pinctrl_stm32.c
@@ -1,5 +1,6 @@
#include <common.h>
#include <dm.h>
+#include <dm/lists.h>
#include <dm/pinctrl.h>
#include <hwspinlock.h>
#include <asm/arch/gpio.h>
@@ -136,7 +137,7 @@ static struct udevice *stm32_pinctrl_get_gpio_dev(struct udevice *dev,
*/
*idx = stm32_offset_to_index(gpio_bank->gpio_dev,
selector - pin_count);
- if (*idx < 0)
+ if (IS_ERR_VALUE(*idx))
return NULL;
return gpio_bank->gpio_dev;
@@ -215,7 +216,7 @@ static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
#endif
-int stm32_pinctrl_probe(struct udevice *dev)
+static int stm32_pinctrl_probe(struct udevice *dev)
{
struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
int ret;
@@ -364,6 +365,35 @@ static int stm32_pinctrl_config(int offset)
return 0;
}
+static int stm32_pinctrl_bind(struct udevice *dev)
+{
+ ofnode node;
+ const char *name;
+ int ret;
+
+ dev_for_each_subnode(node, dev) {
+ debug("%s: bind %s\n", __func__, ofnode_get_name(node));
+
+ ofnode_get_property(node, "gpio-controller", &ret);
+ if (ret < 0)
+ continue;
+ /* Get the name of each gpio node */
+ name = ofnode_get_name(node);
+ if (!name)
+ return -EINVAL;
+
+ /* Bind each gpio node */
+ ret = device_bind_driver_to_node(dev, "gpio_stm32",
+ name, node, NULL);
+ if (ret)
+ return ret;
+
+ debug("%s: bind %s\n", __func__, name);
+ }
+
+ return 0;
+}
+
#if CONFIG_IS_ENABLED(PINCTRL_FULL)
static int stm32_pinctrl_set_state(struct udevice *dev, struct udevice *config)
{
@@ -433,7 +463,7 @@ U_BOOT_DRIVER(pinctrl_stm32) = {
.id = UCLASS_PINCTRL,
.of_match = stm32_pinctrl_ids,
.ops = &stm32_pinctrl_ops,
- .bind = dm_scan_fdt_dev,
+ .bind = stm32_pinctrl_bind,
.probe = stm32_pinctrl_probe,
.priv_auto_alloc_size = sizeof(struct stm32_pinctrl_priv),
};
diff --git a/drivers/power/pmic/stpmic1.c b/drivers/power/pmic/stpmic1.c
index 65296c5fc3..c3381489dd 100644
--- a/drivers/power/pmic/stpmic1.c
+++ b/drivers/power/pmic/stpmic1.c
@@ -221,7 +221,7 @@ static int stpmic1_sysreset_request(struct udevice *dev, enum sysreset_t type)
struct udevice *pmic_dev;
int ret;
- if (type != SYSRESET_POWER)
+ if (type != SYSRESET_POWER && type != SYSRESET_POWER_OFF)
return -EPROTONOSUPPORT;
ret = uclass_get_device_by_driver(UCLASS_PMIC,
@@ -235,8 +235,13 @@ static int stpmic1_sysreset_request(struct udevice *dev, enum sysreset_t type)
if (ret < 0)
return ret;
- ret = pmic_reg_write(pmic_dev, STPMIC1_MAIN_CR,
- ret | STPMIC1_SWOFF | STPMIC1_RREQ_EN);
+ ret |= STPMIC1_SWOFF;
+ ret &= ~STPMIC1_RREQ_EN;
+ /* request Power Cycle */
+ if (type == SYSRESET_POWER)
+ ret |= STPMIC1_RREQ_EN;
+
+ ret = pmic_reg_write(pmic_dev, STPMIC1_MAIN_CR, ret);
if (ret < 0)
return ret;
diff --git a/drivers/power/regulator/stm32-vrefbuf.c b/drivers/power/regulator/stm32-vrefbuf.c
index 0ad6833ed0..645528e84e 100644
--- a/drivers/power/regulator/stm32-vrefbuf.c
+++ b/drivers/power/regulator/stm32-vrefbuf.c
@@ -30,7 +30,7 @@ struct stm32_vrefbuf {
struct udevice *vdda_supply;
};
-static const unsigned int stm32_vrefbuf_voltages[] = {
+static const int stm32_vrefbuf_voltages[] = {
/* Matches resp. VRS = 000b, 001b, 010b, 011b */
2500000, 2048000, 1800000, 1500000,
};
diff --git a/drivers/power/regulator/stpmic1.c b/drivers/power/regulator/stpmic1.c
index 50ef2a21d1..1e3f96f3a0 100644
--- a/drivers/power/regulator/stpmic1.c
+++ b/drivers/power/regulator/stpmic1.c
@@ -422,6 +422,7 @@ static int stpmic1_ldo_set_mode(struct udevice *dev, int mode)
case STPMIC1_LDO_MODE_SINK_SOURCE:
ret &= ~STPMIC1_LDO12356_VOUT_MASK;
ret |= STPMIC1_LDO3_DDR_SEL << STPMIC1_LDO12356_VOUT_SHIFT;
+ /* fallthrough */
case STPMIC1_LDO_MODE_NORMAL:
ret &= ~STPMIC1_LDO3_MODE;
break;
diff --git a/drivers/ram/stm32mp1/stm32mp1_ram.c b/drivers/ram/stm32mp1/stm32mp1_ram.c
index 84e39d093b..a362cf98bf 100644
--- a/drivers/ram/stm32mp1/stm32mp1_ram.c
+++ b/drivers/ram/stm32mp1/stm32mp1_ram.c
@@ -26,7 +26,7 @@ int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed)
unsigned long ddr_clk;
struct clk clk;
int ret;
- int idx;
+ unsigned int idx;
for (idx = 0; idx < ARRAY_SIZE(clkname); idx++) {
ret = clk_get_by_name(priv->dev, clkname[idx], &clk);
@@ -59,7 +59,8 @@ int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed)
static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
{
struct ddr_info *priv = dev_get_priv(dev);
- int ret, idx;
+ int ret;
+ unsigned int idx;
struct clk axidcg;
struct stm32mp1_ddr_config config;
diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c
index cca8b707ac..3ab536a52a 100644
--- a/drivers/serial/serial_stm32.c
+++ b/drivers/serial/serial_stm32.c
@@ -195,9 +195,9 @@ static int stm32_serial_probe(struct udevice *dev)
}
plat->clock_rate = clk_get_rate(&clk);
- if (plat->clock_rate < 0) {
+ if (!plat->clock_rate) {
clk_disable(&clk);
- return plat->clock_rate;
+ return -EINVAL;
};
_stm32_serial_init(plat->base, plat->uart_info);
diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c
index bb1067ff4a..8d612f22d6 100644
--- a/drivers/spi/stm32_qspi.c
+++ b/drivers/spi/stm32_qspi.c
@@ -361,9 +361,9 @@ static int stm32_qspi_probe(struct udevice *bus)
}
priv->clock_rate = clk_get_rate(&clk);
- if (priv->clock_rate < 0) {
+ if (!priv->clock_rate) {
clk_disable(&clk);
- return priv->clock_rate;
+ return -EINVAL;
}
ret = reset_get_by_index(bus, 0, &reset_ctl);
@@ -395,14 +395,15 @@ static int stm32_qspi_claim_bus(struct udevice *dev)
{
struct stm32_qspi_priv *priv = dev_get_priv(dev->parent);
struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ int slave_cs = slave_plat->cs;
- if (slave_plat->cs >= STM32_QSPI_MAX_CHIP)
+ if (slave_cs >= STM32_QSPI_MAX_CHIP)
return -ENODEV;
- if (priv->cs_used != slave_plat->cs) {
- struct stm32_qspi_flash *flash = &priv->flash[slave_plat->cs];
+ if (priv->cs_used != slave_cs) {
+ struct stm32_qspi_flash *flash = &priv->flash[slave_cs];
- priv->cs_used = slave_plat->cs;
+ priv->cs_used = slave_cs;
if (flash->initialized) {
/* Set the configuration: speed + cs */
@@ -444,11 +445,12 @@ static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
int ret;
if (speed > 0) {
- prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
- if (prescaler > 255)
- prescaler = 255;
- else if (prescaler < 0)
- prescaler = 0;
+ prescaler = 0;
+ if (qspi_clk) {
+ prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
+ if (prescaler > 255)
+ prescaler = 255;
+ }
}
csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000);
diff --git a/drivers/spi/stm32_spi.c b/drivers/spi/stm32_spi.c
index 34b217584d..75b6006b45 100644
--- a/drivers/spi/stm32_spi.c
+++ b/drivers/spi/stm32_spi.c
@@ -99,8 +99,8 @@ struct stm32_spi_priv {
unsigned int cur_bpw;
unsigned int cur_hz;
unsigned int cur_xferlen; /* current transfer length in bytes */
- int tx_len; /* number of data to be written in bytes */
- int rx_len; /* number of data to be read in bytes */
+ unsigned int tx_len; /* number of data to be written in bytes */
+ unsigned int rx_len; /* number of data to be read in bytes */
const void *tx_buf; /* data to be written, or NULL */
void *rx_buf; /* data to be read, or NULL */
u32 cur_mode;
@@ -322,7 +322,8 @@ static int stm32_spi_set_fthlv(struct udevice *dev, u32 xfer_len)
static int stm32_spi_set_speed(struct udevice *bus, uint hz)
{
struct stm32_spi_priv *priv = dev_get_priv(bus);
- u32 div, mbrdiv;
+ u32 mbrdiv;
+ long div;
debug("%s: hz=%d\n", __func__, hz);
@@ -341,7 +342,7 @@ static int stm32_spi_set_speed(struct udevice *bus, uint hz)
else
mbrdiv = fls(div) - 1;
- if ((mbrdiv - 1) < 0)
+ if (!mbrdiv)
return -EINVAL;
clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_MBR,
@@ -481,7 +482,7 @@ static int stm32_spi_probe(struct udevice *dev)
struct stm32_spi_priv *priv = dev_get_priv(dev);
unsigned long clk_rate;
int ret;
- int i;
+ unsigned int i;
priv->base = dev_remap_addr(dev);
if (!priv->base)
diff --git a/drivers/sysreset/sysreset_syscon.c b/drivers/sysreset/sysreset_syscon.c
index 1028160247..d0e586f66f 100644
--- a/drivers/sysreset/sysreset_syscon.c
+++ b/drivers/sysreset/sysreset_syscon.c
@@ -23,8 +23,9 @@ struct syscon_reboot_priv {
static int syscon_reboot_request(struct udevice *dev, enum sysreset_t type)
{
struct syscon_reboot_priv *priv = dev_get_priv(dev);
+ ulong driver_data = dev_get_driver_data(dev);
- if (type == SYSRESET_POWER)
+ if (type != driver_data)
return -EPROTONOSUPPORT;
regmap_write(priv->regmap, priv->offset, priv->mask);
@@ -53,7 +54,8 @@ int syscon_reboot_probe(struct udevice *dev)
}
static const struct udevice_id syscon_reboot_ids[] = {
- { .compatible = "syscon-reboot" },
+ { .compatible = "syscon-reboot", .data = SYSRESET_COLD },
+ { .compatible = "syscon-poweroff", .data = SYSRESET_POWER_OFF },
{ /* sentinel */ }
};
generated by cgit (git 2.34.1) at 2024-12-26 23:10:12 +0000