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-rw-r--r--include/asm-blackfin/cplbtab.h38
-rw-r--r--include/asm-blackfin/cpu/bf533_irq.h2
-rw-r--r--include/asm-blackfin/cpu/defBF532.h4
-rw-r--r--include/asm-blackfin/cpu/def_LPBlackfin.h6
-rw-r--r--include/asm-blackfin/page_offset.h2
-rw-r--r--include/asm-blackfin/uaccess.h2
6 files changed, 27 insertions, 27 deletions
diff --git a/include/asm-blackfin/cplbtab.h b/include/asm-blackfin/cplbtab.h
index dc6aee2b94..ab7d989b1a 100644
--- a/include/asm-blackfin/cplbtab.h
+++ b/include/asm-blackfin/cplbtab.h
@@ -3,9 +3,9 @@
*
* Blackfin BF533/2.6 support : LG Soft India
* Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd
- * Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's
+ * Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's
* shouldn't be victimized. cplbmgr.S search logic is corrected
- * to findout the appropriate victim.
+ * to findout the appropriate victim.
* 2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC
* : LG Soft India
*/
@@ -15,12 +15,12 @@
#define __ARCH_BFINNOMMU_CPLBTAB_H
/*************************************************************************
- * ICPLB TABLE
+ * ICPLB TABLE
*************************************************************************/
.data
-/* This table is configurable */
+/* This table is configurable */
.align 4;
@@ -33,7 +33,7 @@
/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
-#define ANOMALY_05000158 0x200
+#define ANOMALY_05000158 0x200
#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
@@ -45,14 +45,14 @@
#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
- #define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
+ #define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
#define SDRAM_EBIU (PAGE_SIZE_1MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
-#endif
+#endif
.global icplb_table
icplb_table:
.byte4 0xFFA00000;
-.byte4 (L1_IMEMORY);
+.byte4 (L1_IMEMORY);
.byte4 0x00000000;
.byte4 (SDRAM_IKERNEL); /*SDRAM_Page1*/
.byte4 0x00400000;
@@ -174,20 +174,20 @@ ipdt_table:
.byte4 0xffffffff; /* end of section - termination*/
/*********************************************************************
- * DCPLB TABLE
+ * DCPLB TABLE
********************************************************************/
.global dcplb_table
dcplb_table:
.byte4 0x00000000;
.byte4 (SDRAM_DKERNEL); /*SDRAM_Page1*/
-.byte4 0x00400000;
+.byte4 0x00400000;
.byte4 (SDRAM_DKERNEL); /*SDRAM_Page1*/
.byte4 0x07C00000;
.byte4 (SDRAM_DKERNEL); /*SDRAM_Page15*/
-.byte4 0x00800000;
+.byte4 0x00800000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page2*/
-.byte4 0x00C00000;
+.byte4 0x00C00000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page3*/
.byte4 0x01000000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page4*/
@@ -197,7 +197,7 @@ dcplb_table:
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page6*/
.byte4 0x01C00000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page7*/
-#ifndef CONFIG_EZKIT
+#ifndef CONFIG_EZKIT
.byte4 0x02000000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page8*/
.byte4 0x02400000;
@@ -217,7 +217,7 @@ dcplb_table:
/**********************************************************************
* PAGE DESCRIPTOR TABLE
- *
+ *
**********************************************************************/
/* Till here we are discussing about the static memory management model.
@@ -225,15 +225,15 @@ dcplb_table:
* descriptors to cover the entire addressable memory than will fit into
* the available on-chip 16 CPLB MMRs. When this happens, the below table
* will be used which will hold all the potentially required CPLB descriptors
- *
+ *
* This is how Page descriptor Table is implemented in uClinux/Blackfin.
- */
+ */
.global dpdt_table
dpdt_table:
#ifdef CONFIG_CPLB_INFO
.byte4 0x00000000;
.byte4 (SDRAM_DKERNEL); /*SDRAM_Page0*/
-.byte4 0x00400000;
+.byte4 0x00400000;
.byte4 (SDRAM_DKERNEL); /*SDRAM_Page1*/
#endif
.byte4 0x00800000;
@@ -271,12 +271,12 @@ dpdt_table:
.byte4 (SDRAM_EBIU); /* Async Memory Bank 2 (Secnd)*/
.byte4 0x20100000;
.byte4 (SDRAM_EBIU); /* Async Memory Bank 1 (Prim B)*/
-.byte4 0x20000000;
+.byte4 0x20000000;
.byte4 (SDRAM_EBIU); /* Async Memory Bank 0 (Prim A)*/
.byte4 0x20300000; /*Fix for Network*/
.byte4 (SDRAM_EBIU); /*Async Memory bank 3*/
-#ifdef CONFIG_STAMP
+#ifdef CONFIG_STAMP
.byte4 0x04000000;
.byte4 (SDRAM_DGENERIC);
.byte4 0x04400000;
diff --git a/include/asm-blackfin/cpu/bf533_irq.h b/include/asm-blackfin/cpu/bf533_irq.h
index 902308a486..9c5230db41 100644
--- a/include/asm-blackfin/cpu/bf533_irq.h
+++ b/include/asm-blackfin/cpu/bf533_irq.h
@@ -81,7 +81,7 @@
/* The ABSTRACT IRQ definitions */
-/* The first seven of the following are fixed,
+/* The first seven of the following are fixed,
* the rest you change if you need to
*/
diff --git a/include/asm-blackfin/cpu/defBF532.h b/include/asm-blackfin/cpu/defBF532.h
index c30d5cd7bc..26a5fe6442 100644
--- a/include/asm-blackfin/cpu/defBF532.h
+++ b/include/asm-blackfin/cpu/defBF532.h
@@ -30,7 +30,7 @@
/* include all Core registers and bit definitions */
#include <asm/cpu/def_LPBlackfin.h>
-/* Helper macros
+/* Helper macros
* usage:
* P0.H = HI(UART_THR);
* P0.L = LO(UART_THR);
@@ -789,7 +789,7 @@
#define ERR_TYP_P0 0x0E
#define ERR_TYP_P1 0x0F
-/*
+/*
* PROGRAMMABLE FLAG MASKS
*/
diff --git a/include/asm-blackfin/cpu/def_LPBlackfin.h b/include/asm-blackfin/cpu/def_LPBlackfin.h
index 11a6504391..9ac78c836a 100644
--- a/include/asm-blackfin/cpu/def_LPBlackfin.h
+++ b/include/asm-blackfin/cpu/def_LPBlackfin.h
@@ -21,7 +21,7 @@
#ifndef _DEF_LPBLACKFIN_H
#define _DEF_LPBLACKFIN_H
-/*
+/*
* #if !defined(__ADSPLPBLACKFIN__)
* #warning def_LPBlackfin.h should only be included for 532 compatible chips.
* #endif
@@ -344,9 +344,9 @@
/* ** Masks */
#define ENDM 0x00000001 /* (doesn't really exist) Enable Data Memory L1 */
#define ENDCPLB 0x00000002 /* Enable DCPLB */
-#define ASRAM_BSRAM 0x00000000
+#define ASRAM_BSRAM 0x00000000
#define ACACHE_BSRAM 0x00000008
-#define ACACHE_BCACHE 0x0000000C
+#define ACACHE_BCACHE 0x0000000C
#define DCBS 0x00000010 /* L1 Data Cache Bank Select */
#define PORT_PREF0 0x00001000 /* DAG0 Port Preference */
#define PORT_PREF1 0x00002000 /* DAG1 Port Preference */
diff --git a/include/asm-blackfin/page_offset.h b/include/asm-blackfin/page_offset.h
index 45e34b5178..262473fc3d 100644
--- a/include/asm-blackfin/page_offset.h
+++ b/include/asm-blackfin/page_offset.h
@@ -22,7 +22,7 @@
* MA 02111-1307 USA
*/
-/*
+/*
* Changes made by Akbar Hussain April 10, 2001
*/
diff --git a/include/asm-blackfin/uaccess.h b/include/asm-blackfin/uaccess.h
index 84b4b4ead7..8578166a37 100644
--- a/include/asm-blackfin/uaccess.h
+++ b/include/asm-blackfin/uaccess.h
@@ -3,7 +3,7 @@
*
* Copyright (c) 2005 blackfin.uclinux.org
*
- * This file is based on
+ * This file is based on
* Based on: include/asm-m68knommu/uaccess.h
* Changes made by Lineo Inc. May 2001
*
generated by cgit (git 2.34.1) at 2024-12-27 04:15:22 +0000