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-rw-r--r--include/configs/IceCube.h1
-rw-r--r--include/configs/MVBLUE.h60
-rw-r--r--include/configs/QS860T.h4
-rw-r--r--include/configs/TOP5200.h160
-rw-r--r--include/configs/TQM855M.h36
-rw-r--r--include/configs/TQM866M.h526
-rw-r--r--include/configs/dbau1x00.h14
7 files changed, 695 insertions, 106 deletions
diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h
index 2f0a875838..194f62faf2 100644
--- a/include/configs/IceCube.h
+++ b/include/configs/IceCube.h
@@ -215,6 +215,7 @@
*/
#define CONFIG_MPC5XXX_FEC 1
#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
+#define CONFIG_PHY_ADDR 0x00
/*
* GPIO configuration
diff --git a/include/configs/MVBLUE.h b/include/configs/MVBLUE.h
index 6965e1cdb7..32f9e91c3b 100644
--- a/include/configs/MVBLUE.h
+++ b/include/configs/MVBLUE.h
@@ -53,7 +53,7 @@
#define ERR_LED(code)
#endif
-#undef DEBUG
+#undef DEBUG
#define CONFIG_MPC824X 1
#define CONFIG_MPC8245 1
@@ -71,14 +71,14 @@
#define CONFIG_BOOT_RETRY_TIME -1
#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds (stop with 's')...\n\0"
-#define CONFIG_AUTOBOOT_STOP_STR "s\0"
+#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds (stop with 's')...\n"
+#define CONFIG_AUTOBOOT_STOP_STR "s"
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_RESET_TO_RETRY 60
#define CONFIG_COMMANDS ( CFG_CMD_ASKENV | CFG_CMD_BOOTD | CFG_CMD_CACHE | CFG_CMD_DHCP | \
- CFG_CMD_ECHO | CFG_CMD_ENV | CFG_CMD_FLASH | CFG_CMD_IMI | \
- CFG_CMD_IRQ | CFG_CMD_NET | CFG_CMD_PCI | CFG_CMD_RUN )
+ CFG_CMD_ECHO | CFG_CMD_ENV | CFG_CMD_FLASH | CFG_CMD_IMI | \
+ CFG_CMD_IRQ | CFG_CMD_NET | CFG_CMD_PCI | CFG_CMD_RUN )
#define CONFIG_BOOTP_MASK ( 0xffffffff )
@@ -103,19 +103,19 @@
#define CONFIG_NFSBOOTCOMMAND "bootp; run nfsargs addcons;bootm"
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "console_nr=0\0" \
- "dhcp_client_id=mvBOX-XP\0" \
- "dhcp_vendor-class-identifier=mvBOX\0" \
- "adminboot=setenv bootargs root=/dev/mtdblock5 rw rootfstype=jffs2;run addcons;bootm ffc00000\0" \
- "flashboot=setenv bootargs root=/dev/mtdblock5 ro rootfstype=jffs2;run addcons;bootm ffc00000\0" \
- "safeboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=cramfs;run addcons;bootm ffc00000\0" \
- "hdboot=setenv bootargs root=/dev/hda1;run addcons;bootm ffc00000\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off\0" \
- "addcons=setenv bootargs $(bootargs) console=ttyS$(console_nr),$(baudrate)N8\0" \
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "console_nr=0\0" \
+ "dhcp_client_id=mvBOX-XP\0" \
+ "dhcp_vendor-class-identifier=mvBOX\0" \
+ "adminboot=setenv bootargs root=/dev/mtdblock5 rw rootfstype=jffs2;run addcons;bootm ffc00000\0" \
+ "flashboot=setenv bootargs root=/dev/mtdblock5 ro rootfstype=jffs2;run addcons;bootm ffc00000\0" \
+ "safeboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=cramfs;run addcons;bootm ffc00000\0" \
+ "hdboot=setenv bootargs root=/dev/hda1;run addcons;bootm ffc00000\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off\0" \
+ "addcons=setenv bootargs $(bootargs) console=ttyS$(console_nr),$(baudrate)N8\0" \
"mv_version=" MV_VERSION "\0" \
- "bootretry=30\0"
+ "bootretry=30\0"
#define CONFIG_OVERWRITE_ETHADDR_ONCE
@@ -124,11 +124,11 @@
*-----------------------------------------------------------------------
*/
-#define CONFIG_PCI
+#define CONFIG_PCI
#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI
#define CONFIG_NET_RETRY_COUNT 5
#define CONFIG_TULIP
@@ -144,8 +144,8 @@
*/
#define CFG_SDRAM_BASE 0x00000000
-#define CFG_FLASH_BASE 0xFFF00000
-#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_FLASH_BASE 0xFFF00000
+#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_RESET_ADDRESS 0xFFF00100
#define CFG_EUMB_ADDR 0xFC000000
@@ -196,7 +196,7 @@
* For the detail description refer to the MPC8240 user's manual.
*/
-#define CONFIG_SYS_CLK_FREQ 33000000
+#define CONFIG_SYS_CLK_FREQ 33000000
#define CFG_HZ 10000
/* Bit-field values for MCCR1. */
@@ -205,17 +205,17 @@
/* Bit-field values for MCCR2. */
#define CFG_TSWAIT 0x5
-#define CFG_REFINT 430
+#define CFG_REFINT 430
/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
-#define CFG_BSTOPRE 121
+#define CFG_BSTOPRE 121
/* Bit-field values for MCCR3. */
#define CFG_REFREC 8
/* Bit-field values for MCCR4. */
-#define CFG_PRETOACT 3
-#define CFG_ACTTOPRE 5
+#define CFG_PRETOACT 3
+#define CFG_ACTTOPRE 5
#define CFG_ACTORW 3
#define CFG_SDMODE_CAS_LAT 3
#define CFG_REGISTERD_TYPE_BUFFER 1
@@ -292,7 +292,7 @@
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#undef CFG_FLASH_PROTECTION
+#undef CFG_FLASH_PROTECTION
#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
#define CFG_MAX_FLASH_SECT 63 /* Max number of sectors per flash */
@@ -300,11 +300,11 @@
#define CFG_FLASH_WRITE_TOUT 1000
-#define CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_IS_IN_FLASH
#define CFG_ENV_OFFSET 0x00010000
-#define CFG_ENV_SIZE 0x00010000
-#define CFG_ENV_SECT_SIZE 0x00010000
+#define CFG_ENV_SIZE 0x00010000
+#define CFG_ENV_SECT_SIZE 0x00010000
/*-----------------------------------------------------------------------
* Cache Configuration
diff --git a/include/configs/QS860T.h b/include/configs/QS860T.h
index 92eccd36aa..8d29a31a05 100644
--- a/include/configs/QS860T.h
+++ b/include/configs/QS860T.h
@@ -47,7 +47,6 @@
#define CONFIG_ENV_OVERWRITE 1 /* allow overwrite MAC address */
-
/*
* High Level Configuration Options
* (easy to change)
@@ -368,7 +367,6 @@ CONFIG_SPI
/* #define CFG_BR5 0xE4000000 */
-
/*
* BR6 and OR6 (Expansion bus)
* Base address = 0xE800_0000 - 0xEBFF_FFFF
@@ -381,7 +379,6 @@ CONFIG_SPI
/* #define CFG_BR6 0xE8000000 */
-
/*
* BR7 and OR7 (Expansion bus)
* Base address = 0xEC00_0000 - 0xEFFF_FFFF
@@ -394,7 +391,6 @@ CONFIG_SPI
/* #define CFG_BR7 0xE8000000 */
-
/*
* Internal Definitions
*
diff --git a/include/configs/TOP5200.h b/include/configs/TOP5200.h
index 21daa2d971..624beed31a 100644
--- a/include/configs/TOP5200.h
+++ b/include/configs/TOP5200.h
@@ -1,16 +1,17 @@
/*
* (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * modified for TOP5200 by Reinhard Meyer, www.emk-elektronik.de
- * TOP5200 differences from IceCube:
- * 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks
- * bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins
- * 1 SDRAM/DDRAM Bank up to 256 MB
- * local VPD I2C Bus is software driven and uses
- * GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL
- * FLASH is located at 0x80000000
- * Internal regs are at 0xfff00000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * modified for TOP5200-series by Reinhard Meyer, www.emk-elektronik.de
+ *
+ * TOP5200 differences from IceCube:
+ * 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks
+ * bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins
+ * 1 SDRAM/DDRAM Bank up to 256 MB
+ * local VPD I2C Bus is software driven and uses
+ * GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL
+ * FLASH is re-located at 0xff000000
+ * Internal regs are at 0xf0000000
* Reset jumps to 0x00000100
*
* See file CREDITS for list of people who contributed to this
@@ -44,7 +45,7 @@
#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */
#define CONFIG_TOP5200 1 /* ... on TOP5200 board - we need this for FEC.C */
-#define CFG_MPC5XXX_CLKIN 33333333 /* ... running at 33MHz */
+#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
@@ -98,17 +99,48 @@
#include <cmd_confdefs.h>
/*
+ * low boot
+ */
+#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
+# define CFG_LOWBOOT 1
+# define CFG_LOWBOOT16 1
+#endif
+
+/*
* Autobooting
*/
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */
-#define CONFIG_BOOTARGS "root=/dev/ram rw"
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath)\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs $(bootargs) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
+ ":$(hostname):$(netdev):off panic=1\0" \
+ "flash_nfs=run nfsargs addip;" \
+ "bootm $(kernel_addr)\0" \
+ "flash_self=run ramargs addip;" \
+ "bootm $(kernel_addr) $(ramdisk_addr)\0" \
+ "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
+ "rootpath=/opt/eldk/ppc_82xx\0" \
+ "bootfile=/tftpboot/MPC5200/uImage\0" \
+ ""
+
+#define CONFIG_BOOTCOMMAND "run flash_self"
/*
* IPB Bus clocking configuration.
*/
#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
-
+
/*
* I2C configuration
*/
@@ -120,21 +152,21 @@
#define CFG_I2C_EEPROM_ADDR_LEN 2
#define CFG_EEPROM_SIZE 0x2000
-
+
#define CONFIG_ENV_OVERWRITE
#define CONFIG_MISC_INIT_R
-
+
#undef CONFIG_HARD_I2C /* I2C with hardware support */
#define CONFIG_SOFT_I2C 1
-
+
#if defined (CONFIG_SOFT_I2C)
# define SDA0 0x40
# define SCL0 0x80
-# define GPIOE0 *((volatile uchar*)(CFG_MBAR+0x0c00))
-# define DDR0 *((volatile uchar*)(CFG_MBAR+0x0c08))
-# define DVO0 *((volatile uchar*)(CFG_MBAR+0x0c0c))
-# define DVI0 *((volatile uchar*)(CFG_MBAR+0x0c20))
-# define ODE0 *((volatile uchar*)(CFG_MBAR+0x0c04))
+# define GPIOE0 *((volatile uchar*)(CFG_MBAR+0x0c00))
+# define DDR0 *((volatile uchar*)(CFG_MBAR+0x0c08))
+# define DVO0 *((volatile uchar*)(CFG_MBAR+0x0c0c))
+# define DVI0 *((volatile uchar*)(CFG_MBAR+0x0c20))
+# define ODE0 *((volatile uchar*)(CFG_MBAR+0x0c04))
# define I2C_INIT {GPIOE0|=(SDA0|SCL0);ODE0|=(SDA0|SCL0);DVO0|=(SDA0|SCL0);DDR0|=(SDA0|SCL0);}
# define I2C_READ ((DVI0&SDA0)?1:0)
# define I2C_SDA(x) {if(x)DVO0|=SDA0;else DVO0&=~SDA0;}
@@ -145,12 +177,12 @@
# define CFG_I2C_SPEED 100000
# define CFG_I2C_SLAVE 0x7F
#endif
-
-#if defined (CONFIG_HARD_I2C)
+
+#if defined (CONFIG_HARD_I2C)
# define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
# define CFG_I2C_SPEED 100000 /* 100 kHz */
# define CFG_I2C_SLAVE 0x7F
-#endif
+#endif
/*
* Flash configuration, expect one 16 Megabyte Bank at most
@@ -158,7 +190,7 @@
#define CFG_FLASH_BASE 0xff000000
#define CFG_FLASH_SIZE 0x01000000
#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
-#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0)
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0)
#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
@@ -167,32 +199,32 @@
#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
-/*
- * DRAM configuration - will be read from VPD later... TODO!
- */
-#if 0
-/* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */
-#define CFG_DRAM_DDR 0
-#define CFG_DRAM_EMODE 0
-#define CFG_DRAM_MODE 0x008D
-#define CFG_DRAM_CONTROL 0x514F0000
-#define CFG_DRAM_CONFIG1 0xC2233A00
-#define CFG_DRAM_CONFIG2 0x88B70004
-#define CFG_DRAM_TAP_DEL 0x08
-#define CFG_DRAM_RAM_SIZE 0x19
-#endif
-#if 1
-/* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */
-#define CFG_DRAM_DDR 0
-#define CFG_DRAM_EMODE 0
-#define CFG_DRAM_MODE 0x00CD
-#define CFG_DRAM_CONTROL 0x514F0000
-#define CFG_DRAM_CONFIG1 0xD2333A00
-#define CFG_DRAM_CONFIG2 0x8AD70004
-#define CFG_DRAM_TAP_DEL 0x08
-#define CFG_DRAM_RAM_SIZE 0x19
-#endif
-
+/*
+ * DRAM configuration - will be read from VPD later... TODO!
+ */
+#if 0
+/* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */
+#define CFG_DRAM_DDR 0
+#define CFG_DRAM_EMODE 0
+#define CFG_DRAM_MODE 0x008D
+#define CFG_DRAM_CONTROL 0x514F0000
+#define CFG_DRAM_CONFIG1 0xC2233A00
+#define CFG_DRAM_CONFIG2 0x88B70004
+#define CFG_DRAM_TAP_DEL 0x08
+#define CFG_DRAM_RAM_SIZE 0x19
+#endif
+#if 1
+/* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */
+#define CFG_DRAM_DDR 0
+#define CFG_DRAM_EMODE 0
+#define CFG_DRAM_MODE 0x00CD
+#define CFG_DRAM_CONTROL 0x514F0000
+#define CFG_DRAM_CONFIG1 0xD2333A00
+#define CFG_DRAM_CONFIG2 0x8AD70004
+#define CFG_DRAM_TAP_DEL 0x08
+#define CFG_DRAM_RAM_SIZE 0x19
+#endif
+
/*
* Environment settings
*/
@@ -201,17 +233,17 @@
#define CFG_ENV_SIZE 0x0700
#define CFG_I2C_EEPROM_ADDR 0x57
-/*
- * VPD settings
- */
+/*
+ * VPD settings
+ */
#define CFG_FACT_OFFSET 0x1800
#define CFG_FACT_SIZE 0x0800
#define CFG_I2C_FACT_ADDR 0x57
-
+
/*
- * Memory map
- *
- * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
+ * Memory map
+ *
+ * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
*/
#define CFG_MBAR 0xf0000000 /* DO NOT CHANGE this */
#define CFG_SDRAM_BASE 0x00000000
@@ -240,12 +272,12 @@
*/
#define CONFIG_MPC5XXX_FEC 1
#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
-#define CONFIG_PHY_ADDR 0x1f
+#define CONFIG_PHY_ADDR 0x1f
#define CONFIG_PHY_TYPE 0x79c874
/*
- * GPIO configuration:
- * PSC1,2,3 predefined as UART
- * PCI disabled
+ * GPIO configuration:
+ * PSC1,2,3 predefined as UART
+ * PCI disabled
* Ethernet 100 with MD
*/
#define CFG_GPS_PORT_CONFIG 0x00058444
diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h
index e926d933c2..cb4a16abdc 100644
--- a/include/configs/TQM855M.h
+++ b/include/configs/TQM855M.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2000-2003
+ * (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -83,6 +83,39 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
+/* enable I2C and select the hardware/software driver */
+#undef CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
+
+#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
+#define CFG_I2C_SLAVE 0xFE
+
+#ifdef CONFIG_SOFT_I2C
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL 0x00000020 /* PB 26 */
+#define PB_SDA 0x00000010 /* PB 27 */
+
+#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
+#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
+#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
+ else immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
+ else immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
+#endif /* CONFIG_SOFT_I2C */
+
+#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */
+#define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
+#if 0
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
+#define CFG_EEPROM_PAGE_WRITE_BITS 5
+#endif
+
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
#define CONFIG_MAC_PARTITION
@@ -93,6 +126,7 @@
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_ASKENV | \
CFG_CMD_DHCP | \
+ CFG_CMD_EEPROM | \
CFG_CMD_IDE | \
CFG_CMD_DATE )
diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h
new file mode 100644
index 0000000000..0219836f5e
--- /dev/null
+++ b/include/configs/TQM866M.h
@@ -0,0 +1,526 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC866 1 /* This is a MPC866 CPU */
+#define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */
+
+#define CFG_8XX_XIN 10000000 /* XXX XXX XXX */
+
+#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
+#undef CONFIG_8xx_CONS_SMC2
+#undef CONFIG_8xx_CONS_NONE
+
+#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
+
+#define CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+
+#define CONFIG_BOARD_TYPES 1 /* support board types */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath)\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs $(bootargs) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
+ ":$(hostname):$(netdev):off panic=1\0" \
+ "flash_nfs=run nfsargs addip;" \
+ "bootm $(kernel_addr)\0" \
+ "flash_self=run ramargs addip;" \
+ "bootm $(kernel_addr) $(ramdisk_addr)\0" \
+ "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
+ "rootpath=/opt/eldk/ppc_8xx\0" \
+ "bootfile=/tftpboot/TQM855M/uImage\0" \
+ "kernel_addr=40080000\0" \
+ "ramdisk_addr=40180000\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+#define CONFIG_STATUS_LED 1 /* Status LED enabled */
+
+#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
+
+/* enable I2C and select the hardware/software driver */
+#undef CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
+
+#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
+#define CFG_I2C_SLAVE 0xFE
+
+#ifdef CONFIG_SOFT_I2C
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL 0x00000020 /* PB 26 */
+#define PB_SDA 0x00000010 /* PB 27 */
+
+#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
+#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
+#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
+ else immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
+ else immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
+#endif /* CONFIG_SOFT_I2C */
+
+#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C256 */
+#define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
+#define CFG_EEPROM_PAGE_WRITE_BITS 4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
+
+#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
+
+#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_IDE | \
+ CFG_CMD_I2C | \
+ CFG_CMD_DATE )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#if 0
+#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
+#endif
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR 0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR CFG_IMMR
+#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
+#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0x40000000
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
+#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
+#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control 11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+ SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration 11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef CONFIG_CAN_DRIVER
+#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else /* we must activate GPL5 in the SIUMCR for CAN */
+#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif /* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control 11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register 11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control 11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR (PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ * set PLL multiplication factor
+ */
+#if defined(CONFIG_133MHz)
+ /* for 133 MHz, we use a 10 MHz clock:
+ * MFN = 0x09, MFD = 0x1D, S = 0, MFI = 13
+ */
+#define CFG_PLPRCR \
+ ( 9 << PLPRCR_MFN_SHIFT | 0x1D << PLPRCR_MFD_SHIFT | \
+ 0 << PLPRCR_S_SHIFT | 0x0D << PLPRCR_MFI_SHIFT | \
+ PLPRCR_TEXPS )
+#elif defined(CONFIG_80MHz) /* for 80 MHz, we use a 16 MHz clock * 5 */
+#define CFG_PLPRCR \
+ ( (5-1)<<PLPRCR_MFI_SHIFT | PLPRCR_TEXPS )
+#else /* up to 66 MHz we use a 1:1 clock */
+#define CFG_PLPRCR ( PLPRCR_SPLSS | PLPRCR_TEXPS )
+#endif /* CONFIG_??MHz */
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register 15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK SCCR_EBDF11
+#if defined(CONFIG_133MHz) /* for 133 MHz, we use a 10 MHz clock * 13 */
+#define CFG_SCCR (/* SCCR_TBS | */ \
+ SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
+ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
+ SCCR_DFALCD00)
+#elif defined(CONFIG_80MHz) /* for 80 MHz, we use a 16 MHz clock * 5 */
+#define CFG_SCCR (/* SCCR_TBS | */ \
+ SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
+ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
+ SCCR_DFALCD00)
+#else /* up to 66 MHz we use a 1:1 clock */
+#define CFG_SCCR (SCCR_TBS | \
+ SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
+ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
+ SCCR_DFALCD00)
+#endif /* CONFIG_??MHz */
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR (0xEC000000)
+#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
+
+#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
+#undef CONFIG_IDE_LED /* LED for ide not supported */
+#undef CONFIG_IDE_RESET /* reset for ide not supported */
+
+#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
+#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
+
+#define CFG_ATA_IDE0_OFFSET 0x0000
+
+#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O */
+#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses */
+#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers */
+#define CFG_ATA_ALT_OFFSET 0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER 0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
+#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
+#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#if defined(CONFIG_133MHz)
+/* 133 MHz CPU - 66 MHz bus: */
+#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
+ OR_SCY_3_CLK | OR_EHTR | OR_BI)
+#elif defined(CONFIG_100MHz)
+/* 100 MHz CPU - 50 MHz bus: */
+#elif defined(CONFIG_80MHz)
+/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
+#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
+ OR_SCY_3_CLK | OR_EHTR | OR_BI)
+#elif defined(CONFIG_66MHz)
+/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
+#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
+ OR_SCY_3_CLK | OR_EHTR | OR_BI)
+#else /* 50 MHz */
+/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
+#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
+ OR_SCY_2_CLK | OR_EHTR | OR_BI)
+#endif /*CONFIG_??MHz */
+
+#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CFG_OR1_REMAP CFG_OR0_REMAP
+#define CFG_OR1_PRELIM CFG_OR0_PRELIM
+#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
+#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
+#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
+#define CFG_OR_TIMING_SDRAM 0x00000A00
+
+#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef CONFIG_CAN_DRIVER
+#define CFG_OR3_PRELIM CFG_OR2_PRELIM
+#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
+#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
+#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
+ BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif /* CONFIG_CAN_DRIVER */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ * gclk CPU clock (not bus clock!)
+ * Trefresh Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096 Rows from SDRAM example configuration
+ * 1000 factor s -> ms
+ * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
+ * 4 Number of refresh cycles per period
+ * 64 Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider = 98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+#if defined(CONFIG_133MHz)
+#define CFG_MAMR_PTA 129
+#elif defined(CONFIG_100MHz)
+#define CFG_MAMR_PTA 98
+#elif defined(CONFIG_80MHz)
+#define CFG_MAMR_PTA 156
+#elif defined(CONFIG_66MHz)
+#define CFG_MAMR_PTA 129
+#else /* 50 MHz */
+#define CFG_MAMR_PTA 98
+#endif /*CONFIG_??MHz */
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
+ * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
+ */
+#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
+#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
+#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
+#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
+ MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
+ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
+ MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
+ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define CONFIG_SCC1_ENET
+#define CONFIG_FEC_ENET
+#define CONFIG_ETHPRIME "SCC ETHERNET"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h
index 6f647f2e8b..d78b727502 100644
--- a/include/configs/dbau1x00.h
+++ b/include/configs/dbau1x00.h
@@ -30,24 +30,24 @@
#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
#define CONFIG_DBAU1X00 1
-#define CONFIG_AU1X00 1 /* alchemy series cpu */
+#define CONFIG_AU1X00 1 /* alchemy series cpu */
#ifdef CONFIG_DBAU1000
/* Also known as Merlot */
-#define CONFIG_AU1000 1
+#define CONFIG_AU1000 1
#else
#ifdef CONFIG_DBAU1100
-#define CONFIG_AU1100 1
+#define CONFIG_AU1100 1
#else
#ifdef CONFIG_DBAU1500
-#define CONFIG_AU1500 1
-#else
+#define CONFIG_AU1500 1
+#else
#error "No valid board set"
#endif
#endif
#endif
-#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */
+#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */
#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
@@ -158,7 +158,7 @@
#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
-/* Offset for data I/O */
+/* Offset for data I/O */
#define CFG_ATA_DATA_OFFSET 8
/* Offset for normal register accesses */
generated by cgit (git 2.34.1) at 2024-12-28 10:52:32 +0000