summaryrefslogtreecommitdiff
path: root/include/configs
diff options
context:
space:
mode:
Diffstat (limited to 'include/configs')
-rw-r--r--include/configs/dlvision-10g.h9
-rw-r--r--include/configs/gdppc440etx.h4
-rw-r--r--include/configs/intip.h4
-rw-r--r--include/configs/io.h13
-rw-r--r--include/configs/io64.h2
-rw-r--r--include/configs/iocon.h9
-rw-r--r--include/configs/neo.h96
7 files changed, 85 insertions, 52 deletions
diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h
index 146819712d..2cd20279be 100644
--- a/include/configs/dlvision-10g.h
+++ b/include/configs/dlvision-10g.h
@@ -34,10 +34,12 @@
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_HOSTNAME dlvsion-10g
-#define CONFIG_IDENT_STRING " dlvision-10g 0.02"
+#define CONFIG_IDENT_STRING " dlvision-10g 0.03"
#include "amcc-common.h"
-#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
#define CONFIG_LAST_STAGE_INIT
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
@@ -80,6 +82,7 @@
* Commands additional to the ones defined in amcc-common.h
*/
#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DTT
#undef CONFIG_CMD_EEPROM
/*
@@ -115,7 +118,7 @@
/* Temp sensor/hwmon/dtt */
#define CONFIG_DTT_LM63 1 /* National LM63 */
-#define CONFIG_DTT_SENSORS { 0x4c, 0x4e } /* Sensor addresses */
+#define CONFIG_DTT_SENSORS { 0x4c, 0x4e, 0x18 } /* Sensor addresses */
#define CONFIG_DTT_PWM_LOOKUPTABLE \
{ { 46, 10 }, { 48, 14 }, { 50, 19 }, { 52, 23 },\
{ 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } }
diff --git a/include/configs/gdppc440etx.h b/include/configs/gdppc440etx.h
index 3c59ff4922..9efbb8e34c 100644
--- a/include/configs/gdppc440etx.h
+++ b/include/configs/gdppc440etx.h
@@ -50,6 +50,10 @@
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f*/
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
+#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
+#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
diff --git a/include/configs/intip.h b/include/configs/intip.h
index 92b65af7c9..33364a843e 100644
--- a/include/configs/intip.h
+++ b/include/configs/intip.h
@@ -37,10 +37,10 @@
#define CONFIG_460EX 1 /* Specific PPC460EX */
#ifdef CONFIG_DEVCONCENTER
#define CONFIG_HOSTNAME devconcenter
-#define CONFIG_IDENT_STRING " devconcenter 0.05"
+#define CONFIG_IDENT_STRING " devconcenter 0.06"
#else
#define CONFIG_HOSTNAME intip
-#define CONFIG_IDENT_STRING " intip 0.05"
+#define CONFIG_IDENT_STRING " intip 0.06"
#endif
#define CONFIG_440 1
#define CONFIG_4xx 1 /* ... PPC4xx family */
diff --git a/include/configs/io.h b/include/configs/io.h
index 9d2a87d22d..03661cce2d 100644
--- a/include/configs/io.h
+++ b/include/configs/io.h
@@ -34,11 +34,13 @@
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_HOSTNAME io
-#define CONFIG_IDENT_STRING " io 0.04"
+#define CONFIG_IDENT_STRING " io 0.05"
#include "amcc-common.h"
-#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
-#define CONFIG_LAST_STAGE_INIT /* call last_stage_init */
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+#define CONFIG_LAST_STAGE_INIT
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
@@ -48,6 +50,10 @@
#define PLLMR0_DEFAULT PLLMR0_266_133_66
#define PLLMR1_DEFAULT PLLMR1_266_133_66
+#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
+#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
@@ -76,6 +82,7 @@
* Commands additional to the ones defined in amcc-common.h
*/
#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DTT
#undef CONFIG_CMD_EEPROM
/*
diff --git a/include/configs/io64.h b/include/configs/io64.h
index 51b2dd1c13..887aaefd39 100644
--- a/include/configs/io64.h
+++ b/include/configs/io64.h
@@ -53,7 +53,7 @@
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_HOSTNAME io64
-#define CONFIG_IDENT_STRING " io64 0.01"
+#define CONFIG_IDENT_STRING " io64 0.02"
#include "amcc-common.h"
#define CONFIG_BOARD_EARLY_INIT_F
diff --git a/include/configs/iocon.h b/include/configs/iocon.h
index 9fcc6430cd..7f8825bed1 100644
--- a/include/configs/iocon.h
+++ b/include/configs/iocon.h
@@ -34,10 +34,11 @@
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_HOSTNAME iocon
-#define CONFIG_IDENT_STRING " iocon 0.03"
+#define CONFIG_IDENT_STRING " iocon 0.04"
#include "amcc-common.h"
-#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_LAST_STAGE_INIT
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
@@ -48,6 +49,10 @@
#define PLLMR0_DEFAULT PLLMR0_266_133_66
#define PLLMR1_DEFAULT PLLMR1_266_133_66
+#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
+#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
diff --git a/include/configs/neo.h b/include/configs/neo.h
index 8de5aaf1ed..38b5becc2e 100644
--- a/include/configs/neo.h
+++ b/include/configs/neo.h
@@ -35,9 +35,13 @@
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_HOSTNAME neo
+#define CONFIG_IDENT_STRING " neo 0.01"
#include "amcc-common.h"
-#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+#define CONFIG_LAST_STAGE_INIT
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
@@ -149,53 +153,53 @@
#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+#define CONFIG_ENV_ADDR 0xFFF00000
+#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR_REDUND 0xFFF20000
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#endif
/*
* PPC405 GPIO Configuration
*/
-#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
-{ \
-/* GPIO Core 0 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO5 TS3 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
-} \
+#define CONFIG_SYS_4xx_GPIO_TABLE { \
+{ \
+/* GPIO Core 0 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
+} \
}
/*
@@ -226,12 +230,22 @@
#define CONFIG_SYS_EBC_PB1CR 0xFB85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
/* Memory Bank 2 (FPGA) initialization */
-#define CONFIG_FPGA_BASE 0x7f100000
+#define CONFIG_SYS_FPGA0_BASE 0x7f100000
#define CONFIG_SYS_EBC_PB2AP 0x92015480
#define CONFIG_SYS_EBC_PB2CR 0x7f11a000 /* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
+
+#define CONFIG_SYS_FPGA_COUNT 1
+
/* Memory Bank 3 (Latches) initialization */
+#define CONFIG_SYS_LATCH_BASE 0x7f200000
#define CONFIG_SYS_EBC_PB3AP 0x92015480
#define CONFIG_SYS_EBC_PB3CR 0x7f21a000 /* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_LATCH0_RESET 0xffff
+#define CONFIG_SYS_LATCH0_BOOT 0xffff
+#define CONFIG_SYS_LATCH1_RESET 0xffbf
+#define CONFIG_SYS_LATCH1_BOOT 0xffff
+
#endif /* __CONFIG_H */
generated by cgit (git 2.34.1) at 2024-12-27 18:35:37 +0000