diff options
Diffstat (limited to 'include/dt-bindings/pinctrl/stm32f746-pinfunc.h')
-rw-r--r-- | include/dt-bindings/pinctrl/stm32f746-pinfunc.h | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/include/dt-bindings/pinctrl/stm32f746-pinfunc.h b/include/dt-bindings/pinctrl/stm32f746-pinfunc.h index 6348c6a830..549323ffe9 100644 --- a/include/dt-bindings/pinctrl/stm32f746-pinfunc.h +++ b/include/dt-bindings/pinctrl/stm32f746-pinfunc.h @@ -154,7 +154,6 @@ #define STM32F746_PA15_FUNC_EVENTOUT 0xf10 #define STM32F746_PA15_FUNC_ANALOG 0xf11 - #define STM32F746_PB0_FUNC_GPIO 0x1000 #define STM32F746_PB0_FUNC_TIM1_CH2N 0x1002 #define STM32F746_PB0_FUNC_TIM3_CH3 0x1003 @@ -188,6 +187,9 @@ #define STM32F746_PB3_FUNC_TIM2_CH2 0x1302 #define STM32F746_PB3_FUNC_SPI1_SCK_I2S1_CK 0x1306 #define STM32F746_PB3_FUNC_SPI3_SCK_I2S3_CK 0x1307 + +#define STM32F769_PB3_FUNC_SDMMC2_D2 0x130b + #define STM32F746_PB3_FUNC_EVENTOUT 0x1310 #define STM32F746_PB3_FUNC_ANALOG 0x1311 @@ -197,6 +199,9 @@ #define STM32F746_PB4_FUNC_SPI1_MISO 0x1406 #define STM32F746_PB4_FUNC_SPI3_MISO 0x1407 #define STM32F746_PB4_FUNC_SPI2_NSS_I2S2_WS 0x1408 + +#define STM32F769_PB4_FUNC_SDMMC2_D3 0x140b + #define STM32F746_PB4_FUNC_EVENTOUT 0x1410 #define STM32F746_PB4_FUNC_ANALOG 0x1411 @@ -505,6 +510,9 @@ #define STM32F746_PD6_FUNC_SPI3_MOSI_I2S3_SD 0x3606 #define STM32F746_PD6_FUNC_SAI1_SD_A 0x3607 #define STM32F746_PD6_FUNC_USART2_RX 0x3608 + +#define STM32F769_PD6_FUNC_SDMMC2_CLK 0x360c + #define STM32F746_PD6_FUNC_FMC_NWAIT 0x360d #define STM32F746_PD6_FUNC_DCMI_D10 0x360e #define STM32F746_PD6_FUNC_LCD_B2 0x360f @@ -514,6 +522,9 @@ #define STM32F746_PD7_FUNC_GPIO 0x3700 #define STM32F746_PD7_FUNC_USART2_CK 0x3708 #define STM32F746_PD7_FUNC_SPDIFRX_IN0 0x3709 + +#define STM32F769_PD7_FUNC_SDMMC2_CMD 0x370c + #define STM32F746_PD7_FUNC_FMC_NE1 0x370d #define STM32F746_PD7_FUNC_EVENTOUT 0x3710 #define STM32F746_PD7_FUNC_ANALOG 0x3711 @@ -893,6 +904,9 @@ #define STM32F746_PG9_FUNC_USART6_RX 0x6909 #define STM32F746_PG9_FUNC_QUADSPI_BK2_IO2 0x690a #define STM32F746_PG9_FUNC_SAI2_FS_B 0x690b + +#define STM32F769_PG9_FUNC_SDMMC2_D0 0x690c + #define STM32F746_PG9_FUNC_FMC_NE2_FMC_NCE 0x690d #define STM32F746_PG9_FUNC_DCMI_VSYNC 0x690e #define STM32F746_PG9_FUNC_EVENTOUT 0x6910 @@ -901,6 +915,9 @@ #define STM32F746_PG10_FUNC_GPIO 0x6a00 #define STM32F746_PG10_FUNC_LCD_G3 0x6a0a #define STM32F746_PG10_FUNC_SAI2_SD_B 0x6a0b + +#define STM32F769_PG10_FUNC_SDMMC2_D1 0x6a0c + #define STM32F746_PG10_FUNC_FMC_NE3 0x6a0d #define STM32F746_PG10_FUNC_DCMI_D2 0x6a0e #define STM32F746_PG10_FUNC_LCD_B2 0x6a0f |