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-rw-r--r--include/configs/advantech_dms-ba16.h2
-rw-r--r--include/configs/gw_ventana.h7
-rw-r--r--include/configs/imx6_logic.h176
-rw-r--r--include/configs/m53evk.h2
-rw-r--r--include/configs/mccmon6.h8
-rw-r--r--include/configs/mx6cuboxi.h2
-rw-r--r--include/configs/mx6slevk.h9
-rw-r--r--include/dt-bindings/clock/imx6sl-clock.h180
8 files changed, 374 insertions, 12 deletions
diff --git a/include/configs/advantech_dms-ba16.h b/include/configs/advantech_dms-ba16.h
index 4886500d6a..30dd9e5966 100644
--- a/include/configs/advantech_dms-ba16.h
+++ b/include/configs/advantech_dms-ba16.h
@@ -261,6 +261,7 @@
#define CONFIG_SYS_FSL_USDHC_NUM 3
/* Framebuffer */
+#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
@@ -271,6 +272,7 @@
#define CONFIG_IPUV3_CLK 260000000
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
+#endif
#define CONFIG_PWM_IMX
#define CONFIG_IMX6_PWM_PER_CLK 66000000
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index 1606f204ce..2b98f535c6 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -100,7 +100,10 @@
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_USDHC_NUM 1
+
+/* eMMC Configs */
+#define CONFIG_SUPPORT_EMMC_BOOT
+#define CONFIG_SUPPORT_EMMC_RPMB
/* Filesystem support */
#define CONFIG_CMD_UBIFS
@@ -152,7 +155,6 @@
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_FEC_MXC_PHYADDR 0
-#define CONFIG_PHYLIB
#define CONFIG_ARP_TIMEOUT 200UL
/* USB Configs */
@@ -235,6 +237,7 @@
#endif
#if defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_SYS_MMC_ENV_DEV 0
+ #define CONFIG_SYS_MMC_ENV_PART 1
#define CONFIG_ENV_OFFSET (709 * SZ_1K)
#define CONFIG_ENV_SIZE (128 * SZ_1K)
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + (128 * SZ_1K))
diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h
new file mode 100644
index 0000000000..175ddc4886
--- /dev/null
+++ b/include/configs/imx6_logic.h
@@ -0,0 +1,176 @@
+/*
+ * Copyright (C) 2017 Logic PD, Inc.
+ *
+ * Configuration settings for the LogicPD i.MX6 SOM.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __IMX6LOGIC_CONFIG_H
+#define __IMX6LOGIC_CONFIG_H
+
+#define CONFIG_MXC_UART_BASE UART1_BASE
+#define CONSOLE_DEV "ttymxc0"
+
+#include <config_distro_defaults.h>
+#include "mx6_common.h"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
+
+#define CONFIG_MXC_UART
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* Dev kit SD card */
+
+/* Ethernet Configs */
+#define CONFIG_MII
+#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_ETHPRIME "FEC"
+#define CONFIG_FEC_MXC_PHYADDR 0
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+
+/* Command definition */
+#define CONFIG_CMD_BMODE
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "image=zImage\0" \
+ "bootm_size=0x10000000\0" \
+ "fdt_addr_r=0x18000000\0" \
+ "fdt_addr=0x18000000\0" \
+ "ramdisk_addr_r=0x13000000\0" \
+ "ramdiskaddr=0x13000000\0" \
+ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "ramdisk_file=rootfs.cpio.uboot\0" \
+ "boot_fdt=try\0" \
+ "ip_dyn=yes\0" \
+ "console=" CONSOLE_DEV "\0" \
+ "mmcdev=1\0" \
+ "mmcpart=1\0" \
+ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+ "nandroot=ubi0:rootfs rootfstype=ubifs\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate}" \
+ " root=${mmcroot} ${mtdparts}\0" \
+ "nandargs=setenv bootargs console=${console},${baudrate}" \
+ " ubi.mtd=fs root=${nandroot} ${mtdparts}\0" \
+ "ramargs=setenv bootargs console=${console},${baudrate}" \
+ " root=/dev/ram rw ${mtdparts}\0" \
+ "loadbootscript=" \
+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...;" \
+ " source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};" \
+ " setenv kernelsize ${filesize}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "loadramdisk=fatload mmc ${mmcdev}:${mmcpart} ${ramdiskaddr}" \
+ " ${ramdisk_file}; setenv ramdisksize ${filesize}\0" \
+ "mmcboot=echo Booting from mmc...; run mmcargs; run loadimage;" \
+ " run loadfdt; bootz ${loadaddr} - ${fdt_addr}\0" \
+ "mmcramboot=run ramargs; run loadimage;" \
+ " run loadfdt; run loadramdisk;" \
+ " bootz ${loadaddr} ${ramdiskaddr} ${fdt_addr}\0" \
+ "nandboot=echo Booting from nand ...; " \
+ " run nandargs;" \
+ " nand read ${loadaddr} kernel ${kernelsize};" \
+ " nand read ${fdt_addr} dtb;" \
+ " bootz ${loadaddr} - ${fdt_addr}\0" \
+ "nandramboot=echo Booting RAMdisk from nand ...; " \
+ " nand read ${ramdiskaddr} fs ${ramdisksize};" \
+ " nand read ${loadaddr} kernel ${kernelsize};" \
+ " nand read ${fdt_addr} dtb;" \
+ " run ramargs;" \
+ " bootz ${loadaddr} ${ramdiskaddr} ${fdt_addr}\0" \
+ "netargs=setenv bootargs console=${console},${baudrate} " \
+ "root=/dev/nfs" \
+ " ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${image}; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0" \
+ "autoboot=mmc dev ${mmcdev};" \
+ "if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "fi; " \
+ "else run netboot; fi"
+#define CONFIG_BOOTCOMMAND \
+ "run autoboot"
+
+#define CONFIG_ARP_TIMEOUT 200UL
+
+#define CONFIG_SYS_MEMTEST_START 0x10000000
+#define CONFIG_SYS_MEMTEST_END 0x10010000
+#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#define CONFIG_ENV_SIZE (8 * 1024)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET 0x400000
+#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
+
+/* NAND stuff */
+#define CONFIG_CMD_NAND_TRIMFFS
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
+
+/* MTD device */
+# define CONFIG_MTD_DEVICE
+# define CONFIG_CMD_MTDPARTS
+# define CONFIG_MTD_PARTITIONS
+# define MTDIDS_DEFAULT "nand0=gpmi-nand"
+# define MTDPARTS_DEFAULT "mtdparts=gpmi-nand:4m(uboot)," \
+ "1m(env),16m(kernel),1m(dtb),-(fs)"
+
+/* DMA stuff, needed for GPMI/MXS NAND support */
+#define CONFIG_APBH_DMA
+#define CONFIG_APBH_DMA_BURST
+#define CONFIG_APBH_DMA_BURST8
+
+/* EEPROM contains serial no, MAC addr and other Logic PD info */
+#define CONFIG_I2C_EEPROM
+
+#endif /* __IMX6LOGIC_CONFIG_H */
diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h
index a70f041b2d..275ecf36ca 100644
--- a/include/configs/m53evk.h
+++ b/include/configs/m53evk.h
@@ -1,5 +1,5 @@
/*
- * DENX M53 configuration
+ * Aries M53 configuration
* Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h
index 7bda977c97..9e5c29f92f 100644
--- a/include/configs/mccmon6.h
+++ b/include/configs/mccmon6.h
@@ -265,6 +265,14 @@
"if tftpboot ${nor_img_addr} ${nor_img_file}; then " \
"run nor_update;" \
"fi\0" \
+ "tftp_nor_dtb="\
+ "echo 'Update mccmon6 NOR DTB via TFTP'; " \
+ "setenv nor_img_file imx6q-mccmon6.dtb; " \
+ "setenv nor_img_size 0x20000; " \
+ "setenv nor_bank_start 0x09980000; " \
+ "if tftpboot ${nor_img_addr} ${nor_img_file}; then " \
+ "run nor_update;" \
+ "fi\0" \
"tftp_nor_img="\
"echo 'Update mccmon6 NOR image via TFTP'; " \
"if tftpboot ${nor_img_addr} ${nor_img_file}; then " \
diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h
index 2782911da3..84fdf656cd 100644
--- a/include/configs/mx6cuboxi.h
+++ b/include/configs/mx6cuboxi.h
@@ -84,7 +84,7 @@
"initrd_high=0xffffffff\0" \
"fdt_high=0xffffffff\0" \
"ip_dyn=yes\0" \
- "console=" CONSOLE_DEV "\0" \
+ "console=" CONSOLE_DEV ",115200\0" \
"bootm_size=0x10000000\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"update_sd_firmware=" \
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index f35d1265b0..2fff7995ea 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -27,19 +27,12 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
/* I2C Configs */
-#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_I2C_SPEED 100000
-/* PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_PFUZE100
-#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
-
#define CONFIG_FEC_MXC
#define CONFIG_MII
#define IMX_FEC_BASE ENET_BASE_ADDR
@@ -143,7 +136,7 @@
/* Environment organization */
#define CONFIG_ENV_SIZE SZ_8K
-#if defined CONFIG_SYS_BOOT_SPINOR
+#if defined CONFIG_SPI_BOOT
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET (768 * 1024)
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
diff --git a/include/dt-bindings/clock/imx6sl-clock.h b/include/dt-bindings/clock/imx6sl-clock.h
new file mode 100644
index 0000000000..e14573e293
--- /dev/null
+++ b/include/dt-bindings/clock/imx6sl-clock.h
@@ -0,0 +1,180 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX6SL_H
+#define __DT_BINDINGS_CLOCK_IMX6SL_H
+
+#define IMX6SL_CLK_DUMMY 0
+#define IMX6SL_CLK_CKIL 1
+#define IMX6SL_CLK_OSC 2
+#define IMX6SL_CLK_PLL1_SYS 3
+#define IMX6SL_CLK_PLL2_BUS 4
+#define IMX6SL_CLK_PLL3_USB_OTG 5
+#define IMX6SL_CLK_PLL4_AUDIO 6
+#define IMX6SL_CLK_PLL5_VIDEO 7
+#define IMX6SL_CLK_PLL6_ENET 8
+#define IMX6SL_CLK_PLL7_USB_HOST 9
+#define IMX6SL_CLK_USBPHY1 10
+#define IMX6SL_CLK_USBPHY2 11
+#define IMX6SL_CLK_USBPHY1_GATE 12
+#define IMX6SL_CLK_USBPHY2_GATE 13
+#define IMX6SL_CLK_PLL4_POST_DIV 14
+#define IMX6SL_CLK_PLL5_POST_DIV 15
+#define IMX6SL_CLK_PLL5_VIDEO_DIV 16
+#define IMX6SL_CLK_ENET_REF 17
+#define IMX6SL_CLK_PLL2_PFD0 18
+#define IMX6SL_CLK_PLL2_PFD1 19
+#define IMX6SL_CLK_PLL2_PFD2 20
+#define IMX6SL_CLK_PLL3_PFD0 21
+#define IMX6SL_CLK_PLL3_PFD1 22
+#define IMX6SL_CLK_PLL3_PFD2 23
+#define IMX6SL_CLK_PLL3_PFD3 24
+#define IMX6SL_CLK_PLL2_198M 25
+#define IMX6SL_CLK_PLL3_120M 26
+#define IMX6SL_CLK_PLL3_80M 27
+#define IMX6SL_CLK_PLL3_60M 28
+#define IMX6SL_CLK_STEP 29
+#define IMX6SL_CLK_PLL1_SW 30
+#define IMX6SL_CLK_OCRAM_ALT_SEL 31
+#define IMX6SL_CLK_OCRAM_SEL 32
+#define IMX6SL_CLK_PRE_PERIPH2_SEL 33
+#define IMX6SL_CLK_PRE_PERIPH_SEL 34
+#define IMX6SL_CLK_PERIPH2_CLK2_SEL 35
+#define IMX6SL_CLK_PERIPH_CLK2_SEL 36
+#define IMX6SL_CLK_CSI_SEL 37
+#define IMX6SL_CLK_LCDIF_AXI_SEL 38
+#define IMX6SL_CLK_USDHC1_SEL 39
+#define IMX6SL_CLK_USDHC2_SEL 40
+#define IMX6SL_CLK_USDHC3_SEL 41
+#define IMX6SL_CLK_USDHC4_SEL 42
+#define IMX6SL_CLK_SSI1_SEL 43
+#define IMX6SL_CLK_SSI2_SEL 44
+#define IMX6SL_CLK_SSI3_SEL 45
+#define IMX6SL_CLK_PERCLK_SEL 46
+#define IMX6SL_CLK_PXP_AXI_SEL 47
+#define IMX6SL_CLK_EPDC_AXI_SEL 48
+#define IMX6SL_CLK_GPU2D_OVG_SEL 49
+#define IMX6SL_CLK_GPU2D_SEL 50
+#define IMX6SL_CLK_LCDIF_PIX_SEL 51
+#define IMX6SL_CLK_EPDC_PIX_SEL 52
+#define IMX6SL_CLK_SPDIF0_SEL 53
+#define IMX6SL_CLK_SPDIF1_SEL 54
+#define IMX6SL_CLK_EXTERN_AUDIO_SEL 55
+#define IMX6SL_CLK_ECSPI_SEL 56
+#define IMX6SL_CLK_UART_SEL 57
+#define IMX6SL_CLK_PERIPH 58
+#define IMX6SL_CLK_PERIPH2 59
+#define IMX6SL_CLK_OCRAM_PODF 60
+#define IMX6SL_CLK_PERIPH_CLK2_PODF 61
+#define IMX6SL_CLK_PERIPH2_CLK2_PODF 62
+#define IMX6SL_CLK_IPG 63
+#define IMX6SL_CLK_CSI_PODF 64
+#define IMX6SL_CLK_LCDIF_AXI_PODF 65
+#define IMX6SL_CLK_USDHC1_PODF 66
+#define IMX6SL_CLK_USDHC2_PODF 67
+#define IMX6SL_CLK_USDHC3_PODF 68
+#define IMX6SL_CLK_USDHC4_PODF 69
+#define IMX6SL_CLK_SSI1_PRED 70
+#define IMX6SL_CLK_SSI1_PODF 71
+#define IMX6SL_CLK_SSI2_PRED 72
+#define IMX6SL_CLK_SSI2_PODF 73
+#define IMX6SL_CLK_SSI3_PRED 74
+#define IMX6SL_CLK_SSI3_PODF 75
+#define IMX6SL_CLK_PERCLK 76
+#define IMX6SL_CLK_PXP_AXI_PODF 77
+#define IMX6SL_CLK_EPDC_AXI_PODF 78
+#define IMX6SL_CLK_GPU2D_OVG_PODF 79
+#define IMX6SL_CLK_GPU2D_PODF 80
+#define IMX6SL_CLK_LCDIF_PIX_PRED 81
+#define IMX6SL_CLK_EPDC_PIX_PRED 82
+#define IMX6SL_CLK_LCDIF_PIX_PODF 83
+#define IMX6SL_CLK_EPDC_PIX_PODF 84
+#define IMX6SL_CLK_SPDIF0_PRED 85
+#define IMX6SL_CLK_SPDIF0_PODF 86
+#define IMX6SL_CLK_SPDIF1_PRED 87
+#define IMX6SL_CLK_SPDIF1_PODF 88
+#define IMX6SL_CLK_EXTERN_AUDIO_PRED 89
+#define IMX6SL_CLK_EXTERN_AUDIO_PODF 90
+#define IMX6SL_CLK_ECSPI_ROOT 91
+#define IMX6SL_CLK_UART_ROOT 92
+#define IMX6SL_CLK_AHB 93
+#define IMX6SL_CLK_MMDC_ROOT 94
+#define IMX6SL_CLK_ARM 95
+#define IMX6SL_CLK_ECSPI1 96
+#define IMX6SL_CLK_ECSPI2 97
+#define IMX6SL_CLK_ECSPI3 98
+#define IMX6SL_CLK_ECSPI4 99
+#define IMX6SL_CLK_EPIT1 100
+#define IMX6SL_CLK_EPIT2 101
+#define IMX6SL_CLK_EXTERN_AUDIO 102
+#define IMX6SL_CLK_GPT 103
+#define IMX6SL_CLK_GPT_SERIAL 104
+#define IMX6SL_CLK_GPU2D_OVG 105
+#define IMX6SL_CLK_I2C1 106
+#define IMX6SL_CLK_I2C2 107
+#define IMX6SL_CLK_I2C3 108
+#define IMX6SL_CLK_OCOTP 109
+#define IMX6SL_CLK_CSI 110
+#define IMX6SL_CLK_PXP_AXI 111
+#define IMX6SL_CLK_EPDC_AXI 112
+#define IMX6SL_CLK_LCDIF_AXI 113
+#define IMX6SL_CLK_LCDIF_PIX 114
+#define IMX6SL_CLK_EPDC_PIX 115
+#define IMX6SL_CLK_OCRAM 116
+#define IMX6SL_CLK_PWM1 117
+#define IMX6SL_CLK_PWM2 118
+#define IMX6SL_CLK_PWM3 119
+#define IMX6SL_CLK_PWM4 120
+#define IMX6SL_CLK_SDMA 121
+#define IMX6SL_CLK_SPDIF 122
+#define IMX6SL_CLK_SSI1 123
+#define IMX6SL_CLK_SSI2 124
+#define IMX6SL_CLK_SSI3 125
+#define IMX6SL_CLK_UART 126
+#define IMX6SL_CLK_UART_SERIAL 127
+#define IMX6SL_CLK_USBOH3 128
+#define IMX6SL_CLK_USDHC1 129
+#define IMX6SL_CLK_USDHC2 130
+#define IMX6SL_CLK_USDHC3 131
+#define IMX6SL_CLK_USDHC4 132
+#define IMX6SL_CLK_PLL4_AUDIO_DIV 133
+#define IMX6SL_CLK_SPBA 134
+#define IMX6SL_CLK_ENET 135
+#define IMX6SL_CLK_LVDS1_SEL 136
+#define IMX6SL_CLK_LVDS1_OUT 137
+#define IMX6SL_CLK_LVDS1_IN 138
+#define IMX6SL_CLK_ANACLK1 139
+#define IMX6SL_PLL1_BYPASS_SRC 140
+#define IMX6SL_PLL2_BYPASS_SRC 141
+#define IMX6SL_PLL3_BYPASS_SRC 142
+#define IMX6SL_PLL4_BYPASS_SRC 143
+#define IMX6SL_PLL5_BYPASS_SRC 144
+#define IMX6SL_PLL6_BYPASS_SRC 145
+#define IMX6SL_PLL7_BYPASS_SRC 146
+#define IMX6SL_CLK_PLL1 147
+#define IMX6SL_CLK_PLL2 148
+#define IMX6SL_CLK_PLL3 149
+#define IMX6SL_CLK_PLL4 150
+#define IMX6SL_CLK_PLL5 151
+#define IMX6SL_CLK_PLL6 152
+#define IMX6SL_CLK_PLL7 153
+#define IMX6SL_PLL1_BYPASS 154
+#define IMX6SL_PLL2_BYPASS 155
+#define IMX6SL_PLL3_BYPASS 156
+#define IMX6SL_PLL4_BYPASS 157
+#define IMX6SL_PLL5_BYPASS 158
+#define IMX6SL_PLL6_BYPASS 159
+#define IMX6SL_PLL7_BYPASS 160
+#define IMX6SL_CLK_SSI1_IPG 161
+#define IMX6SL_CLK_SSI2_IPG 162
+#define IMX6SL_CLK_SSI3_IPG 163
+#define IMX6SL_CLK_SPDIF_GCLK 164
+#define IMX6SL_CLK_END 165
+
+#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */
generated by cgit (git 2.34.1) at 2024-12-27 03:36:15 +0000