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-rw-r--r--include/asm-ppc/processor.h2
-rw-r--r--include/configs/luan.h306
-rw-r--r--include/ppc440.h225
-rw-r--r--include/ppc4xx_enet.h6
4 files changed, 406 insertions, 133 deletions
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 0b30d2d710..811378383d 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -731,6 +731,8 @@
#define PVR_440GX_RC 0x51B21892
#define PVR_440GX_RF 0x51B21894
#define PVR_405EP_RB 0x51210950
+#define PVR_440SP_RA 0x53221850
+#define PVR_440SP_RB 0x53221891
#define PVR_601 0x00010000
#define PVR_602 0x00050000
#define PVR_603 0x00030000
diff --git a/include/configs/luan.h b/include/configs/luan.h
new file mode 100644
index 0000000000..0335a00985
--- /dev/null
+++ b/include/configs/luan.h
@@ -0,0 +1,306 @@
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ * John Otken, jotken@softadvances.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * luan.h - configuration for LUAN board
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_LUAN 1 /* Board is Luan */
+#define CONFIG_440SP 1 /* Specific PPC440SP support */
+#define CONFIG_4xx 1 /* PPC4xx family */
+#define CONFIG_440 1
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
+#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc */
+#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
+#define CFG_SDRAM_BASE 0x00000000 /* MUST be zero */
+
+#define CFG_LARGE_FLASH 0xffc00000 /* 4MB flash address CS0 */
+#define CFG_SMALL_FLASH 0xff900000 /* 1MB flash address CS2 */
+#define CFG_SRAM_BASE 0xff800000 /* 1MB SRAM address CS2 */
+#define CFG_EPLD_BASE 0xff000000 /* EPLD and FRAM CS1 */
+
+#define CFG_ISRAM_BASE 0xf8000000 /* internal 8k SRAM (L2 cache) */
+
+#define CFG_PERIPHERAL_BASE 0xf0000000 /* internal peripherals */
+
+#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
+#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
+#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
+
+#if CFG_LARGE_FLASH == 0xffc00000
+#define CFG_FLASH_BASE CFG_LARGE_FLASH
+#else
+#define CFG_FLASH_BASE CFG_SMALL_FLASH
+#endif
+
+#undef CFG_DRAM_TEST
+#if CFG_SRAM_BASE
+#define CFG_KBYTES_SDRAM 1024*2
+#else
+#define CFG_KBYTES_SDRAM 1024
+#endif
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in SDRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE
+#define CFG_INIT_RAM_END (8 << 10)
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CFG_EXT_SERIAL_CLOCK 11059200 /* external 11.059MHz clk */
+#define CONFIG_BAUDRATE 115200
+#undef CONFIG_SERIAL_MULTI
+#undef CONFIG_UART1_CONSOLE /* define if you want console on UART1 */
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+/*
+ * Define here the location of the environment variables (FLASH or EEPROM).
+ * Note: DENX encourages to use redundant environment in FLASH.
+ */
+#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+
+#define CFG_FLASH_ADDR0 0x555
+#define CFG_FLASH_ADDR1 0x2aa
+#define CFG_FLASH_WORD_SIZE unsigned char
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#undef CONFIG_SPD_EEPROM /* SPD EEPROM init doesn't support DDR2 */
+#define SPD_EEPROM_ADDRESS {0x52,0x53} /* I2C SPD addresses */
+#define IIC0_DIMM0_ADDR 0x52
+#define IIC0_DIMM1_ADDR 0x53
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "hostname=luan\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath)\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs $(bootargs) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
+ ":$(hostname):$(netdev):off panic=1\0" \
+ "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm $(kernel_addr)\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm $(kernel_addr) $(ramdisk_addr)\0" \
+ "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
+ "bootm\0" \
+ "rootpath=/opt/eldk/ppc_4xx\0" \
+ "bootfile=/tftpboot/luan/uImage\0" \
+ "kernel_addr=fc000000\0" \
+ "ramdisk_addr=fc100000\0" \
+ "load=tftp 100000 /tftpboot/luan/u-boot.bin\0" \
+ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
+ "cp.b 100000 fffc0000 40000;" \
+ "setenv filesize;saveenv\0" \
+ "upd=run load;run update\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 1
+#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NETCONSOLE /* include NetConsole support */
+#define CONFIG_NET_MULTI /* needed for NetConsole */
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#ifdef DEBUG
+#define CONFIG_PANIC_HANG
+#else
+#define CONFIG_HW_WATCHDOG /* watchdog */
+#endif
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_CACHE | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_DIAG | \
+ CFG_CMD_ELF | \
+ CFG_CMD_I2C | \
+ CFG_CMD_IRQ | \
+ CFG_CMD_MII | \
+ CFG_CMD_NET | \
+ CFG_CMD_NFS | \
+ CFG_CMD_PCI | \
+ CFG_CMD_PING | \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_SETGETDCR | \
+ CFG_CMD_SDRAM | \
+ 0)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+#undef CONFIG_LYNXKDI /* support kdi files */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_PCI)
+
+/* General PCI */
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
+#define CFG_PCI_TARGET_INIT
+#undef CFG_PCI_MASTER_INIT
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
+#define CFG_PCI_SUBSYS_DEVICEID 0x4403 /* whatever */
+
+#endif /* CONFIG_COMMANDS & CFG_CMD_PCI */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/ppc440.h b/include/ppc440.h
index 41db16ff2f..018f7be8ac 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -78,7 +78,7 @@
#define ivor13 0x19d /* interrupt vector offset register 13 */
#define ivor14 0x19e /* interrupt vector offset register 14 */
#define ivor15 0x19f /* interrupt vector offset register 15 */
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
#define mcsrr0 0x23a /* machine check save/restore register 0 */
#define mcsrr1 0x23b /* mahcine check save/restore register 1 */
#define mcsr 0x23c /* machine check status register */
@@ -178,7 +178,6 @@
#define sdr_plbtr 0x4200
#define sdr_mfr 0x4300 /* SDR0_MFR reg */
-
/*-----------------------------------------------------------------------------
| SDRAM Controller
+----------------------------------------------------------------------------*/
@@ -504,7 +503,7 @@
/*-----------------------------------------------------------------------------
| L2 Cache
+----------------------------------------------------------------------------*/
-#if defined (CONFIG_440GX)
+#if defined (CONFIG_440GX) || defined(CONFIG_440SP)
#define L2_CACHE_BASE 0x030
#define l2_cache_cfg (L2_CACHE_BASE+0x00) /* L2 Cache Config */
#define l2_cache_cmd (L2_CACHE_BASE+0x01) /* L2 Cache Command */
@@ -527,7 +526,7 @@
| Clocking, Power Management and Chip Control
+----------------------------------------------------------------------------*/
#define CNTRL_DCR_BASE 0x0b0
-#if defined (CONFIG_440GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
#define cpc0_er (CNTRL_DCR_BASE+0x00) /* CPM enable register */
#define cpc0_fr (CNTRL_DCR_BASE+0x01) /* CPM force register */
#define cpc0_sr (CNTRL_DCR_BASE+0x02) /* CPM status register */
@@ -690,6 +689,40 @@
/*---------------------------------------------------------------------------+
| Universal interrupt controller 0 interrupts (UIC0)
+---------------------------------------------------------------------------*/
+#if defined(CONFIG_440SP)
+#define UIC_U0 0x80000000 /* UART 0 */
+#define UIC_U1 0x40000000 /* UART 1 */
+#define UIC_IIC0 0x20000000 /* IIC */
+#define UIC_IIC1 0x10000000 /* IIC */
+#define UIC_PIM 0x08000000 /* PCI0 inbound message */
+#define UIC_PCRW 0x04000000 /* PCI0 command write register */
+#define UIC_PPM 0x02000000 /* PCI0 power management */
+#define UIC_PVPD 0x01000000 /* PCI0 VPD Access */
+#define UIC_MSI0 0x00800000 /* PCI0 MSI level 0 */
+#define UIC_P1IM 0x00400000 /* PCI1 Inbound Message */
+#define UIC_P1CRW 0x00200000 /* PCI1 command write register */
+#define UIC_P1PM 0x00100000 /* PCI1 power management */
+#define UIC_P1VPD 0x00080000 /* PCI1 VPD Access */
+#define UIC_P1MSI0 0x00040000 /* PCI1 MSI level 0 */
+#define UIC_P2IM 0x00020000 /* PCI2 inbound message */
+#define UIC_P2CRW 0x00010000 /* PCI2 command register write */
+#define UIC_P2PM 0x00008000 /* PCI2 power management */
+#define UIC_P2VPD 0x00004000 /* PCI2 VPD access */
+#define UIC_P2MSI0 0x00002000 /* PCI2 MSI level 0 */
+#define UIC_D0CPF 0x00001000 /* DMA0 command pointer */
+#define UIC_D0CSF 0x00000800 /* DMA0 command status */
+#define UIC_D1CPF 0x00000400 /* DMA1 command pointer */
+#define UIC_D1CSF 0x00000200 /* DMA1 command status */
+#define UIC_I2OID 0x00000100 /* I2O inbound doorbell */
+#define UIC_I2OPLF 0x00000080 /* I2O inbound post list */
+#define UIC_I2O0LL 0x00000040 /* I2O0 low latency PLB write */
+#define UIC_I2O1LL 0x00000020 /* I2O1 low latency PLB write */
+#define UIC_I2O0HB 0x00000010 /* I2O0 high bandwidth PLB write */
+#define UIC_I2O1HB 0x00000008 /* I2O1 high bandwidth PLB write */
+#define UIC_GPTCT 0x00000004 /* GPT count timer */
+#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
+#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
+#else /* CONFIG_440SP */
#define UIC_U0 0x80000000 /* UART 0 */
#define UIC_U1 0x40000000 /* UART 1 */
#define UIC_IIC0 0x20000000 /* IIC */
@@ -722,6 +755,7 @@
#define UIC_EIR6 0x00000004 /* External interrupt 6 */
#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
+#endif /* CONFIG_440SP */
/* For compatibility with 405 code */
#define UIC_MAL_TXEOB UIC_MTE
@@ -730,6 +764,40 @@
/*---------------------------------------------------------------------------+
| Universal interrupt controller 1 interrupts (UIC1)
+---------------------------------------------------------------------------*/
+#if defined(CONFIG_440SP)
+#define UIC_EIR0 0x80000000 /* External interrupt 0 */
+#define UIC_MS 0x40000000 /* MAL SERR */
+#define UIC_MTDE 0x20000000 /* MAL TXDE */
+#define UIC_MRDE 0x10000000 /* MAL RXDE */
+#define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */
+#define UIC_EBCO 0x04000000 /* EBCO interrupt status */
+#define UIC_MTE 0x02000000 /* MAL TXEOB */
+#define UIC_MRE 0x01000000 /* MAL RXEOB */
+#define UIC_P0MSI1 0x00800000 /* PCI0 MSI level 1 */
+#define UIC_P1MSI1 0x00400000 /* PCI1 MSI level 1 */
+#define UIC_P2MSI1 0x00200000 /* PCI2 MSI level 1 */
+#define UIC_L2C 0x00100000 /* L2 cache */
+#define UIC_CT0 0x00080000 /* GPT compare timer 0 */
+#define UIC_CT1 0x00040000 /* GPT compare timer 1 */
+#define UIC_CT2 0x00020000 /* GPT compare timer 2 */
+#define UIC_CT3 0x00010000 /* GPT compare timer 3 */
+#define UIC_CT4 0x00008000 /* GPT compare timer 4 */
+#define UIC_EIR1 0x00004000 /* External interrupt 1 */
+#define UIC_EIR2 0x00002000 /* External interrupt 2 */
+#define UIC_EIR3 0x00001000 /* External interrupt 3 */
+#define UIC_EIR4 0x00000800 /* External interrupt 4 */
+#define UIC_EIR5 0x00000400 /* External interrupt 5 */
+#define UIC_DMAE 0x00000200 /* DMA error */
+#define UIC_I2OE 0x00000100 /* I2O error */
+#define UIC_SRE 0x00000080 /* Serial ROM error */
+#define UIC_P0AE 0x00000040 /* PCI0 asynchronous error */
+#define UIC_P1AE 0x00000020 /* PCI1 asynchronous error */
+#define UIC_P2AE 0x00000010 /* PCI2 asynchronous error */
+#define UIC_ETH0 0x00000008 /* Ethernet 0 */
+#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
+#define UIC_ETH1 0x00000002 /* Reserved */
+#define UIC_XOR 0x00000001 /* XOR */
+#else /* CONFIG_440SP */
#define UIC_MS 0x80000000 /* MAL SERR */
#define UIC_MTDE 0x40000000 /* MAL TXDE */
#define UIC_MRDE 0x20000000 /* MAL RXDE */
@@ -762,6 +830,7 @@
#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
#define UIC_ETH1 0x00000002 /* Ethernet 1 */
#define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */
+#endif /* CONFIG_440SP */
/* For compatibility with 405 code */
#define UIC_MAL_SERR UIC_MS
@@ -850,6 +919,11 @@
#define EBC_BXAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23)
#define EBC_BXAP_BCE_DISABLE 0x00000000
#define EBC_BXAP_BCE_ENABLE 0x00400000
+#define EBC_BXAP_BCT_MASK 0x00300000
+#define EBC_BXAP_BCT_2TRANS 0x00000000
+#define EBC_BXAP_BCT_4TRANS 0x00100000
+#define EBC_BXAP_BCT_8TRANS 0x00200000
+#define EBC_BXAP_BCT_16TRANS 0x00300000
#define EBC_BXAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18)
#define EBC_BXAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
#define EBC_BXAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14)
@@ -905,133 +979,22 @@
#define EBC_CFG_PR_128 0x0000C000
/*-----------------------------------------------------------------------------+
-| SDR 0 Bit Settings
+| SDR0 Bit Settings
+-----------------------------------------------------------------------------*/
-#define SDR0_SDSTP0_ENG_MASK 0x80000000
-#define SDR0_SDSTP0_ENG_PLLDIS 0x00000000
-#define SDR0_SDSTP0_ENG_PLLENAB 0x80000000
-#define SDR0_SDSTP0_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
-#define SDR0_SDSTP0_ENG_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
-#define SDR0_SDSTP0_SRC_MASK 0x40000000
-#define SDR0_SDSTP0_SRC_PLLOUTA 0x00000000
-#define SDR0_SDSTP0_SRC_PLLOUTB 0x40000000
-#define SDR0_SDSTP0_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
-#define SDR0_SDSTP0_SRC_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
-#define SDR0_SDSTP0_SEL_MASK 0x38000000
-#define SDR0_SDSTP0_SEL_PLLOUT 0x00000000
-#define SDR0_SDSTP0_SEL_CPU 0x08000000
-#define SDR0_SDSTP0_SEL_EBC 0x28000000
-#define SDR0_SDSTP0_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<27)
-#define SDR0_SDSTP0_SEL_DECODE(n) ((((unsigned long)(n))>>27)&0x07)
-#define SDR0_SDSTP0_TUNE_MASK 0x07FE0000
-#define SDR0_SDSTP0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<17)
-#define SDR0_SDSTP0_TUNE_DECODE(n) ((((unsigned long)(n))>>17)&0x3FF)
-#define SDR0_SDSTP0_FBDV_MASK 0x0001F000
-#define SDR0_SDSTP0_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
-#define SDR0_SDSTP0_FBDV_DECODE(n) ((((((unsigned long)(n))>>12)-1)&0x1F)+1)
-#define SDR0_SDSTP0_FWDVA_MASK 0x00000F00
-#define SDR0_SDSTP0_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<8)
-#define SDR0_SDSTP0_FWDVA_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x0F)+1)
-#define SDR0_SDSTP0_FWDVB_MASK 0x000000E0
-#define SDR0_SDSTP0_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<5)
-#define SDR0_SDSTP0_FWDVB_DECODE(n) ((((((unsigned long)(n))>>5)-1)&0x07)+1)
-#define SDR0_SDSTP0_PRBDV0_MASK 0x0000001C
-#define SDR0_SDSTP0_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<2)
-#define SDR0_SDSTP0_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>2)-1)&0x07)+1)
-#define SDR0_SDSTP0_OPBDV0_MASK 0x00000003
-#define SDR0_SDSTP0_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<0)
-#define SDR0_SDSTP0_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x03)+1)
-
-#define SDR0_SDSTP1_LFBDV_MASK 0xFC000000
-#define SDR0_SDSTP1_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<26)
-#define SDR0_SDSTP1_LFBDV_DECODE(n) ((((unsigned long)(n))>>26)&0x3F)
-#define SDR0_SDSTP1_EBCDV0_MASK 0x03000000
-#define SDR0_SDSTP1_EBCDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
-#define SDR0_SDSTP1_EBCDV0_DECODE(n) ((((unsigned long)(n))>>24)&0x03)
-#define SDR0_SDSTP1_MALDV0_MASK 0x00C00000
-#define SDR0_SDSTP1_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<22)
-#define SDR0_SDSTP1_MALDV0_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
-#define SDR0_SDSTP1_RW_MASK 0x00300000
-#define SDR0_SDSTP1_RW_8BIT 0x00000000
-#define SDR0_SDSTP1_RW_16BIT 0x00100000
-#define SDR0_SDSTP1_RW_32BIT 0x00200000
-#define SDR0_SDSTP1_RW_ENCODE(n) ((((unsigned long)(n))&0x03)<<20)
-#define SDR0_SDSTP1_RW_DECODE(n) ((((unsigned long)(n))>>20)&0x03)
-#define SDR0_SDSTP1_EARV_MASK 0x00080000
-#define SDR0_SDSTP1_EARV_EBC 0x00000000
-#define SDR0_SDSTP1_EARV_PCI 0x00080000
-#define SDR0_SDSTP1_PAE_MASK 0x00040000
-#define SDR0_SDSTP1_PAE_DISABLE 0x00000000
-#define SDR0_SDSTP1_PAE_ENABLE 0x00040000
-#define SDR0_SDSTP1_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18)
-#define SDR0_SDSTP1_PAE_DECODE(n) ((((unsigned long)(n))>>18)&0x01)
-#define SDR0_SDSTP1_PHCE_MASK 0x00020000
-#define SDR0_SDSTP1_PHCE_DISABLE 0x00000000
-#define SDR0_SDSTP1_PHCE_ENABLE 0x00020000
-#define SDR0_SDSTP1_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17)
-#define SDR0_SDSTP1_PHCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01)
-#define SDR0_SDSTP1_PISE_MASK 0x00010000
-#define SDR0_SDSTP1_PISE_DISABLE 0x00000000
-#define SDR0_SDSTP1_PISE_ENABLE 0x00010000
-#define SDR0_SDSTP1_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16)
-#define SDR0_SDSTP1_PISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01)
-#define SDR0_SDSTP1_PCWE_MASK 0x00008000
-#define SDR0_SDSTP1_PCWE_DISABLE 0x00000000
-#define SDR0_SDSTP1_PCWE_ENABLE 0x00008000
-#define SDR0_SDSTP1_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15)
-#define SDR0_SDSTP1_PCWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01)
-#define SDR0_SDSTP1_PPIM_MASK 0x00008000
-#define SDR0_SDSTP1_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11)
-#define SDR0_SDSTP1_PPIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F)
-#define SDR0_SDSTP1_PR64E_MASK 0x00000400
-#define SDR0_SDSTP1_PR64E_DISABLE 0x00000000
-#define SDR0_SDSTP1_PR64E_ENABLE 0x00000400
-#define SDR0_SDSTP1_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<10)
-#define SDR0_SDSTP1_PR64E_DECODE(n) ((((unsigned long)(n))>>10)&0x01)
-#define SDR0_SDSTP1_PXFS_MASK 0x00000300
-#define SDR0_SDSTP1_PXFS_HIGH 0x00000000
-#define SDR0_SDSTP1_PXFS_MED 0x00000100
-#define SDR0_SDSTP1_PXFS_LOW 0x00000200
-#define SDR0_SDSTP1_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
-#define SDR0_SDSTP1_PXFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
-#define SDR0_SDSTP1_PDM_MASK 0x00000040
-#define SDR0_SDSTP1_PDM_MULTIPOINT 0x00000000
-#define SDR0_SDSTP1_PDM_P2P 0x00000040
-#define SDR0_SDSTP1_PDM_ENCODE(n) ((((unsigned long)(n))&0x01)<<6)
-#define SDR0_SDSTP1_PDM_DECODE(n) ((((unsigned long)(n))>>6)&0x01)
-#define SDR0_SDSTP1_EPS_MASK 0x00000038
-#define SDR0_SDSTP1_EPS_GROUP0 0x00000000
-#define SDR0_SDSTP1_EPS_GROUP1 0x00000008
-#define SDR0_SDSTP1_EPS_GROUP2 0x00000010
-#define SDR0_SDSTP1_EPS_GROUP3 0x00000018
-#define SDR0_SDSTP1_EPS_GROUP4 0x00000020
-#define SDR0_SDSTP1_EPS_GROUP5 0x00000028
-#define SDR0_SDSTP1_EPS_GROUP6 0x00000030
-#define SDR0_SDSTP1_EPS_GROUP7 0x00000038
-#define SDR0_SDSTP1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<3)
-#define SDR0_SDSTP1_EPS_DECODE(n) ((((unsigned long)(n))>>3)&0x07)
-#define SDR0_SDSTP1_RMII_MASK 0x00000004
-#define SDR0_SDSTP1_RMII_100MBIT 0x00000000
-#define SDR0_SDSTP1_RMII_10MBIT 0x00000004
-#define SDR0_SDSTP1_RMII_ENCODE(n) ((((unsigned long)(n))&0x01)<<2)
-#define SDR0_SDSTP1_RMII_DECODE(n) ((((unsigned long)(n))>>2)&0x01)
-#define SDR0_SDSTP1_TRE_MASK 0x00000002
-#define SDR0_SDSTP1_TRE_DISABLE 0x00000000
-#define SDR0_SDSTP1_TRE_ENABLE 0x00000002
-#define SDR0_SDSTP1_TRE_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
-#define SDR0_SDSTP1_TRE_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
-#define SDR0_SDSTP1_NTO1_MASK 0x00000001
-#define SDR0_SDSTP1_NTO1_DISABLE 0x00000000
-#define SDR0_SDSTP1_NTO1_ENABLE 0x00000001
-#define SDR0_SDSTP1_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<0)
-#define SDR0_SDSTP1_NTO1_DECODE(n) ((((unsigned long)(n))>>0)&0x01)
-
-#define SDR0_EBC_RW_MASK 0x30000000
-#define SDR0_EBC_RW_8BIT 0x00000000
-#define SDR0_EBC_RW_16BIT 0x10000000
-#define SDR0_EBC_RW_32BIT 0x20000000
-#define SDR0_EBC_RW_ENCODE(n) ((((unsigned long)(n))&0x03)<<28)
-#define SDR0_EBC_RW_DECODE(n) ((((unsigned long)(n))>>28)&0x03)
+#define SDR0_SDCS_SDD (0x80000000 >> 31)
+
+#if defined(CONFIG_440GP)
+#define CPC0_STRP1_PAE_MASK (0x80000000 >> 11)
+#define CPC0_STRP1_PISE_MASK (0x80000000 >> 13)
+#endif /* defined(CONFIG_440GP) */
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
+#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13)
+#define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15)
+#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 21)
+#define SDR0_SDSTP1_PAME_MASK (0x80000000 >> 27)
+#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
#define SDR0_UARTX_UXICS_MASK 0xF0000000
#define SDR0_UARTX_UXICS_PLB 0x20000000
@@ -1196,7 +1159,7 @@
/*-----------------------------------------------------------------------------+
| Clocking
+-----------------------------------------------------------------------------*/
-#if !defined (CONFIG_440GX) && !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
+#if !defined (CONFIG_440GX) && !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && !defined(CONFIG_440SP)
#define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */
#define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */
#define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */
diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h
index eacfb68016..d6d33b6957 100644
--- a/include/ppc4xx_enet.h
+++ b/include/ppc4xx_enet.h
@@ -131,7 +131,9 @@ typedef struct emac_4xx_hw_st {
#if defined(CONFIG_440GX)
#define EMAC_NUM_DEV 4
-#elif (defined(CONFIG_440) || defined(CONFIG_405EP)) && defined(CONFIG_NET_MULTI)
+#elif (defined(CONFIG_440) || defined(CONFIG_405EP)) && \
+ defined(CONFIG_NET_MULTI) && \
+ !defined(CONFIG_440SP)
#define EMAC_NUM_DEV 2
#else
#define EMAC_NUM_DEV 1
@@ -321,7 +323,7 @@ typedef struct emac_4xx_hw_st {
#define EMAC_M0_WKE (0x04000000)
/* on 440GX EMAC_MR1 has a different layout! */
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
/* MODE Reg 1 */
#define EMAC_M1_FDE (0x80000000)
#define EMAC_M1_ILE (0x40000000)