diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/command.h | 2 | ||||
| -rw-r--r-- | include/configs/p2571.h | 75 | ||||
| -rw-r--r-- | include/configs/tegra-common-post.h | 12 | ||||
| -rw-r--r-- | include/configs/tegra-common.h | 7 | ||||
| -rw-r--r-- | include/configs/tegra124-common.h | 2 | ||||
| -rw-r--r-- | include/configs/tegra210-common.h | 76 | ||||
| -rw-r--r-- | include/dt-bindings/clock/tegra210-car.h | 342 | ||||
| -rw-r--r-- | include/fdtdec.h | 3 |
8 files changed, 516 insertions, 3 deletions
diff --git a/include/command.h b/include/command.h index bd3fc049ec..6c04cd9007 100644 --- a/include/command.h +++ b/include/command.h @@ -104,6 +104,8 @@ static inline int bootm_maybe_autostart(cmd_tbl_t *cmdtp, const char *cmd) extern int do_bootz(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); +extern int do_booti(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); + extern int common_diskboot(cmd_tbl_t *cmdtp, const char *intf, int argc, char *const argv[]); diff --git a/include/configs/p2571.h b/include/configs/p2571.h new file mode 100644 index 0000000000..77faf5fdbc --- /dev/null +++ b/include/configs/p2571.h @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _P2571_H +#define _P2571_H + +#include <linux/sizes.h> + +/* enable PMIC */ +#define CONFIG_MAX77620_POWER + +#include "tegra210-common.h" + +/* High-level configuration options */ +#define V_PROMPT "Tegra210 (P2571) # " +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2571" + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +/* I2C */ +#define CONFIG_SYS_I2C_TEGRA +#define CONFIG_CMD_I2C + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC +#define CONFIG_CMD_MMC + +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) + +/* SPI */ +#define CONFIG_TEGRA114_SPI /* Compatible w/ Tegra114 SPI */ +#define CONFIG_TEGRA114_SPI_CTRLS 6 +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 24000000 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +/* USB2.0 Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_DHCP + +/* + * TODO(twarren@nvidia.com) - add tegra-common-usb-gadget.h back + * breaks 64-bit build in ci_udc.c + */ +#include "tegra-common-post.h" + +#define COUNTER_FREQUENCY 38400000 + +#endif /* _P2571_H */ diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index 483222fbcf..e67ff7b957 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -62,11 +62,19 @@ #define CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS #endif +#ifdef CONFIG_ARM64 +#define FDT_HIGH "ffffffffffffffff" +#define INITRD_HIGH "ffffffffffffffff" +#else +#define FDT_HIGH "ffffffff" +#define INITRD_HIGH "ffffffff" +#endif + #define CONFIG_EXTRA_ENV_SETTINGS \ TEGRA_DEVICE_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ - "fdt_high=ffffffff\0" \ - "initrd_high=ffffffff\0" \ + "fdt_high=" FDT_HIGH "\0" \ + "initrd_high=" INITRD_HIGH "\0" \ BOOTENV \ BOARD_EXTRA_ENV_SETTINGS \ CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 7b4c0d7063..ffe167e85a 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -18,8 +18,11 @@ #include <asm/arch/tegra.h> /* get chip and board defs */ +/* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */ +#ifndef CONFIG_ARM64 #define CONFIG_SYS_TIMER_RATE 1000000 #define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE +#endif /* * Display CPU and Board information @@ -43,7 +46,9 @@ #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */ #endif +#ifndef CONFIG_ARM64 #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ +#endif /* * NS16550 Configuration @@ -101,9 +106,11 @@ #define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000) #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) +#ifndef CONFIG_ARM64 #ifndef CONFIG_SPL_BUILD #define CONFIG_USE_ARCH_MEMCPY #endif +#endif /*----------------------------------------------------------------------- * Physical Memory Map diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h index 1aee5c89f4..af7698d95c 100644 --- a/include/configs/tegra124-common.h +++ b/include/configs/tegra124-common.h @@ -26,7 +26,7 @@ /*----------------------------------------------------------------------- * Physical Memory Map */ -#define CONFIG_SYS_TEXT_BASE 0x8010E000 +#define CONFIG_SYS_TEXT_BASE 0x80110000 /* * Memory layout for where various images get loaded by boot scripts: diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h new file mode 100644 index 0000000000..0348d4783b --- /dev/null +++ b/include/configs/tegra210-common.h @@ -0,0 +1,76 @@ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA210_COMMON_H_ +#define _TEGRA210_COMMON_H_ + +#include "tegra-common.h" + +/* Cortex-A57 uses a cache line size of 64 bytes */ +#define CONFIG_SYS_CACHELINE_SIZE 64 + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_STACKBASE 0x82800000 /* 40MB */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_SYS_TEXT_BASE 0x8010E000 + +/* Generic Interrupt Controller */ +#define CONFIG_GICV2 + +/* + * Memory layout for where various images get loaded by boot scripts: + * + * scriptaddr can be pretty much anywhere that doesn't conflict with something + * else. Put it above BOOTMAPSZ to eliminate conflicts. + * + * pxefile_addr_r can be pretty much anywhere that doesn't conflict with + * something else. Put it above BOOTMAPSZ to eliminate conflicts. + * + * kernel_addr_r must be within the first 128M of RAM in order for the + * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will + * decompress itself to 0x8000 after the start of RAM, kernel_addr_r + * should not overlap that area, or the kernel will have to copy itself + * somewhere else before decompression. Similarly, the address of any other + * data passed to the kernel shouldn't overlap the start of RAM. Pushing + * this up to 16M allows for a sizable kernel to be decompressed below the + * compressed load address. + * + * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for + * the compressed kernel to be up to 16M too. + * + * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows + * for the FDT/DTB to be up to 1M, which is hopefully plenty. + */ +#define CONFIG_LOADADDR 0x81000000 +#define MEM_LAYOUT_ENV_SETTINGS \ + "scriptaddr=0x90000000\0" \ + "pxefile_addr_r=0x90100000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "fdt_addr_r=0x82000000\0" \ + "ramdisk_addr_r=0x82100000\0" + +/* Defines for SPL */ +#define CONFIG_SPL_TEXT_BASE 0x80108000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80090000 +#define CONFIG_SPL_STACK 0x800ffffc + +/* For USB EHCI controller */ +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1 + +#endif /* _TEGRA210_COMMON_H_ */ diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h new file mode 100644 index 0000000000..d134741eb5 --- /dev/null +++ b/include/dt-bindings/clock/tegra210-car.h @@ -0,0 +1,342 @@ +/* + * This header provides Tegra210-specific constants for binding + * nvidia,tegra210-car. + */ + +#ifndef _DT_BINDINGS_CLOCK_TEGRA210_CAR_H +#define _DT_BINDINGS_CLOCK_TEGRA210_CAR_H + +/* 0 */ +/* 1 */ +/* 2 */ +#define TEGRA210_CLK_ISPB 3 +#define TEGRA210_CLK_RTC 4 +#define TEGRA210_CLK_TIMER 5 +#define TEGRA210_CLK_UARTA 6 +/* 7 (register bit affects uartb and vfir) */ +/* 8 */ +#define TEGRA210_CLK_SDMMC2 9 +/* 10 (register bit affects spdif_in and spdif_out) */ +#define TEGRA210_CLK_I2S1 11 +#define TEGRA210_CLK_I2C1 12 +/* 13 */ +#define TEGRA210_CLK_SDMMC1 14 +#define TEGRA210_CLK_SDMMC4 15 +/* 16 */ +#define TEGRA210_CLK_PWM 17 +#define TEGRA210_CLK_I2S2 18 +/* 20 (register bit affects vi and vi_sensor) */ +/* 21 */ +#define TEGRA210_CLK_USBD 22 +#define TEGRA210_CLK_ISP 23 +/* 26 */ +/* 25 */ +#define TEGRA210_CLK_DISP2 26 +#define TEGRA210_CLK_DISP1 27 +#define TEGRA210_CLK_HOST1X 28 +#define TEGRA210_CLK_VCP 29 +#define TEGRA210_CLK_I2S0 30 +/* 31 */ + +#define TEGRA210_CLK_MC 32 +/* 33 */ +#define TEGRA210_CLK_APBDMA 34 +/* 35 */ +#define TEGRA210_CLK_KBC 36 +/* 37 */ +/* 38 */ +/* 39 (register bit affects fuse and fuse_burn) */ +#define TEGRA210_CLK_KFUSE 40 +#define TEGRA210_CLK_SBC1 41 +#define TEGRA210_CLK_NOR 42 +/* 43 */ +#define TEGRA210_CLK_SBC2 44 +/* 45 */ +#define TEGRA210_CLK_SBC3 46 +#define TEGRA210_CLK_I2C5 47 +#define TEGRA210_CLK_DSIA 48 +/* 49 */ +#define TEGRA210_CLK_MIPI 50 +#define TEGRA210_CLK_HDMI 51 +#define TEGRA210_CLK_CSI 52 +/* 53 */ +#define TEGRA210_CLK_I2C2 54 +#define TEGRA210_CLK_UARTC 55 +#define TEGRA210_CLK_MIPI_CAL 56 +#define TEGRA210_CLK_EMC 57 +#define TEGRA210_CLK_USB2 58 +#define TEGRA210_CLK_USB3 59 +/* 60 */ +#define TEGRA210_CLK_VDE 61 +#define TEGRA210_CLK_BSEA 62 +#define TEGRA210_CLK_BSEV 63 + +/* 64 */ +#define TEGRA210_CLK_UARTD 65 +/* 66 */ +#define TEGRA210_CLK_I2C3 67 +#define TEGRA210_CLK_SBC4 68 +#define TEGRA210_CLK_SDMMC3 69 +#define TEGRA210_CLK_PCIE 70 +#define TEGRA210_CLK_OWR 71 +#define TEGRA210_CLK_AFI 72 +#define TEGRA210_CLK_CSITE 73 +/* 74 */ +/* 75 */ +#define TEGRA210_CLK_LA 76 +#define TEGRA210_CLK_TRACE 77 +#define TEGRA210_CLK_SOC_THERM 78 +#define TEGRA210_CLK_DTV 79 +/* 80 */ +#define TEGRA210_CLK_I2CSLOW 81 +#define TEGRA210_CLK_DSIB 82 +#define TEGRA210_CLK_TSEC 83 +/* 84 */ +/* 85 */ +/* 86 */ +/* 87 */ +/* 88 */ +#define TEGRA210_CLK_XUSB_HOST 89 +/* 90 */ +#define TEGRA210_CLK_MSENC 91 +#define TEGRA210_CLK_CSUS 92 +/* 93 */ +/* 94 */ +/* 95 (bit affects xusb_dev and xusb_dev_src) */ + +/* 96 */ +/* 97 */ +/* 98 */ +#define TEGRA210_CLK_MSELECT 99 +#define TEGRA210_CLK_TSENSOR 100 +#define TEGRA210_CLK_I2S3 101 +#define TEGRA210_CLK_I2S4 102 +#define TEGRA210_CLK_I2C4 103 +#define TEGRA210_CLK_SBC5 104 +#define TEGRA210_CLK_SBC6 105 +#define TEGRA210_CLK_D_AUDIO 106 +#define TEGRA210_CLK_APBIF 107 +#define TEGRA210_CLK_DAM0 108 +#define TEGRA210_CLK_DAM1 109 +#define TEGRA210_CLK_DAM2 110 +#define TEGRA210_CLK_HDA2CODEC_2X 111 +/* 112 */ +#define TEGRA210_CLK_AUDIO0_2X 113 +#define TEGRA210_CLK_AUDIO1_2X 114 +#define TEGRA210_CLK_AUDIO2_2X 115 +#define TEGRA210_CLK_AUDIO3_2X 116 +#define TEGRA210_CLK_AUDIO4_2X 117 +#define TEGRA210_CLK_SPDIF_2X 118 +#define TEGRA210_CLK_ACTMON 119 +#define TEGRA210_CLK_EXTERN1 120 +#define TEGRA210_CLK_EXTERN2 121 +#define TEGRA210_CLK_EXTERN3 122 +#define TEGRA210_CLK_SATA_OOB 123 +#define TEGRA210_CLK_SATA 124 +#define TEGRA210_CLK_HDA 125 +/* 126 */ +#define TEGRA210_CLK_SE 127 + +#define TEGRA210_CLK_HDA2HDMI 128 +#define TEGRA210_CLK_SATA_COLD 129 +/* 130 */ +/* 131 */ +/* 132 */ +/* 133 */ +/* 134 */ +/* 135 */ +/* 136 */ +/* 137 */ +/* 138 */ +/* 139 */ +/* 140 */ +/* 141 */ +/* 142 */ +/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */ +/* xusb_host_src and xusb_ss_src) */ +#define TEGRA210_CLK_CILAB 144 +#define TEGRA210_CLK_CILCD 145 +#define TEGRA210_CLK_CILE 146 +#define TEGRA210_CLK_DSIALP 147 +#define TEGRA210_CLK_DSIBLP 148 +#define TEGRA210_CLK_ENTROPY 149 +#define TEGRA210_CLK_DDS 150 +/* 151 */ +#define TEGRA210_CLK_DP2 152 +#define TEGRA210_CLK_AMX 153 +#define TEGRA210_CLK_ADX 154 +/* 155 (bit affects dfll_ref and dfll_soc) */ +#define TEGRA210_CLK_XUSB_SS 156 +/* 157 */ +/* 158 */ +/* 159 */ + +/* 160 */ +/* 161 */ +/* 162 */ +/* 163 */ +/* 164 */ +/* 165 */ +#define TEGRA210_CLK_I2C6 166 +/* 167 */ +/* 168 */ +/* 169 */ +/* 170 */ +#define TEGRA210_CLK_VIM2_CLK 171 +/* 172 */ +/* 173 */ +/* 174 */ +/* 175 */ +#define TEGRA210_CLK_HDMI_AUDIO 176 +#define TEGRA210_CLK_CLK72MHZ 177 +#define TEGRA210_CLK_VIC03 178 +/* 179 */ +#define TEGRA210_CLK_ADX1 180 +#define TEGRA210_CLK_DPAUX 181 +#define TEGRA210_CLK_SOR0 182 +/* 183 */ +#define TEGRA210_CLK_GPU 184 +#define TEGRA210_CLK_AMX1 185 +/* 186 */ +/* 187 */ +/* 188 */ +/* 189 */ +/* 190 */ +/* 191 */ +#define TEGRA210_CLK_UARTB 192 +#define TEGRA210_CLK_VFIR 193 +#define TEGRA210_CLK_SPDIF_IN 194 +#define TEGRA210_CLK_SPDIF_OUT 195 +#define TEGRA210_CLK_VI 196 +#define TEGRA210_CLK_VI_SENSOR 197 +#define TEGRA210_CLK_FUSE 198 +#define TEGRA210_CLK_FUSE_BURN 199 +#define TEGRA210_CLK_CLK_32K 200 +#define TEGRA210_CLK_CLK_M 201 +#define TEGRA210_CLK_CLK_M_DIV2 202 +#define TEGRA210_CLK_CLK_M_DIV4 203 +#define TEGRA210_CLK_PLL_REF 204 +#define TEGRA210_CLK_PLL_C 205 +#define TEGRA210_CLK_PLL_C_OUT1 206 +#define TEGRA210_CLK_PLL_C2 207 +#define TEGRA210_CLK_PLL_C3 208 +#define TEGRA210_CLK_PLL_M 209 +#define TEGRA210_CLK_PLL_M_OUT1 210 +#define TEGRA210_CLK_PLL_P 211 +#define TEGRA210_CLK_PLL_P_OUT1 212 +#define TEGRA210_CLK_PLL_P_OUT2 213 +#define TEGRA210_CLK_PLL_P_OUT3 214 +#define TEGRA210_CLK_PLL_P_OUT4 215 +#define TEGRA210_CLK_PLL_A 216 +#define TEGRA210_CLK_PLL_A_OUT0 217 +#define TEGRA210_CLK_PLL_D 218 +#define TEGRA210_CLK_PLL_D_OUT0 219 +#define TEGRA210_CLK_PLL_D2 220 +#define TEGRA210_CLK_PLL_D2_OUT0 221 +#define TEGRA210_CLK_PLL_U 222 +#define TEGRA210_CLK_PLL_U_480M 223 + +#define TEGRA210_CLK_PLL_U_60M 224 +#define TEGRA210_CLK_PLL_U_48M 225 +#define TEGRA210_CLK_PLL_U_12M 226 +/* 227 */ +/* 228 */ +#define TEGRA210_CLK_PLL_RE_VCO 229 +#define TEGRA210_CLK_PLL_RE_OUT 230 +#define TEGRA210_CLK_PLL_E 231 +#define TEGRA210_CLK_SPDIF_IN_SYNC 232 +#define TEGRA210_CLK_I2S0_SYNC 233 +#define TEGRA210_CLK_I2S1_SYNC 234 +#define TEGRA210_CLK_I2S2_SYNC 235 +#define TEGRA210_CLK_I2S3_SYNC 236 +#define TEGRA210_CLK_I2S4_SYNC 237 +#define TEGRA210_CLK_VIMCLK_SYNC 238 +#define TEGRA210_CLK_AUDIO0 239 +#define TEGRA210_CLK_AUDIO1 240 +#define TEGRA210_CLK_AUDIO2 241 +#define TEGRA210_CLK_AUDIO3 242 +#define TEGRA210_CLK_AUDIO4 243 +#define TEGRA210_CLK_SPDIF 244 +#define TEGRA210_CLK_CLK_OUT_1 245 +#define TEGRA210_CLK_CLK_OUT_2 246 +#define TEGRA210_CLK_CLK_OUT_3 247 +#define TEGRA210_CLK_BLINK 248 +/* 249 */ +/* 250 */ +/* 251 */ +#define TEGRA210_CLK_XUSB_HOST_SRC 252 +#define TEGRA210_CLK_XUSB_FALCON_SRC 253 +#define TEGRA210_CLK_XUSB_FS_SRC 254 +#define TEGRA210_CLK_XUSB_SS_SRC 255 + +#define TEGRA210_CLK_XUSB_DEV_SRC 256 +#define TEGRA210_CLK_XUSB_DEV 257 +#define TEGRA210_CLK_XUSB_HS_SRC 258 +#define TEGRA210_CLK_SCLK 259 +#define TEGRA210_CLK_HCLK 260 +#define TEGRA210_CLK_PCLK 261 +/* 262 */ +/* 263 */ +#define TEGRA210_CLK_DFLL_REF 264 +#define TEGRA210_CLK_DFLL_SOC 265 +#define TEGRA210_CLK_VI_SENSOR2 266 +#define TEGRA210_CLK_PLL_P_OUT5 267 +#define TEGRA210_CLK_CML0 268 +#define TEGRA210_CLK_CML1 269 +#define TEGRA210_CLK_PLL_C4 270 +#define TEGRA210_CLK_PLL_DP 271 +#define TEGRA210_CLK_PLL_E_MUX 272 +#define TEGRA210_CLK_PLLD_DSI 273 +/* 274 */ +/* 275 */ +/* 276 */ +/* 277 */ +/* 278 */ +/* 279 */ +/* 280 */ +/* 281 */ +/* 282 */ +/* 283 */ +/* 284 */ +/* 285 */ +/* 286 */ +/* 287 */ + +/* 288 */ +/* 289 */ +/* 290 */ +/* 291 */ +/* 292 */ +/* 293 */ +/* 294 */ +/* 295 */ +/* 296 */ +/* 297 */ +/* 298 */ +/* 299 */ +#define TEGRA210_CLK_AUDIO0_MUX 300 +#define TEGRA210_CLK_AUDIO1_MUX 301 +#define TEGRA210_CLK_AUDIO2_MUX 302 +#define TEGRA210_CLK_AUDIO3_MUX 303 +#define TEGRA210_CLK_AUDIO4_MUX 304 +#define TEGRA210_CLK_SPDIF_MUX 305 +#define TEGRA210_CLK_CLK_OUT_1_MUX 306 +#define TEGRA210_CLK_CLK_OUT_2_MUX 307 +#define TEGRA210_CLK_CLK_OUT_3_MUX 308 +/* 309 */ +/* 310 */ +#define TEGRA210_CLK_SOR0_LVDS 311 +#define TEGRA210_CLK_XUSB_SS_DIV2 312 + +#define TEGRA210_CLK_PLL_M_UD 313 +#define TEGRA210_CLK_PLL_C_UD 314 + +#define TEGRA210_CLK_PLL_X 227 +#define TEGRA210_CLK_PLL_X_OUT0 228 + +#define TEGRA210_CLK_CCLK_G 262 +#define TEGRA210_CLK_CCLK_LP 263 + +#define TEGRA210_CLK_CLK_MAX 315 + +#endif /* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */ diff --git a/include/fdtdec.h b/include/fdtdec.h index 232360341a..4b3f8d13c3 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -137,6 +137,7 @@ enum fdt_compat_id { COMPAT_NVIDIA_TEGRA124_SOR, /* Tegra 124 Serial Output Resource */ COMPAT_NVIDIA_TEGRA124_PMC, /* Tegra 124 power mgmt controller */ COMPAT_NVIDIA_TEGRA20_DC, /* Tegra 2 Display controller */ + COMPAT_NVIDIA_TEGRA210_SDMMC, /* Tegra210 SDMMC controller */ COMPAT_NVIDIA_TEGRA124_SDMMC, /* Tegra124 SDMMC controller */ COMPAT_NVIDIA_TEGRA30_SDMMC, /* Tegra30 SDMMC controller */ COMPAT_NVIDIA_TEGRA20_SDMMC, /* Tegra20 SDMMC controller */ @@ -145,6 +146,8 @@ enum fdt_compat_id { COMPAT_NVIDIA_TEGRA20_PCIE, /* Tegra 20 PCIe controller */ COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL, /* Tegra124 XUSB pad controller */ + COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL, + /* Tegra210 XUSB pad controller */ COMPAT_SMSC_LAN9215, /* SMSC 10/100 Ethernet LAN9215 */ COMPAT_SAMSUNG_EXYNOS5_SROMC, /* Exynos5 SROMC */ COMPAT_SAMSUNG_S3C2440_I2C, /* Exynos I2C Controller */ |