diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-mips/addrspace.h | 2 | ||||
| -rw-r--r-- | include/configs/tb0229.h | 177 | ||||
| -rw-r--r-- | include/linux/byteorder/swab.h | 18 |
3 files changed, 187 insertions, 10 deletions
diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h index 845dd7c946..b8214b1c85 100644 --- a/include/asm-mips/addrspace.h +++ b/include/asm-mips/addrspace.h @@ -44,7 +44,7 @@ * Returns the uncached address of a sdram address */ #ifndef __ASSEMBLY__ -#ifdef CONFIG_AU1X00 +#if defined(CONFIG_AU1X00) || defined(CONFIG_TB0229) /* We use a 36 bit physical address map here and cannot access physical memory directly from core */ #define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000) diff --git a/include/configs/tb0229.h b/include/configs/tb0229.h new file mode 100644 index 0000000000..53fafdd6ea --- /dev/null +++ b/include/configs/tb0229.h @@ -0,0 +1,177 @@ +/* + * (C) Copyright 2003 + * Masami Komiya <mkomiya@sonare.it> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Config header file for TANBAC TB0229 board using an VR4131 CPU module + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MIPS32 1 /* MIPS 4Kc CPU core */ +#define CONFIG_TB0229 1 /* on a TB0229 Board */ + +#ifndef CPU_CLOCK_RATE +#define CPU_CLOCK_RATE 200000000 /* 200 MHz clock for the MIPS core */ +#endif +#define CPU_TCLOCK_RATE 16588800 /* 16.5888 MHz for TClock */ + +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_BAUDRATE 115200 + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"boot\" for the network boot using DHCP, TFTP and NFS;" \ + "echo Type \"run netboot_initrd\" for the network boot with initrd;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo Type \"run flash_local\" to mount local root filesystem;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netboot=dhcp;tftp;run netargs; bootm\0" \ + "nfsargs=setenv bootargs root=/dev/nfs ip=dhcp\0" \ + "localargs=setenv bootargs root=1F02 ip=dhcp\0" \ + "addmisc=setenv bootargs $(bootargs) " \ + "console=ttyS0,$(baudrate) " \ + "read-only=readonly\0" \ + "netargs=run nfsargs addmisc\0" \ + "flash_nfs=run nfsargs addmisc;" \ + "bootm $(kernel_addr)\0" \ + "flash_local=run localargs addmisc;" \ + "bootm $(kernel_addr)\0" \ + "netboot_initrd=dhcp;tftp;tftp 80600000 initrd;" \ + "setenv bootargs root=/dev/ram ramdisk_size=8192 ip=dhcp;"\ + "run addmisc;" \ + "bootm 80400000 80600000\0" \ + "rootpath=/export/miniroot-mipsel\0" \ + "autoload=no\0" \ + "kernel_addr=BFC60000\0" \ + "ramdisk_addr=B0100000\0" \ + "u-boot=u-boot.bin\0" \ + "bootfile=uImage\0" \ + "load=dhcp;tftp 80400000 $(u-boot)\0" \ + "load_kernel=dhcp;tftp 80400000 $(bootfile)\0" \ + "update_uboot=run load;" \ + "protect off BFC00000 BFC3FFFF;" \ + "erase BFC00000 BFC3FFFF;" \ + "cp.b 80400000 BFC00000 $(filesize)\0" \ + "update_kernel=run load_kernel;" \ + "erase BFC60000 BFD5FFFF;" \ + "cp.b 80400000 BFC60000 $(filesize)\0" \ + "initenv=erase bfc40000 bfc5ffff\0" \ + "" +//#define CONFIG_BOOTCOMMAND "run flash_local" +#define CONFIG_BOOTCOMMAND "run netboot" + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_PING | \ + CFG_CMD_PCI | \ + CFG_CMD_ELF ) +#include <cmd_confdefs.h> + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "# " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args*/ + +#define CFG_MALLOC_LEN 128*1024 + +#define CFG_BOOTPARAMS_LEN 128*1024 + +#define CFG_HZ (CPU_TCLOCK_RATE/4) + +#define CFG_SDRAM_BASE 0x80000000 + +#define CFG_LOAD_ADDR 0x80400000 /* default load address */ + +#define CFG_MEMTEST_START 0x80000000 +#define CFG_MEMTEST_END 0x80800000 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ + +#define PHYS_FLASH_1 0xbfc00000 /* Flash Bank #1 */ + +/* The following #defines are needed to get flash environment right */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (192 << 10) + +#define CFG_INIT_SP_OFFSET 0x400000 + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (20 * CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_ENV_IS_IN_FLASH 1 + +/* Address and size of Primary Environment Sector */ +#define CFG_ENV_ADDR 0xBFC40000 +#define CFG_ENV_SIZE 0x20000 + +#define CFG_DIRECT_FLASH_TFTP + +#define CONFIG_NR_DRAM_BANKS 1 + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 +#define CFG_ICACHE_SIZE 16384 +#define CFG_CACHELINE_SIZE 16 + +/*----------------------------------------------------------------------- + * Serial Configuration + */ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK 18432000 +#define CFG_NS16550_COM1 0xaf000800 + +/*----------------------------------------------------------------------- + * PCI stuff + */ +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_NET_MULTI +#define CONFIG_EEPRO100 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ + +#define CONFIG_RTL8139 + +#endif /* __CONFIG_H */ diff --git a/include/linux/byteorder/swab.h b/include/linux/byteorder/swab.h index 755a8212e7..03468f7086 100644 --- a/include/linux/byteorder/swab.h +++ b/include/linux/byteorder/swab.h @@ -96,34 +96,34 @@ #endif /* OPTIMIZE */ -extern __inline__ __const__ __u16 __fswab16(__u16 x) +static __inline__ __const__ __u16 __fswab16(__u16 x) { return __arch__swab16(x); } -extern __inline__ __u16 __swab16p(__u16 *x) +static __inline__ __u16 __swab16p(__u16 *x) { return __arch__swab16p(x); } -extern __inline__ void __swab16s(__u16 *addr) +static __inline__ void __swab16s(__u16 *addr) { __arch__swab16s(addr); } -extern __inline__ __const__ __u32 __fswab32(__u32 x) +static __inline__ __const__ __u32 __fswab32(__u32 x) { return __arch__swab32(x); } -extern __inline__ __u32 __swab32p(__u32 *x) +static __inline__ __u32 __swab32p(__u32 *x) { return __arch__swab32p(x); } -extern __inline__ void __swab32s(__u32 *addr) +static __inline__ void __swab32s(__u32 *addr) { __arch__swab32s(addr); } #ifdef __BYTEORDER_HAS_U64__ -extern __inline__ __const__ __u64 __fswab64(__u64 x) +static __inline__ __const__ __u64 __fswab64(__u64 x) { # ifdef __SWAB_64_THRU_32__ __u32 h = x >> 32; @@ -133,11 +133,11 @@ extern __inline__ __const__ __u64 __fswab64(__u64 x) return __arch__swab64(x); # endif } -extern __inline__ __u64 __swab64p(__u64 *x) +static __inline__ __u64 __swab64p(__u64 *x) { return __arch__swab64p(x); } -extern __inline__ void __swab64s(__u64 *addr) +static __inline__ void __swab64s(__u64 *addr) { __arch__swab64s(addr); } |