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Corrected DCR addresses of PPC440EP power management registers.
Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com>
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Reverting became necessary after it turned out that the patches in
the u-boot-arm repo were modified, and in some cases corrupted.
This reverts the following commits:
066bebd6353e33af3adefc3404560871699e9961
7a837b7310166ae8fc8b8d66d7ef01b60a80f9d6
c88ae20580b2b01487b4cdcc8b2a113f551aee36
a147e56f03871bba4f05058d5e04ce7deb010b04
d6674e0e2a6a1f033945f78838566210d3f28c95
8c8463cce44d849e37744749b32d38e1dfb12e50
c98b47ad24b2d91f41c09a3d62d7f70ad84f4b7d
8bf69d81782619187933a605f1a95ee1d069478d
8c16cb0d3b971f46fbe77c072664c0f2dcd4471d
a574a73852a527779234e73e17e7597fd8128882
1377b5583a48021d983e1fd565f7d40c89e84d63
1704dc20917b4f71e373e2c888497ee666d40380
Signed-off-by: Wolfgang Denk <wd@denx.de>
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This patch reworks the default environment on Kilauea/Haleakala. Now
"net_nfs" for exmaple uses the device-tree style booting formerly know
as "net_nfs_fdt". Also the addresses in RAM were changed because of the
new image booting support, which check for image overwriting. So the
addresses needed togeet adjusted.
Signed-off-by: Stefan Roese <sr@denx.de>
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Since the new image support checks for image overwriting, the default
environment needs to get adjusted to use correct addresses.
Signed-off-by: Stefan Roese <sr@denx.de>
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The patch 70431e8a7393b6b793f77957f95b999fc9a269b8 (Make MPC83xx one step
closer to full relocation.) doesn't use CFG_MONITOR_BASE anymore. But
on 4xx systems _start currently cannot be used for this calculation.
So revert back to the original version for now.
Signed-off-by: Stefan Roese <sr@denx.de>
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FLAGS are generated by U-BOOT generator.
Board specific FLAGS are in board directory
Signed-off-by: Michal Simek <monstr@monstr.eu>
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Signed-off-by: Michal Simek <monstr@monstr.eu>
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Signed-off-by: Michal Simek <monstr@monstr.eu>
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Signed-off-by: Michal Simek <monstr@monstr.eu>
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Signed-off-by: Michal Simek <monstr@monstr.eu>
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Signed-off-by: Michal Simek <monstr@monstr.eu>
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Signed-off-by: Michal Simek <monstr@monstr.eu>
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Signed-off-by: Michal Simek <monstr@monstr.eu>
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Signed-off-by: Michal Simek <monstr@monstr.eu>
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targets. See www.gaisler.com for information.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
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exchangeable but a standard LEON3 design is assumed. See www.gaisler.com for information.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
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Edition) with GRLIB template design. See www.gaisler.com for information.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
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See www.gaisler.com for information.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
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design. See www.gaisler.com for board information.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
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Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
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can print available cores (type: AHB Master, AHB Slave, APB Slave), their address ranges, IRQ number and version.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
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Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
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Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
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Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
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Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
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Conflicts:
lib_ppc/board.c
Signed-off-by: Wolfgang Denk <wd@denx.de>
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This patch fixes a problem with the RGMII setup of the 460GT. The 460GT
has 2 RGMII instances and we need to configure the 2nd RGMII instance
for the EMAC2+3 channels.
Signed-off-by: Stefan Roese <sr@denx.de>
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fdt.c: In function 'ft_cpu_setup':
fdt.c:33: warning: implicit declaration of function 'do_fixup_by_prop_u32'
fdt.c:39: warning: implicit declaration of function 'do_fixup_by_compat_u32'
fdt.c:43: warning: implicit declaration of function 'fdt_fixup_ethernet'
fdt.c:45: warning: implicit declaration of function 'fdt_fixup_memory'
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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The fdt set command was treating properties specified as <00> and <0011>
as byte streams, rather than as an array of cells. As we already have
syntax for expressing the desire for a stream of bytes ([ xx xx ...]),
we should use the <> syntax to describe arrays of cells, which are always
32-bits per element. If we imagine this likely (IMHO) scenario:
> fdt set /ethernet-phy@1 reg <1>
With the old code, this would create a bad fdt, since the reg cell would be
made to be one byte in length. But the cell must be 4 bytes, so this would
break mysteriously.
Also, the dts spec calls for constants inside the angle brackets (<>)
to conform to C constant standards as they pertain to base.
Take this scenario:
> fdt set /ethernet@f00 reg <0xe250000\ 0x1000>
The old fdt command would complain that it couldn't parse that. Or, if you
wanted to specify that a certain clock ran at 33 MHz, you'd be required to
do this:
> fdt set /mydev clock <1f78a40>
Whereas the new code will accept decimal numbers.
While I was in there, I extended the fdt command parser to handle property
strings which are split across multiple arguments:
> fdt set /ethernet@f00 interrupts < 33 2 34 2 36 2 >
> fdt p /ethernet@f00
ethernet@f00 {
interrupts = <0x21 0x2 0x22 0x2 0x24 0x2>;
};
Lastly, the fdt print code was rearranged slightly to print arrays of cells
if the length of the property is a multiple of 4 bytes, and to not print
leading zeros.
Signed-off-by: Andy Fleming <afleming@freescale.com>
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Canyonlands (460EX) shares the first PCIe interface with the SoC SATA
interface. This usage can be configured with the jumper J6. This patch
correctly configures the SATA/PCIe PHY for SATA usage when this jumper
is installed.
Signed-off-by: Stefan Roese <sr@denx.de>
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finish off what commit 43ddd9c820fec44816188f53346b464e20b3142d,
"Remove deprecated CONFIG_OF_HAS_UBOOT_ENV and CONFIG_OF_HAS_BD_T"
started.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Add phy_info for Vitesse VSC8601.
Add config option, CFG_VSC8601_SKEWFIX, to enable RGMII skew timing compensation.
Signed-off-by: Tor Krill <tor@excito.com>
Reviewed-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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This patch makes SPARC/LEON processors able to read and write
to the SMC91111 chip using the chip external I/O bus of the memory
controller. This patchs defines the standard in and out macros
expected by the SMC9111 driver.
To access that I/O bus one must set up the memory controller
(MCTRL or FTMCTRL) correctly. It is assumed that the user sets
up this correctly when the other MCTRL parameters are set up. It
can be set up from the board configuration header file.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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