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2017-11-28arm64: zynqmp: Add SMMU support for SATA IPAnurag Kumar Vulisha
AXI master interface in CEVA AHCI controller requires two unique Write/Read ID tags per port. This is because, ahci controller uses different AXI ID[3:0] bits for identifying non-data transfers(like reading descriptors, updating PRD tables, etc) and data transfers (like sending/receiving FIS).To make SMMU work with SATA we need to add correct SMMU stream id for SATA. SMMU stream id for SATA is determined based on the AXI ID[1:0] as shown below SATA SMMU ID = <TBU number>, 0011, 00, 00, AXI ID[1:0] Note: SATA in ZynqMp uses TBU1 so TBU number = 0x1, so SMMU ID = 001, 0011, 00, 00, AXI ID[1:0] Since we have four different AXI ID[3:0] (2 for port0 & 2 for port1 as said above) we get four different SMMU stream id's combinations for SATA. These AXI ID can be configured using PAXIC register. In this patch we assumed the below AXI ID values Read ID/ Write ID for Non-Data Port0 transfers = 0 Read ID/ Write ID for Data Port0 transfers = 1 Read ID/ Write ID for Non-Data Port1 transfers = 2 Read ID/ Write ID for Data Port1 transfers = 3 Based on the above values,SMMU stream ID's for SATA will be 0x4c0 & 0x4c1 for PORT0, 0x4c2 & 0x4c3 for PORT1. These values needed to be added to iommus dts property. This patch does the same. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: dts: xilinx: fix PCI bus dtc warningsRob Herring
dtc recently added PCI bus checks. Fix these warnings. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Add missing gpio property to dtsiMichal Simek
All gpio controllers should contain this property. This property is not checked by the code that's why this issue wasn't found earlier. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Update the GPU address sizeHyun Kwon
The correct register size is 0x10000, otherwise it overlaps with other register space. Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Add clock name for GPUMadhurkiran Harikrishnan
This patch will add names to the clocks used by GPU. Signed-off-by: Madhurkiran Harikrishnan <madhurki@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Label whole PL part as fpga_full regionNava kishore Manne
This will simplify dt overlay structure for the whole PL. Signed-off-by: Nava kishore Manne <navam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Fix broken architected timer interrupt triggerMichal Simek
Extract from Linux mainline patch: The ARM architected timer specification mandates that the interrupt associated with each timer is level triggered (which corresponds to the "counter >= comparator" condition). A number of DTs are being remarkably creative, declaring the interrupt to be edge triggered. A quick look at the TRM for the corresponding ARM CPUs clearly shows that this is wrong, and I've corrected those. For non-ARM designs (and in the absence of a publicly available TRM), I've made them active low as well, which can't be completely wrong as the GIC cannot disinguish between level low and level high. The respective maintainers are of course welcome to prove me wrong. While I was at it, I took the liberty to fix a couple of related issue, such as some spurious affinity bits on ThunderX, and their complete absence on ls1043a (both of which seem to be related to copy-pasting from other DTs). Acked-by: Duc Dang <dhdang@apm.com> Acked-by: Carlo Caione <carlo@endlessm.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: PM: Add IRQSoren Brinkmann
PM callbacks are delivered to the NS OS. Let the PM driver handle the IRQ and retrieve callback data from the secure HW. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Reduced min-residency time for idle state nodeJolly Shah
Changed min-residence to 10ms(was 100 ms) for cpu-sleep-0. Tried lower values 5ms and 8ms and it worked fine with Debug Off. But to accommodate PM Debug On case, 10 ms is required. With this change, low power idle state is into effect more frequently. Measured boot time with PM debugs On and Off. No change observed compared to 100ms value. Signed-off-by: Jolly Shah <jollys@xilinx.com> Acked-by: Will Wong <willw@xilinx.com> Tested-by: Koteswararao Nayudu <kotin@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: DT: Fix typo in idle-states node definitionJyotheeswar Reddy
Fixed a typo in specifying "entry-method" Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Update the OPPs for cpu freqShubhrajyoti Datta
Add operating-points-v2. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Add references to cpu nodesMichal Simek
Add missing references to all cpu nodes. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Wire QSPI boot mode for SPLMichal Simek
ZynqMP qspi driver is on the way to mainline Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Enable debug uart for zc1751 dc5Michal Simek
Showing uart earlier. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Add new ID for RFSoCMichal Simek
This ID is available on zc1254. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Add support for CG/EG/EV device detectionMichal Simek
Version string has unused fields 31:20 which can be used for exporting 9 bits from efuse IPDISABLE regs to recognize eg/cg/ev devices. These efuse bits are setup for certain devices. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Use u32 type instead of uint32_tMichal Simek
Warning is reported by checkpatch. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Add SD1 level shifter mode to alternative selectionMichal Simek
Extend Kconfig to cover SD1 level shifter mode. Reported-by: Jason Wu <jason.hy.wu@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Enable config DEFINE_TCM_OCM_MMAP if CONFIG_MP definedSiva Durga Prasad Paladugu
This modifies default value of config DEFINE_TCM_OCM_MMAP to yes if CONFIG_MP is defined MP supports needs OCM and TCM part of memory map. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28tools: mkimage: Extend mkimage to also include pmufwMichal Simek
The patch is adding external pmufw "Platform Management Unit firmware" to boot.bin image. Boot.bin is a Xilinx format which bootrom is capable to read and boot the system. pmufw is copied to the header data section follows by u-boot-spl.bin. pmufw is consumed by PMU unit (Microblaze) and SPL runs on a53-0. This is generated command line when PMUFW_INIT_FILE is setup. ./tools/mkimage -T zynqmpimage -R ./"" -n ./"board/xilinx/zynqmp/pmufw.bin" -d spl/u-boot-spl.bin spl/boot.bin Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-28arm64: zynqmp: Provide a Kconfig option to use specified memory for MMU tableSiva Durga Prasad Paladugu
This patch provides a Kconfig option to use specified memory for MMU table using reserve_mmu platform specific routine. Here we used TCM space for MMU table. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: mp: Correct the R5 release sequenceSiva Durga Prasad Paladugu
This patch corrects the R5 release sequence by adding the below steps. 1. Flush dcache to ensure that image loaded into memory. 2. Keep R5 reset just to ensure R5 in reset. 3. Disable caches before accessing TCM as with out this A53 can do speculative and may result in ECC failures if TCM's are not initialized. So, it is always better to disable dcaches before accessing TCM and enable back. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Reported-by: John Linn <linnj@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Remove slcr with mio status pin detectionMichal Simek
This code is not used on this platform and it is not called. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28ata: Fix ahci wordingMichal Simek
s/achi_/ahci_/g Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-28arm: zynq: Add mini u-boot configuration for zynqMichal Simek
Add configuration files/dtses for mini u-boot configurations which runs out of OCM. ram top is calculated from 0 that's why +#define CONFIG_SYS_SDRAM_BASE 0xfffc0000 +#define CONFIG_SYS_SDRAM_SIZE 0x40000 was hardcoded. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-28arm: zynq: Sort dts namesMichal Simek
Sort names. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-28arm: zynq: Move ZYNQ_SERIAL to KconfigMichal Simek
Move cadence/zynq serial driver via Kconfig Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-28arm: zynq: Enable FPGA/FPGA_XILINX via KconfigMichal Simek
Enabling fpga via Kconfig. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm: zynq: Return value from fdtdec_setup_memory_banksize directlyMichal Simek
There is no reason not to return return value from above function. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm: zynq: Add board support for cc108Michal Simek
cc108 board is wiring uart via PL which is good platform for SPL fpga support. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-28arm: zynq: Enable qspi for zc770_xm013Michal Simek
Enable qspi driver and flashes for this board. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm: zynq: Enable MACRONIX flash for zc702/zc706/zc770 xm010Michal Simek
Enable MACRONIX flash for boards with QSPI enabled. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm: zynq: Enable debug console on zc770 xm010 by defaultMichal Simek
Enable debug console. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm: zynq: Enable bootz command for Xilinx platformsMichal Simek
bootz command is valid way how to boot Linux kernel. Enable it by default. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm: zynq: Sync location of DT properties with LinuxMichal Simek
This is trival change which only ensures the same location with Linux kernel. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm: zynq: Remove empty ifdef env structures from config fileMichal Simek
All these configs were moved to Kconfig that's why this empty ifdef structure is not needed anymore. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm: zynq: Add device-type property for zynq ethernet phy nodesSai Pavan Boddu
Mention device-type = "ethernet-phy", as qemu will need this in absence of compatible. Signed-off-by: Sai Pavan Boddu <saipava@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm: zynq: Add SCL & SDA GPIO entries for recoveryChirag Parekh
Wire i2c pinmuxing gpio recovery for zc702. Signed-off-by: Chirag Parekh <chiragp@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28mtd: nand: zynq: Add a config option to use 1st stage bootloader timingJeff Westfahl
In legacy method, 1st stage bootloader was used to configure the HW setting such as NAND timing. Hence, adding a config option in Zynq NAND driver for the compatibility of device that using 1st stage bootloder instead of U-boot SPL. This commit is to add config option CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS that allow NAND driver use timing values set by the 1st stage bootloader, instead of the hard-coded values in the Zynq NAND driver. Signed-off-by: Jeff Westfahl <jeff.westfahl@ni.com> Signed-off-by: Wilson Lee <wilson.lee@ni.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Keng Soon Cheah <keng.soon.cheah@ni.com> Cc: Chen Yee Chew <chen.yee.chew@ni.com> Cc: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Scott Wood <oss@buserror.net> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm: zynq: Add support for SYZYGY Hub boardTom McLeod
Add the Zynq-based SYZYGY Hub board from Opal Kelly. The board contains a Xilinx Zynq xc7z012s SoC, 1GB DDR3 RAM, and supports booting from SD. Signed-off-by: Tom McLeod <tom.mcleod@opalkelly.com> Cc: Michal Simek <monstr@monstr.eu> CC: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: remove unnecessary logical constraintHeinrich Schuchardt
In if (a || b) else if (!a) the constraint (!a) is always true if else is reached and can be removed. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-27test: Correct operation when tests passSimon Glass
When tests pass an error message is printed because of a variable that is not initialised. Fix this. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-11-27spl: TI: Do not default to SPL_FIT_IMAGE_TINY being enabledTom Rini
This option prevents booting on am335x_evm at least along with most likely other platforms. Fixes: 337bbb629777 ("spl: fit: add SPL_FIT_IMAGE_TINY config to reduce code-size") Signed-off-by: Tom Rini <trini@konsulko.com>
2017-11-27Merge git://www.denx.de/git/u-boot-imxTom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-11-27configs: icore-rqs: Enable falcon modeJagan Teki
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-11-27engicam: imx6q: Return mmc dev 0 for icoreJagan Teki
icorem6 has sd on usdhci1 which is devno 0 so return proper devno from board_mmc_get_env_dev for icorem6 and icorem_6rqs Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-11-27i.MX6: engicam: Add imx6q/imx6ul boards for existing boardsJagan Teki
Add new board names for existing board support imx6q - icore and icore_rqs boards imx6ul - geam6ul and isiot boards Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-11-27board: icore-rqs: Fix mmc get env deviceJagan Teki
As per USDHC boot eFUSE descriptions: USDHC3 => devno 2 USDHC4 => devno 3 Linux will detect mmc0, mmc1, mmc2 based on the status "okay" on usdhc so imx6qdl-icore-rqs.dtsi has enabled usdhc1, usdhc3 and usdhc4.But U-Boot can detect based on the aliases so add mmc1, mmc2 for usdhc3 and usdhc4 respectively and return the board_mmc_get_env_dev by subtracting -1 Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-11-27i.MX6UL: icore: Add SPL_OF_CONTROL supportJagan Teki
Add OF_CONTROL support for SPL code. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-11-27pinctrl: imx6ul: Fix pinctrl data overlapped with DT areaJagan Teki
before relocation pinctrl data BSS is overlapping DT area, when .data is using uninitialized global variable, imx6_pinctrl_soc_info. So assign them flags ZERO_OFFSET_VALID to prevent BSS overlap Suggested-by: Lokesh Vutla <lokeshvutla@ti.com> Reported-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
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