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2018-11-26riscv: complete the list of exception codesLukas Auer
Only the first four exception codes are defined. Add the missing exception codes from the definition in RISC-V Privileged Architecture Version 1.10. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-26riscv: do not reimplement generic io functionsLukas Auer
RISC-V U-Boot reimplements the generic io functions from asm-generic/io.h. Remove the redundant implementation and include the generic io.h instead. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-26riscv: make use of the barrier functions from LinuxLukas Auer
Replace the barrier functions in arch/riscv/include/asm/io.h with those defined in barrier.h, which is imported from Linux. This version is modified to remove the include statement of asm-generic/barrier.h, which is not available in U-Boot or required. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-26riscv: fix use of incorrectly sized variablesLukas Auer
The RISC-V arch incorrectly uses 32-bit instead of 64-bit variables in several places. Fix this. In addition, BITS_PER_LONG is set to 64 on RV64I systems. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-11-26riscv: enable -fdata-sectionsLukas Auer
Enable the -fdata-sections compiler option for RISC-V. Buildman reports the binary size decrease from this as 8365.3 bytes. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-26riscv: set -march and -mabi based on the Kconfig configurationLukas Auer
Use the new Kconfig entries to construct the ISA string for the -march compiler flag. The -mabi compiler flag is selected based on the base integer instruction set. With this change, the C (compressed instructions) ISA extension is now enabled for all boards with CONFIG_RISCV_ISA_C set. Buildman reports a decrease in binary size of 71590 bytes. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-11-26riscv: add Kconfig entries for the C and A ISA extensionsLukas Auer
Add Kconfig entries for the C (compressed instructions) and A (atomic instructions) ISA extensions. Only the C ISA extension is selectable. This matches the configuration in Linux. The Kconfig entries are not used yet. A follow-up patch will select the appropriate compiler flags based on the Kconfig configuration. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-11-26riscv: select CONFIG_PHYS_64BIT on RV64I systemsLukas Auer
CONFIG_PHYS_64BIT should be enabled on RV64I systems. Select it. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-26riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64ILukas Auer
RISC-V defines the base integer instruction sets as RV32I and RV64I. Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_RV64I to match this convention. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-26dts: riscv: update makefile to also clean the RISC-V dts directoryLukas Auer
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-26tools: .gitignore: add prelink-riscvLukas Auer
Ignore tools/prelink-riscv. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-23Merge tag 'pull-tg18' of git://git.denx.de/u-boot-dmTom Rini
Various minor sandbox improvements Better buildman warning handling Misc other things
2018-11-23sun8i_emac: add support for setting EMAC TX/RX delayIcenowy Zheng
Some boards have the EMAC TX/RX lanes wired with a different length with the clock lane, which can be workarounded by setting a TX/RX delay in the EMAC. This kind of delays are already defined in the newest device tree binding of dwmac-sun8i, which has already entered linux-next. Add support for setting these delays. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-11-22sunxi: Fix memory 2-rank initialization for a33 cpuMichael Trimarchi
When we initialize the memory we need to autodetect rank and size but this can happen only if we send the proper reset to both memory module including cke signal. For this reason we need initialize the physical on both channel because we need to presume that both are connected. This way let the CLKE to be activated at the right time with the memory reset coming from the cpu Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-11-22sunxi-mmc: use new mode on both controllers on A64Vasily Khoruzhick
Using new mode improves stability of eMMC and SD cards. Without it SPL fails to load u-boot from SD on Pinebook. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # Amarula A64-Relic Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-11-22sunxi-mmc: don't double clock for new mode unconditionallyVasily Khoruzhick
Comment in Linux driver says that clock needs to be doubled only if we use DDR modes, moreover divider has to be set accordingly. U-boot driver doesn't declare support for any DDR modes and doesn't set internal clock divider in CLKCR, so it doubles clock unconditionally when new mode is used. Some cards can't handle that and as result SPL fails to load u-boot. Fixes: de9b1771c3b ("mmc: sunxi: Support new mode") Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # Amarula A64-Relic
2018-11-22sunxi-mmc: introduce new MMC_SUNXI_HAS_MODE_SWITCH optionVasily Khoruzhick
Allwinner A64 has new mode but doesn't have a mode switch in CCM, and CCM_MMC_CTRL_MODE_SEL_NEW is not defined, so compilation fails if MMC_SUNXI_HAS_NEW_MODE is enabled Introduce new MMC_SUNXI_HAS_MODE_SWITCH option to be able to ifdef usage of CCM_MMC_CTRL_MODE_SEL_NEW Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> [jagan: update commit message] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # Amarula A64-Relic
2018-11-20sf: Add a method to obtain the block-protect settingSimon Glass
It is useful to obtain the block-protect setting of the SPI flash, so we know whether it is fully open or (perhaps partially) write-protected. Add a method for this. Update the sandbox driver to process this operation and add a test. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20test: sf: Add a simple SPI flash testSimon Glass
The current test is a functional test, covering all the way from the command line to the sandbox SPI driver. This is useful, but it is easier to diagnose failures with a smaller test. Add a simple test which reads and writes data and checks that it is stored and retrieved correctly. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20misc: Update read() and write() methods to return bytes xferedSimon Glass
At present these functions return 0 on success. For some devices we want to know how many bytes were transferred. It seems useful to adjust the API to be more like the POSIX read() and write() functions. Update these two methods, a test and all users. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-11-20string: Include the config headerSimon Glass
At present the config header is not included in this file, but it does use a CONFIG option. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20video: Update video_set_default_colors() to support invertSimon Glass
It is useful to be able to invert the colours in some cases so that the text matches the background colour. Add a parameter to the function to support this. It is strange that function takes a private data structure from another driver as an argument. It seems better to pass the device and have the function internally work out how to find its required information. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20binman: Set the pathname correctly for ELF filesSimon Glass
At present, stripped files don't have the right pathname which means that blob compression cannot be used. Fix this. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20binman: Drop an unnecessary comma in blob handlingSimon Glass
This comma is not needed. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20binman: Add a way to enable debugging from the buildSimon Glass
When the build fails due to something wrong in binman it is sometimes useful to get a full backtrace showing the location of the failure. Add a BINMAN_DEBUG environment variable to support this along with some documentation. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20spl: lz4: Allow use of lz4 compression in SPLSimon Glass
In some cases U-Boot is compressed and it is useful to be able to decompress it in SPL. Add a Kconfig and Makefile change to allow this. Note that this does not actually implement decompression. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20spl: Support bootstage, log, hash and early malloc in TPLSimon Glass
At present these features are supported in SPL but not TPL. Update the Kconfig and Makefile to allow this. Also add a few Makefile comments to make earier to track what is going on. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20sandbox: Update some drivers to work in SPL/TPLSimon Glass
At present sandbox drivers are mostly not used before relocation. Some of these are needed by Chromium OS verified boot, since it uses sandbox TPL, so update them accordingly. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20sandbox: cros_ec: exynos: Drop use of cros_ec_get_error()Simon Glass
This function is really just a call to uclass_get_device() and there is no reason why the caller cannot do it. Update sandbox and snow accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Minkyu Kang <mk7.kang@samsung.com>
2018-11-20sandbox: Add a function to read a host fileSimon Glass
Add a way to read a file from the host filesystem. This can be useful for reading test data, for example. Also fix up the writing function which was not the right version, and drop the debugging lines. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20sandbox: log: Add a category for sandboxSimon Glass
It seems useful to make sandbox its own log category since it is used for so much testing. Add this as a new category. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20sandbox: tpm: Allow debugging of data packagesSimon Glass
This is not normally useful, so change the code to avoid writing out every data package. This can be enabled with #define DEBUG. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20cros_ec: Add new features for events and powerSimon Glass
This adds new commands to the EC related to setting and clearing events as well as controlling power-related settings. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20cros_ec: Align uclass data to a cache boundarySimon Glass
The LPC driver expects its buffer to be word-aligned. Add the required flag to the uclass driver to ensure this. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20cros_ec: Fail if we cannot determine the flash burst sizeSimon Glass
This value is required for flashing to work correctly. Add a check for it. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20cros_ec: Add error logging on a few commandsSimon Glass
Add some more logging to provide more information on failures. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20cros_ec: Use uint instead of u8 for parametersSimon Glass
There is no advantage to using a u8 for function parameters. It forces the compiler to mask values and can increase code size. Also the command enum has been extended to 16 bits. Update the functions to use uint instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20buildman: Show boards with warning with w+Simon Glass
At present we should boards with warnings in the same way as those with errors. This is not ideal. Add a new 'warn' state and show these listed in yellow to match the actual warning lines printing with -e. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20buildman: Rename the good, better, worse variablesSimon Glass
At present we don't distinguish between errors and warnings when printing the architecture summary. Rename the variables to better describe their purpose. 'Worse' at present means we got an error, so use that as the name. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20buildman: Detect dtc warningsSimon Glass
At present messages from the device-tree compiler like this: arch/arm/dts/socfpga_arria10_socdk_sdmmc.dtb: Warning (avoid_unnecessary_addr_size): /clocks: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property are detected as errors since they don't match the gcc warning regex. Add a new one for dtc to fix this. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20buildman: Only print toolchain probing with -vSimon Glass
At present --list-tool-chains prints a lot of information about the toolchain-probing process. This is generally not very interesting. Update buildman to print this only if --list-tool-chains is given with -v. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20dm: spi: prevent setting a speed of 0 HzSimon Goldschmidt
When the device tree is missing a correct spi slave description below the bus (compatible "spi-flash" or spi-max-frequency are missing), the 'set_speed' callback can be called with 'speed' == 0 Hz. At least with cadence qspi, this leads to a division by zero. Prevent this by initializing speed to 100 kHz in this case (same fallback value as is done in 'dm_spi_claim_bus') and issue a warning to console. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-20fdt: restore board_fdt_blob_setup() declarationBaruch Siach
Commit 90c08fa038451d (fdt: Add device tree memory bindings) removed the prototype declaration of board_fdt_blob_setup(), most likely by mistake. This didn't break the build because the only file calling this function (lib/fdtdec.c) provides a local weak definition. Restore the declaration. Cc: Michael Pratt <mpratt@chromium.org> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-20cmd: fdt: Fix fdt address information after the movementHiroyuki Yokoyama
This patch fixes the address information of fdt. wrong case: => fdt addr 0x48000000 => fdt move 0x48000000 0x41000000 0xa000 => fdt addr The address of the fdt is 48000000 Active address in this case is 0x41000000. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Pantelis Antoniou <pantelis.antoniou@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-20fdt: Fix uncompress_blob() for U-Boot properMarek Vasut
When U-Boot proper is compiled with CONFIG_MULTI_DTB_FIT and tries to call uncompress_blob(), it fails with -ENOTSUPP. This is because the full implementation of this function which includes compression is available only in SPL. In U-Boot proper or if the compression is not enabled, the blob is not compressed and thus can be passed to locate_dtb_in_fit() in fdtdec_setup() without any changes. Pass the blob without any changes if compression is not enabled instead of failing. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-20dm: core: Widen the dump tree to show more of the driver's name.Liviu Dudau
With drivers that have prefix names that are quite long (like 'versatile_') it is useful to have a wider column for the driver's name when dumping the device driver tree. Also update the tests to take into account the wider output format. Signed-off-by: Liviu Dudau <liviu.dudau@foss.arm.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-20sandbox: README: use setenv ethrotate noHeinrich Schuchardt
If we want to control which network interface is actually used, we have to issue 'setenv ethrotate no'. If ethrotate is not set any interface may be used. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-20sandbox: README: setting environment variablesHeinrich Schuchardt
The command to set environment variables is setenv. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-20sandbox: remove stray DEBUGHeinrich Schuchardt
DEBUG should not be defined in production code. Change printf() to debug() where this writes a debug message. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-20dm/pci: Change the first CFG read to Vendor ID in enumerationHou Zhiqiang
As the PCIe specification recommend reading the Vendor ID register to determine if a Function is present, read the Vendor ID of a non-existent Function must not result in system error, so we'd better make the first CFG read to Vendor ID instead of Header Type register in the PCIe enumeration. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>