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2020-01-30cmd/gpt: Address error cases during gpt rename more correctlyTom Rini
New analysis by the tool has shown that we have some cases where we weren't handling the error exit condition correctly. When we ran into the ENOMEM case we wouldn't exit the function and thus incorrect things could happen. Rework the unwinding such that we don't need a helper function now and free what we may have allocated. Fixes: 18030d04d25d ("GPT: fix memory leaks identified by Coverity") Reported-by: Coverity (CID: 275475, 275476) Cc: Alison Chaiken <alison@she-devel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Jordy <jordy@simplyhacker.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-29Merge tag 'for-v2020.04' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2cTom Rini
i2c changes for 2020.04 - updates the Designware I2C driver - get timings from device tree - handle units in nanoseconds - make sure that the requested bus speed is not exceeded - few smaller clean-ups - adds enums for i2c speed and update drivers which use them - global_data: remove unused mxc_i2c specific field
2020-01-28Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-samsungTom Rini
- Various exynos fixes
2020-01-28Prepare v2020.04-rc1Tom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-01-27Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-spiTom Rini
- spi cs accessing slaves (Bin Meng) - spi prevent overriding established bus (Marcin Wojtas) - support speed in spi command (Marek Vasut) - add W25N01GV spinand (Robert Marko) - move cadence_qspi to use spi-mem (Vignesh Raghavendra) - add octal mode (Vignesh Raghavendra)
2020-01-28arm: exynos: odroid: Change autoboot script to use ${mmcbootdev}Marek Szyprowski
This fixes the default boot command for the SD-card boot case. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2020-01-27Merge branch '2020-01-27-master-imports'Tom Rini
- Add Dialog DA9063 PMIC support - s35392a RTC bugfix - Allow for opt-in of removal of DTB properties from the resulting binary.
2020-01-27pmic: allow dump command for non contiguous register mapsMartin Fuzzey
Some PMICs (such as the DA9063) have non-contiguous register maps. Attempting to read the non implemented registers returns an error rather than a dummy value which causes 'pmic dump' to terminate prematurely. Fix this by allowing the PMIC driver to return -ENODATA for such registers, which will then be displayed as '--' by pmic dump. Use a single error code rather than any error code so that we can distinguish between a hardware failure reading the PMIC and a non implemented register known to the driver. Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
2020-01-27power: regulator: add driver for Dialog DA9063 PMICMartin Fuzzey
Add a driver for the regulators in the the DA9063 PMIC. Robert Beckett: move regulator modes to header so board code can set modes. Correct mode mask used in ldo_set_mode. Add an option CONFIG_SPL_DM_REGULATOR_DA9063. Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group> Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
2020-01-27power: pmic: add driver for Dialog DA9063 PMICMartin Fuzzey
This adds the basic register access operations and child regulator binding (if a regulator driver exists). Robert Beckett: simplify accesses by using bottom bit of address as offset overflow. This avoids the need to track which page we are on. Add an option CONFIG_SPL_DM_PMIC_DA9063. Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group> Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
2020-01-27rtc: s35392a: encode command correctlyIan Ray
The 3-bit "command", or register, is encoded within the device address. Configure the device accordingly, and pass command in DM I2C read/write calls correctly. Signed-off-by: Ian Ray <ian.ray@ge.com> Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
2020-01-27cmd: sata: Add block unbind device functionPeng Ma
If we didn't unbind the sata from block device, the same devices would be added after sata remove, This patch is to resolve this issue as below: => sata info SATA#0: (3.0 Gbps) SATA#1: (3.0 Gbps) Device 0: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005PY30 Type: Hard Disk Supports 48-bit addressing Capacity: 286168.1 MB = 279.4 GB (586072368 x 512) Device 1: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005VX30 Type: Hard Disk Supports 48-bit addressing Capacity: 286168.1 MB = 279.4 GB (586072368 x 512) => sata stop => sata info SATA#0: (3.0 Gbps) SATA#1: (3.0 Gbps) Device 0: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005PY300 Type: Hard Disk Supports 48-bit addressing Capacity: 286168.1 MB = 279.4 GB (586072368 x 512) Device 1: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005VX300 Type: Hard Disk Supports 48-bit addressing Capacity: 286168.1 MB = 279.4 GB (586072368 x 512) Device 2: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005PY300 Type: Hard Disk Supports 48-bit addressing Capacity: 286168.1 MB = 279.4 GB (586072368 x 512) Device 3: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005VX300 Type: Hard Disk Supports 48-bit addressing Capacity: 286168.1 MB = 279.4 GB (586072368 x 512) Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-01-27tbs2910: add custom CONFIG_OF_REMOVE_PROPS list to defconfigAnatolij Gustschin
This shrinks the image size: all -3840.0 text -3840.0 Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Soeren Moch <smoch@web.de>
2020-01-27dts: add property removal option CONFIG_OF_REMOVE_PROPSAnatolij Gustschin
This can be used for device tree size reduction similar as CONFIG_OF_SPL_REMOVE_PROPS option. Some boards must pass the built-in DTB unchanged to the kernel, thus we may not cut it down unconditionally. Therefore enable the property removal list option only if CONFIG_OF_DTB_PROPS_REMOVE is selected. Signed-off-by: Anatolij Gustschin <agust@denx.de>
2020-01-28arm: exynos: Read default MMC device from XOM[7:5] pinsMarek Szyprowski
XOM pins provide information for iROM bootloader about the boot device. Those pins are mapped to lower bits of OP_MODE register (0x10000008), which is common for all Exynos SoC variants. Set the default MMC device id to reflect the boot device selected by XOM[7:5] pins (2 for the SD or 0 for the eMMC). Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2020-01-27spi: cadence-qspi: Add compatible for TI AM654Vignesh Raghavendra
TI's AM654 SoC has a Cadence OSPI IP. Add a new compatible string for the same. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27spi: cadence-qspi: Add support for Cadence Octal SPI controllerVignesh Raghavendra
Cadence OSPI is similar to QSPI IP except that it supports Octal IO (8 IO lines) flashes. Add support for Cadence OSPI IP with existing driver using new compatible Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27mtd: spi-nor-core: Add octal mode supportVignesh Raghavendra
Add support for Octal flash devices. Octal flash devices use 8 IO lines for data transfer. Currently only 1-1-8 Octal Read mode is supported. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27spi: cadence-qspi: Add direct mode supportVignesh Raghavendra
Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27spi: cadence_qspi: Move to spi-mem frameworkVignesh Raghavendra
Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27mtd: spinand: winbond: Add support for W25N01GVRobert Marko
Linux has supported W25N01GV for a long time, so lets import it. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27spi: ti_qspi: Add support for CS other than CS0Vignesh Raghavendra
Make sure corresponding setup registers are updated depending on CS. This ensures that driver can support QSPI flashes on ChipSelects other than on CS0 Reported-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27spi: prevent overriding established bus settingsMarcin Wojtas
The SPI stack relies on a proper bus speed/mode configuration by calling dm_spi_claim_bus(). However the hitherto code allowed to accidentally override those settings in the spi_get_bus_and_cs() routine. The initially established speed could be discarded by using the slave platdata, which turned out to be an issue on the platforms whose slave maximum supported frequency is not on par with the maximum frequency of the bus controller. This patch fixes above issue by configuring the bus from spi_get_bus_and_cs() only in case it was not done before. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27cmd: spi: Permit setting bus frequencyMarek Vasut
The 'sspi' command hard-coded 1 MHz bus frequency for all transmissions. Allow changing that at runtime by specifying '@freq' bus frequency in Hz. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27test: dm: spi: Fix sandbox dm_test_spi_find()Bin Meng
Per sandbox_cs_info(), sandbox spi controller only supports chip select 0. Current test case tries to locate devices on chip select 1, and any call to spi_get_bus_and_cs() or spi_cs_info() with cs number 1 should not return 0. This updates the test case to handle it correctly. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27dm: spi: Check cs number before accessing slavesBin Meng
Add chip select number check in spi_find_chip_select(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # SoPine
2020-01-27spi: nxp_fspi: new driver for the FlexSPI controllerMichael Walle
This is a port of the kernel's spi-nxp-fspi driver. It uses the new spi-mem interface and does not expose the more generic spi-xfer interface. The source was taken from the v5.3-rc3 tag. The port was straightforward: - remove the interrupt handling and the completion by busy polling the controller - remove locks - move the setup of the memory windows into claim_bus() - move the setup of the speed into set_speed() - port the device tree bindings from the original fspi_probe() to ofdata_to_platdata() There were only some style change fixes, no change in any logic. For example, there are busy loops where the return code is not handled correctly, eg. only prints a warning with WARN_ON(). This port intentionally left most functions unchanged to ease future bugfixes. This was tested on a custom LS1028A board. Because the LS1028A doesn't have proper clock framework support, changing the clock speed was not tested. This also means that it is not possible to change the SPI speed on LS1028A for now (neither is it possible in the linux driver). Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Kuldeep Singh <kuldeep.singh@nxp.com>
2020-01-27Merge tag 'u-boot-clk-26Jan2020' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-clk - Various clock fixes and enhancements
2020-01-27i2c: designware_i2c: Do more in the probe() methodSimon Glass
Move some of the code currently in the ofdata_to_platdata() method to probe() so that it is not executed when generating ACPI tables. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-27i2c: designware_i2c: Separate out the speed calculationSimon Glass
We want to be able to calculate the speed separately from actually setting the speed, so we can generate the required ACPI tables. Split out the calculation into its own function. Drop the double underscore on __dw_i2c_set_bus_speed while we are here. That is reserved for compiler internals. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-27i2c: designware_i2c: Move dw_i2c_speed_config to headerSimon Glass
This is used to store the speed information for a bus. We want to provide this to ACPI so that it can tell the kernel. Move this struct to the header file so it can be accessed by the ACPI i2c implementation being added later. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-27i2c: designware_i2c: Add support for fast-plus speedSimon Glass
Fast-plus runs at 1MHz and is used by some devices. Add support for this. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-27i2c: Update drivers to use enum for speedSimon Glass
Convert the obvious uses of i2c bus speeds to use the enum. Use livetree access for code changes. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27i2c: stm32: Update to use standard enums for speedSimon Glass
Update this driver to use the new standard enums for speed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27i2c: omap: Update to use standard enums for speedSimon Glass
Update this driver to use the new standard enums for speed. Note: This driver needs to move to driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27i2c: kona_i2c: Update to use standard enums for speedSimon Glass
Update this driver to use the new standard enums for speed. Note: This driver needs to move to driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27i2c: designware_i2c: Update to use standard enums for speedSimon Glass
Update this driver to use the new standard enums for speed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27i2c: ast_i2c: Update to use standard enums for speedSimon Glass
Update this driver to use the new standard enums for speed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27i2c: Add enums for i2c speed and address sizeSimon Glass
Some drivers define their own speed enums and use their own constants for speed. It makes sense to have a unified defition of the different speeds. Since many controllers have to do different things for fast/high speed, it is a good idea to have an enum for the mode. Add these as well as an enum for the address mode. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27i2c: designware_i2c: Add spike supressionSimon Glass
Some versions of this peripheral include a spike-suppression phase of the bus. Add support for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27i2c: designware_i2c: Rewrite timing calculationSimon Glass
At present the driver can end up with timing parameters which are slightly faster than those expected. It is possible to optimise the parameters to get the best possible result. Create a new function to handle the timing calculation. This uses a table of defaults for each speed mode rather than writing it in code. The function works by calculating the 'period' of each bit on the bus in terms of the input clock to the controller (IC_CLK). It makes sure that the constraints are met and that the different components of that period add up correctly. This code was taken from coreboot which has ended up with this same driver, but now in a much-different form. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27i2c: designware_i2c: Put hold config in a structSimon Glass
Create a struct to hold the three timing parameters. This will make it easier to move these calculations into a separate function in a later patch. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27i2c: designware_i2c: Drop scl_sda_cfg parameterSimon Glass
Instead of passing this parameter into __dw_i2c_set_bus_speed(), pass in the driver's private data, from which the function can obtain that information. This allows the function to have access to the full state of the driver. Signed-off-by: Sicomp_param1mon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-27i2c: designware_i2c: Read device-tree propertiesSimon Glass
The i2c controller defines a few timing properties. Read these in and store them for use by the driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27i2c: designware_i2c: Bring in the binding fileSimon Glass
Bring in this file from Linux v5.4. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27i2c: designware_i2c: Use an accurate bus clock instead of MHzSimon Glass
At present the driver uses an approximation for the bus clock, e.g. 166MHz instead of 166 2/3 MHz. This can result in small errors in the resulting I2C speed, perhaps 0.5% or so. Adjust the existing code to start from the accurate figure, even if later rounding reduces this accuracy. Update the bus speed code to work in KHz instead of MHz, which removes most of the error. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27i2c: designware_i2c: Use an enum for selected speed modeSimon Glass
Group these #defines into an enum to make it easier to understand the relationship between them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jun Chen <ptchentw@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27i2c: designware_i2c: Rename 'max' speed to 'high' speedSimon Glass
Some SoCs support a higher speed than what is currently called 'max' in this driver. Rename it to 'high' speed, which is the official name of the 3.4MHz speed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jun Chen <ptchentw@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27i2c: designware_i2c: Include clk.h in the header fileSimon Glass
We use struct clk here so really should include this header file to avoid build errors. Also switch the order of clk.h in the C file to match the required code style. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jun Chen <ptchentw@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27i2c: designware_i2c: Don't allow changing IC_CLKSimon Glass
If a different input clock is required then the correct way to do this is with a clock driver. Don't allow boards to override IC_CLK. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
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