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2020-02-01ARM: uniphier: set gd->ram_base correctlyMasahiro Yamada
gd->ram_base is not set at all if the end address of the DRAM ch0 exceeds the 4GB limit. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-01mtd: rawnand: denali_dt: use UCLASS_MTD instead of UCLASS_MISCMasahiro Yamada
UCLASS_MTD is a better fit for NAND drivers. Make NAND_DENALI_DT depend on DM_MTD, which is needed to compile drivers/mtd/mtd-uclass.c Also, make ARCH_UNIPHIER select DM_MTD because all the defconfig of this platform enables NAND_DENALI_DT. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
2020-02-01ARM: uniphier: remove adhoc reset deassertion for the NAND controllerMasahiro Yamada
Now that the reset controlling of the Denali NAND driver (denali_dt.c) works for this platform, remove the adhoc reset deassert code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-01mtd: rawnand: denali: set SPARE_AREA_SKIP_BYTES based on DT compatibleMasahiro Yamada
Currently, the denali NAND driver in U-Boot configures the SPARE_AREA_SKIP_BYTES based on the CONFIG option. Recently, Linux kernel merged a patch that associates the proper value for this register with the DT compatible string. Do likewise in U-Boot too. The denali_spl.c still uses CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-01mtd: rawnand: denali_dt: insert udelay() after reset deassertMasahiro Yamada
When the reset signal is de-asserted, the HW-controlled bootstrap starts running unless it is disabled in the SoC integration. It issues some commands to detect a NAND chip, and sets up registers automatically. Until this process finishes, software should avoid any register access. Without this delay function, some of UniPhier boards hangs up while executing nand_scan_ident(). (denali_read_byte() is blocked) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-01mtd: rawnand: denali: Do not reset the block before booting the kernelMarek Vasut
The Denali NAND driver in mainline Linux currently cannot deassert the reset. The upcoming Linux 5.6 will support the reset controlling, and also set up SPARE_AREA_SKIP_BYTES correctly. So, the Denali driver in the future kernel will work without relying on any bootloader or firmware. However, we still need to take care of stable kernel versions for a while. U-boot should not assert the reset of this controller. Fixes: ed784ac3822b ("mtd: rawnand: denali: add reset handling") Signed-off-by: Marek Vasut <marex@denx.de> [yamada.masahiro: reword the commit description] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-01mtd: rawnand: denali_dt: make the core clock optionalMasahiro Yamada
The "nand_x" and "ecc" clocks are currently optional. Make the core clock optional in the same way. This will allow platforms with no clock driver support to use this driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Tested-by: Marek Vasut <marex@denx.de> # On SoCFPGA Arria V
2020-02-01mtd: rawnand: denali-spl: Add missing hardware init on SoCFPGAMarek Vasut
On Altera SoCFPGA, upon either cold-boot or power-on reset, the Denali NAND IP is initialized by the BootROM ; upon warm-reset, the Denali NAND IP is NOT initialized by BootROM. In fact, upon warm-reset, the SoCFPGA BootROM checks whether the SPL image in on-chip RAM is valid and if so, completely skips re-loading the SPL from the boot media. This does sometimes lead to problems where the software left the boot media in inconsistent state before warm-reset, and because the BootROM does not reset the boot media, the boot media is left in this inconsistent state, often until another component attempts to access the boot media and fails with an difficult to debug failure. To mitigate this problem, the SPL on Altera SoCFPGA always resets all the IPs on the SoC early on boot. This results in a couple of register values, pre-programmed by the BootROM, to be lost during this reset. To restore correct operation of the IP on SoCFPGA, these values must be programmed back into the controller by the driver. Note that on other SoCs which do not use the HW-controlled bootstrap, more registers may have to be programmed. This also aligns the SPL behavior with the full Denali NAND driver, which sets these values in denali_hw_init(). Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-01-28Prepare v2020.04-rc1Tom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-01-27Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-spiTom Rini
- spi cs accessing slaves (Bin Meng) - spi prevent overriding established bus (Marcin Wojtas) - support speed in spi command (Marek Vasut) - add W25N01GV spinand (Robert Marko) - move cadence_qspi to use spi-mem (Vignesh Raghavendra) - add octal mode (Vignesh Raghavendra)
2020-01-27Merge branch '2020-01-27-master-imports'Tom Rini
- Add Dialog DA9063 PMIC support - s35392a RTC bugfix - Allow for opt-in of removal of DTB properties from the resulting binary.
2020-01-27pmic: allow dump command for non contiguous register mapsMartin Fuzzey
Some PMICs (such as the DA9063) have non-contiguous register maps. Attempting to read the non implemented registers returns an error rather than a dummy value which causes 'pmic dump' to terminate prematurely. Fix this by allowing the PMIC driver to return -ENODATA for such registers, which will then be displayed as '--' by pmic dump. Use a single error code rather than any error code so that we can distinguish between a hardware failure reading the PMIC and a non implemented register known to the driver. Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
2020-01-27power: regulator: add driver for Dialog DA9063 PMICMartin Fuzzey
Add a driver for the regulators in the the DA9063 PMIC. Robert Beckett: move regulator modes to header so board code can set modes. Correct mode mask used in ldo_set_mode. Add an option CONFIG_SPL_DM_REGULATOR_DA9063. Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group> Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
2020-01-27power: pmic: add driver for Dialog DA9063 PMICMartin Fuzzey
This adds the basic register access operations and child regulator binding (if a regulator driver exists). Robert Beckett: simplify accesses by using bottom bit of address as offset overflow. This avoids the need to track which page we are on. Add an option CONFIG_SPL_DM_PMIC_DA9063. Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group> Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
2020-01-27rtc: s35392a: encode command correctlyIan Ray
The 3-bit "command", or register, is encoded within the device address. Configure the device accordingly, and pass command in DM I2C read/write calls correctly. Signed-off-by: Ian Ray <ian.ray@ge.com> Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
2020-01-27cmd: sata: Add block unbind device functionPeng Ma
If we didn't unbind the sata from block device, the same devices would be added after sata remove, This patch is to resolve this issue as below: => sata info SATA#0: (3.0 Gbps) SATA#1: (3.0 Gbps) Device 0: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005PY30 Type: Hard Disk Supports 48-bit addressing Capacity: 286168.1 MB = 279.4 GB (586072368 x 512) Device 1: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005VX30 Type: Hard Disk Supports 48-bit addressing Capacity: 286168.1 MB = 279.4 GB (586072368 x 512) => sata stop => sata info SATA#0: (3.0 Gbps) SATA#1: (3.0 Gbps) Device 0: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005PY300 Type: Hard Disk Supports 48-bit addressing Capacity: 286168.1 MB = 279.4 GB (586072368 x 512) Device 1: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005VX300 Type: Hard Disk Supports 48-bit addressing Capacity: 286168.1 MB = 279.4 GB (586072368 x 512) Device 2: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005PY300 Type: Hard Disk Supports 48-bit addressing Capacity: 286168.1 MB = 279.4 GB (586072368 x 512) Device 3: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005VX300 Type: Hard Disk Supports 48-bit addressing Capacity: 286168.1 MB = 279.4 GB (586072368 x 512) Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-01-27tbs2910: add custom CONFIG_OF_REMOVE_PROPS list to defconfigAnatolij Gustschin
This shrinks the image size: all -3840.0 text -3840.0 Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Soeren Moch <smoch@web.de>
2020-01-27dts: add property removal option CONFIG_OF_REMOVE_PROPSAnatolij Gustschin
This can be used for device tree size reduction similar as CONFIG_OF_SPL_REMOVE_PROPS option. Some boards must pass the built-in DTB unchanged to the kernel, thus we may not cut it down unconditionally. Therefore enable the property removal list option only if CONFIG_OF_DTB_PROPS_REMOVE is selected. Signed-off-by: Anatolij Gustschin <agust@denx.de>
2020-01-27spi: cadence-qspi: Add compatible for TI AM654Vignesh Raghavendra
TI's AM654 SoC has a Cadence OSPI IP. Add a new compatible string for the same. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27spi: cadence-qspi: Add support for Cadence Octal SPI controllerVignesh Raghavendra
Cadence OSPI is similar to QSPI IP except that it supports Octal IO (8 IO lines) flashes. Add support for Cadence OSPI IP with existing driver using new compatible Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27mtd: spi-nor-core: Add octal mode supportVignesh Raghavendra
Add support for Octal flash devices. Octal flash devices use 8 IO lines for data transfer. Currently only 1-1-8 Octal Read mode is supported. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27spi: cadence-qspi: Add direct mode supportVignesh Raghavendra
Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27spi: cadence_qspi: Move to spi-mem frameworkVignesh Raghavendra
Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27mtd: spinand: winbond: Add support for W25N01GVRobert Marko
Linux has supported W25N01GV for a long time, so lets import it. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27spi: ti_qspi: Add support for CS other than CS0Vignesh Raghavendra
Make sure corresponding setup registers are updated depending on CS. This ensures that driver can support QSPI flashes on ChipSelects other than on CS0 Reported-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27spi: prevent overriding established bus settingsMarcin Wojtas
The SPI stack relies on a proper bus speed/mode configuration by calling dm_spi_claim_bus(). However the hitherto code allowed to accidentally override those settings in the spi_get_bus_and_cs() routine. The initially established speed could be discarded by using the slave platdata, which turned out to be an issue on the platforms whose slave maximum supported frequency is not on par with the maximum frequency of the bus controller. This patch fixes above issue by configuring the bus from spi_get_bus_and_cs() only in case it was not done before. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27cmd: spi: Permit setting bus frequencyMarek Vasut
The 'sspi' command hard-coded 1 MHz bus frequency for all transmissions. Allow changing that at runtime by specifying '@freq' bus frequency in Hz. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27test: dm: spi: Fix sandbox dm_test_spi_find()Bin Meng
Per sandbox_cs_info(), sandbox spi controller only supports chip select 0. Current test case tries to locate devices on chip select 1, and any call to spi_get_bus_and_cs() or spi_cs_info() with cs number 1 should not return 0. This updates the test case to handle it correctly. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27dm: spi: Check cs number before accessing slavesBin Meng
Add chip select number check in spi_find_chip_select(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # SoPine
2020-01-27spi: nxp_fspi: new driver for the FlexSPI controllerMichael Walle
This is a port of the kernel's spi-nxp-fspi driver. It uses the new spi-mem interface and does not expose the more generic spi-xfer interface. The source was taken from the v5.3-rc3 tag. The port was straightforward: - remove the interrupt handling and the completion by busy polling the controller - remove locks - move the setup of the memory windows into claim_bus() - move the setup of the speed into set_speed() - port the device tree bindings from the original fspi_probe() to ofdata_to_platdata() There were only some style change fixes, no change in any logic. For example, there are busy loops where the return code is not handled correctly, eg. only prints a warning with WARN_ON(). This port intentionally left most functions unchanged to ease future bugfixes. This was tested on a custom LS1028A board. Because the LS1028A doesn't have proper clock framework support, changing the clock speed was not tested. This also means that it is not possible to change the SPI speed on LS1028A for now (neither is it possible in the linux driver). Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Kuldeep Singh <kuldeep.singh@nxp.com>
2020-01-27Merge tag 'u-boot-clk-26Jan2020' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-clk - Various clock fixes and enhancements
2020-01-26clock_imx8mq: Make frac_pll_init() staticPedro Jardim
Since frac_pll_init() is only used in this file, change it to 'static'. This fixes the following sparse warning: arch/arm/mach-imx/imx8m/clock_imx8mq.c:662:5: warning: no previous prototype for ‘frac_pll_init’ [-Wmissing-prototypes] Signed-off-by: Pedro Jardim <jardim.c.pedro@gmail.com>
2020-01-26clock_imx8mq: Remove the function sscg_pll_init()Pedro Jardim
Function sscg_pll_init() is not used anywhere, so it can simply be deleted. This was found because of the following sparse warning: arch/arm/mach-imx/imx8m/clock_imx8mq.c:702:5: warning: no previous prototype for ‘sscg_pll_init’ [-Wmissing-prototypes] int sscg_pll_init(u32 pll) ^~~~~~~~~~~~~ Signed-off-by: Pedro Jardim <jardim.c.pedro@gmail.com>
2020-01-26clock_imx8mq: Make do_imx8m_showclocks() staticPedro Jardim
Since do_imx8m_showclocks() is only used inside this file, make it 'static'. This fixes the following sparse warning: arch/arm/mach-imx/imx8m/clock_imx8mq.c:836:5: warning: no previous prototype for ‘do_imx8m_showclocks’ [-Wmissing-prototypes] int do_imx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, ^~~~~~~~~~~~~~~~~~~ Signed-off-by: Pedro Jardim <jardim.c.pedro@gmail.com>
2020-01-26clock_imx8mq: Delete not used init_usb_clk()Pedro Jardim
Function init_usb_clk() is not used anywhere, so it can simply be deleted. This was detected by the following sparse warning: arch/arm/mach-imx/imx8m/clock_imx8mq.c:377:6: warning: no previous prototype for ‘init_usb_clk’ [-Wmissing-prototypes] void init_usb_clk(void) ^~~~~~~~~~~~ Signed-off-by: Pedro Jardim <jardim.c.pedro@gmail.com>
2020-01-26clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate()Giulio Benetti
Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-26clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate()Giulio Benetti
Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-26clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate()Giulio Benetti
Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-26common: fix regression on block cache initAngelo Durgehello
m68k needs block cache list initialized after relocation. Other architectures must not be involved. Fixing regression related to: commit 1526bcce0f7285087621e16e6720636d01839da8 ("common: add blkcache init") Signed-off-by: Angelo Durgehello <angelo.dureghello@timesys.com>
2020-01-26arm: mvebu: fix A38x breakage from commit bb872dd930ccJoel Johnson
This function parameter usage of load_addr was incorrectly caught in the clarifying renames of commit bb872dd930cc, which results in boot failures on Marvell A38x. Signed-off-by: Joel Johnson <mrjoel@lixil.net> Patch-to: Simon Glass <sjg@chromium.org>
2020-01-26Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiTom Rini
- Libre Computer ALL-H3-IT/ALL-H5-CC board (Chen-Yu Tsai) - Allwinner R40 Ethernet, usb phy enablement (Andre Przywara) - Sunxi auto load from 128KB MMC offset (Andre Przywara) - Orange Pi Win Ethernet phy enablement (Jernej Skrabec)
2020-01-26configs: Orange Pi Win: enable ethernet phyJernej Skrabec
Orange Pi Win has gigabit ethernet port, but default U-Boot configuration for that board enabled ethernet driver but didn't enable realtek phy. Fix that. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-26sunxi: Automate loading from 128KB MMC offsetAndre Przywara
Since commit 067e0b9684d4 ("sunxi: Allow booting from 128KB SD/eMMC offset") we support having the SPL loaded from either the traditional 8KB SD card/eMMC offset, or from the alternative location at 128KB. However the sector to find the U-Boot image was still hard-coded at compile time, and had to be adjusted for one of the two choices. Since we can actually override the function to return the sector offset, we can just check the boot source byte there to select the proper offset based on from where the SPL was loaded. This allows the very same binary image to be loaded from either 128KB or 8KB, with the U-Boot proper image always being located just behind the SPL. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-26sunxi: SPL: Factor out sunxi_get_boot_source()Andre Przywara
The Boot ROM write some boot source ID (SD card, eMMC, SPI, ...) into a certain location in SRAM, so the SPL can easily determine where to load U-Boot proper from. Factor out reading this value, as it will come in handy again shortly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-26clk: Fix error checking of dev_read_addr_ptrSean Anderson
dev_read_addr_ptr returns NULL on error, not FDT_ADDR_T_NONE. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-01-26clk: Include missing headers for linux/clk-provider.hSean Anderson
This header was missing a couple of include dependencies when included on its own. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-01-26clk: uclass: clk_get_by_name() must not be available if CONFIG_OF_PLATDATA ↵Giulio Benetti
is enabled clk_get_by_name() requires clk_get_by_id() that is not available if CONFIG_OF_PLATDATA is defined, so move clk_get_by_name() into #else condition of #if CONFIG_IS_ENABLED(OF_PLATDATA). Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-26clk: show more error info when uclass_get_device_by_namePeng Fan
It will ease debug when uclass_get_device_by_name failed with more error info printed out. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-26clk: mediatek: use unsigned type for returning the clk rateFabien Parent
mtk_clk_find_parent_rate is calling clk_get_rate to know the rate of a parent clock. clk_get_rate returns a ulong, while mtk_clk_find_parent_rate returns an int. This implicit cast creates an issue for clock rates big enough to need the full 32 bits to store its data. When that happen the clk rate will become incorrect because of the implicit cast between ulong -> int -> ulong. This commit change the return type of mtk_clk_find_parent_rate to ulong. Signed-off-by: Fabien Parent <fparent@baylibre.com>
2020-01-25Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini
Updates and fixes for ls1028a, lx2160a, ls1012a, ls1021a, ls2080a, ls1088a platforms: - lx2-rev2 pcie support, enetc related updates, layerscape-pcie fixes