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When introducing the SAMA5D27 SoCs, the SAMA5D2 series got an additional
chip id. The check if the cpu is sama5d2 was changed from a preprocessor
definition (inlining a call to 'get_chip_id()') to a C function,
probably to not call get_chip_id twice?
That however broke a check in the macb ethernet driver. That driver is
more generic and also used for other platforms. I suppose this solution
was implemented to use it in 'gem_is_gigabit_capable()', without having
to stricly depend on the at91 platform:
#ifndef cpu_is_sama5d2
#define cpu_is_sama5d2() 0
#endif
That only works as long as cpu_is_sama5d2 is a preprocessor definition.
(The same is still true for sama5d4 by the way.) So this is a straight
forward fix for the workaround.
The not working check on the SAMA5D2 CPU lead to an issue on a custom
board with a LAN8720A ethernet phy connected to the SoC:
=> dhcp
ethernet@f8008000: PHY present at 1
ethernet@f8008000: Starting autonegotiation...
ethernet@f8008000: Autonegotiation complete
ethernet@f8008000: link up, 1000Mbps full-duplex (lpa: 0xffff)
BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
BOOTP broadcast 4
BOOTP broadcast 5
BOOTP broadcast 6
BOOTP broadcast 7
BOOTP broadcast 8
BOOTP broadcast 9
BOOTP broadcast 10
BOOTP broadcast 11
BOOTP broadcast 12
BOOTP broadcast 13
BOOTP broadcast 14
BOOTP broadcast 15
BOOTP broadcast 16
BOOTP broadcast 17
Retry time exceeded; starting again
Notice the wrong reported link speed, although both SoC and phy only
support 100 MBit/s!
The real issue on reliably detecting the features of that cadence
ethernet mac IP block, is probably more complicated, though.
Fixes: 245cbc583d ("ARM: at91: Get the Chip ID of SAMA5D2 SiP")
Signed-off-by: Alexander Dahl <ada@thorsis.com>
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Signed-off-by: Tom Rini <trini@konsulko.com>
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Enabling DM_MMC is forcing CONFIG_BLK=y so if any board which uses
SCSI must need to enable DM_SCSI otherwise SCSI reads on that particular
target making invalid reading to the disk drive.
Allwinner platform do support SCSI on A10, A20 and R40 SoC's out of
these only A10 have DM_SCSI enabled. So enabling DM_MMC on A20, R40
would eventually end-up with scsi disk read failures like [1]
So, enable DM_MMC in all places of respective SoC's instead of enabling
them globally to Allwinner platform.
Now, DM_MMC is enabled in Allwinner SoC's except A20 and R40.
[1] https://lists.denx.de/pipermail/u-boot/2019-April/364057.html
Reported-by: Pablo Sebastián Greco <pgreco@centosproject.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
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- i.MX8QXP-MEK ethernet fix
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PHY cannot be detected unless we wait about 150 ms.
Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@netmodule.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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As per Linux kernel DT binding doc:
- phy-reset-post-delay : Post reset delay in milliseconds. If present then
a delay of phy-reset-post-delay milliseconds will be observed after the
phy-reset-gpios has been toggled. Can be omitted thus no delay is
observed. Delay is in range of 1ms to 1000ms. Other delays are invalid.
Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@netmodule.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
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This patch moves all instances of static "watchdog_dev" declarations to
the "data" section. This may be needed, as the BSS may not be cleared
in the early U-Boot phase, where watchdog_reset() is already beeing
called. This may result in incorrect pointer access, as the check to
"!watchdog_dev" in watchdog_reset() may not be true and the function
may continue to run.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: "Marek Behún" <marek.behun@nic.cz>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Tested-by: Michal Simek <michal.simek@xilinx.com> (on zcu100)
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
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Negative phy-addresses can occour if the caller function was not able to
determine a valid phy address (from device-tree for example). In this
case we catch this here and search for ANY phy device on the given mdio-
bus.
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Lukasz Majewski <lukma@denx.de>
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Fixes for 2019.04
- fix bashism for MX8
- fix ethernet for MX53
- fix docs for i.MX8
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- Documentation fix
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- Important Khadas VIM2 fix
- Build fix for macOS Mojave
- Build fix for gcc-4.7 for host tools.
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Parts of the code are using C99 constructs (such as variables declared
inside loops), but also GNU extensions (such as typeof), so using
-std=gnu99 is necessary to build with older versions of gcc that don't
default to building with gnu99.
It fixes the following build failure:
./tools/../lib/crc16.c: In function "crc16_ccitt":
./tools/../lib/crc16.c:70:2: error: "for" loop initial declarations are only allowed in C99 mode
for (int i = 0; i < len; i++)
^
./tools/../lib/crc16.c:70:2: note: use option -std=c99 or -std=gnu99 to compile your code
when building the host tools with gcc 4.7.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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The Khadas VIM2 defconfig was missing the USB PHY config and
two other misc configs to setup dram banks and call misc_init_r.
Align it on the other Amlogic SoC based boards defconfig.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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The MESON_GXL_USB_PHY is also used on the Amlogic Meson GXM SoCs.
Fixes: 2960e27e38 ("phy: Add Amlogic Meson USB2 & USB3 Generic PHY drivers")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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Fix missing at91 boards and split the at91 in two categories:
at91 arm v7
at91 arm926esj
which are the two main cores for the at91 architecture.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
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After the commit: "eth: dm: fec: Add gpio phy reset binding"
SHA1: efd0b791069af93e9d439a70d1fe2ae8994dbbfa
The FEC ETH driver switched to PHY GPIO reset performed with data defined
in DTS.
For the HSC|DDC boards the GPIO reset signal is active low and hence the
wrong DTS description must be changed (otherwise the reset for ETH is not
properly setup).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
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Signed-off-by: Lukasz Majewski <lukma@denx.de>
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After running tools/moveconfig.py it turned out that for various boards
there are an empty #ifdef statements.
Remove them to clean u-boot source code.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
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The ohci driver calls board_usb_init(), not usb_board_init().
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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Let the underline marker "=" fill the whole sentence for better
readability.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
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The DDR firmware binaries should be copied to '$(srctree)', so fix
a typo.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
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After building ATF it is needed to copy the generated bl31.bin file to
the U-Boot source tree.
Make this step explicit in the instructions.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
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Minor fixes for the Alt board and PHY use on Gen2.
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- clk: sunxi: a10: Add CLK_AHB_GMAC
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CLK_AHB_GMAC was suppose to be part of previous commit
"clk: sunxi: Implement A10 EMAC clocks" add it so-that
we can get rid of sunxi_set_gate warning on boot message.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
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Use a single '=' to test string equality for compatibility with non-bash
shells. Otherwise, if /bin/sh is dash, build fails:
./tools/imx8m_image.sh: 15: [: signed_hdmi_imx8m.bin: unexpected operator
./tools/imx8m_image.sh: 15: [: signed_hdmi_imx8m.bin: unexpected operator
./tools/imx8m_image.sh: 15: [: spl/u-boot-spl-ddr.bin: unexpected operator
./tools/imx8m_image.sh: 15: [: spl/u-boot-spl-ddr.bin: unexpected operator
WARNING './spl/u-boot-spl-ddr.bin' not found, resulting binary is not-functional
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Tested-by: Chris Spencer <christopher.spencer@sea.co.uk>
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Fixes for 2019.01
- pico-imx6ul: fix after conversion
- engicam boards
- pico-imx7d _ README due to hang with imx-usb-loader
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Since commit 9e3c0174da842 ("pico-imx7d: Add LCD support") we started to
notice some hangs in U-Boot.
There is not an issue on such commit per se, but due to the LCD support
the current drawn is increased and this may cause issues when powering
pico-imx7d-pi from USB.
Some computers may be a bit strict with USB current draw and will
shut down their ports if the draw is too high.
The solution for that is to use an externally powered USB hub between the
board and the host computer.
Add such recommendation to the README file.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
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SRAM address used for bootcount on exiting code is erasing
previous count value when system reset from Linux. So use
the dedicated imx6 scratch register, GPR2 to preserve the
contents even if the system reset from Linux.
Fixes: 4eb9aa39350e ("configs: imx6qdl_icore_mmc: Enable watchdog and bootcounter")
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Shyam Saini <shyam.saini@amarulasolutions.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
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SPL on Engicam i.Core M6 boards enabled DM, so it would require some
malloc() pool before relocation in order to load U-Boot proper properly.
So, enable SPL malloc() pool of 0x2000 size similarly like what we have
used for icore mmc defconfigs.
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Shyam Saini <shyam.saini@amarulasolutions.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
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With UUID support, the root can now point to UUID. This makes
swiching between mmc 0 and mmc 1 easier by simplying changing
mmcdev between 0 and 1. From there, the scripts handle the rest.
Signed-off-by: Adam Ford <aford173@gmail.com>
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After the DM_MMC conversion the following eMMC boot error is observed:
U-Boot SPL 2019.04-rc4 (Mar 20 2019 - 18:53:28 +0000)
Trying to boot from MMC1
MMC Device 0 not found
spl: could not find mmc device 0. error: -19
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
This happens because the SPL code does not initialize the SDHC pins
and clock.
Fix it by moving the original eMMC initialization from U-Boot proper
to SPL.
Reported-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Fabio Berton <fabio.berton@ossystems.com.br>
Reviewed-by: Otavio Salvador <otavio@ossystems.com.br>
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Signed-off-by: Stefano Babic <sbabic@denx.de>
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sunxi HDMI clock fix
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Last-minute fixes for Rockchip for 2019.04:
- reverts the deprecation of the 'download-key' detection
(with a full solution pending for the next release)
- applies a temporary fix for the 32bit pinctrl registers on the RK3288
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Signed-off-by: Lukasz Majewski <lukma@denx.de>
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The I2C bus number to access the PMIC is I2C 7, fix this.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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Activate I2C7 on Alt to allow access to the PMIC.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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Commit d245059ff797 ("ARM: rmobile: rcar-gen3: Activate bootm_size")
only fixed the superfluous CONFIG_SYS_BOOTMAPSZ for R-Car Gen3, even
though it listed all affected boards. Apply the same fix to Gen2.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Fixes: d245059ff797 ("ARM: rmobile: rcar-gen3: Activate bootm_size")
Cc: Eugeniu Rosca <erosca@de.adit-jv.com>
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The PHY LED mode register mask should be 0xc000 , not 0xc0000.
Correct the mask to operate on the right bits.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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Synchronize the R8A7794 Alt defconfig, enable DM SPI, DM SPI FLASH
and I2C driver support.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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The CLK2MHZ macro is unused, remove it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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The R8A7794_ETHERNET_B config option is unused and based on the
description, this is a setting which should be fully done on a
DT level instead. Remove this config option.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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- Bugfixes:
- mmc: correct the HS400 initialization process
- configs: ti: Move FIT image load address to avoid overwrite
- lib: time: update module enable MACRO
- Add mbrugger as RPi board maintainer, correct agraf's email address.
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We'd better use correct way to check if module has enabled.
for we have 3 timer MACRO:
- CONFIG_TIMER
- CONFIG_SPL_TIMER
- CONFIG_TPL_TIMER
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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Correct Alex's email address.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Alexander Graf <agraf@csgraf.de>
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I took over maintainership from Alex Graf with commit
3157bbfa18 ("rpi: Make Matthias maintainer")
But I forgot to update the board maintainer file.
This patch adds myself to the game.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Alexander Graf <agraf@csgraf.de>
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The FIT image is loaded to 0x8700_0000 followed by extracting from that
several large images also into the 0x8x00_0000 range. Large images
can end up overwriting the FIT image as it is being extracted from.
Move the FIT load address clear out to 0x9000_0000, this will require
a board to have at least 256MB of DRAM, if less then more careful
planning will be required for that platform.
Signed-off-by: Andrew F. Davis <afd@ti.com>
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After the commit b9a2a0e2e9c0 ("mmc: Add support for downgrading
HS200/HS400 to HS mode"), it add a parameter in mmc_set_card_speed()
which indicates that the HS200/HS400 to HS downgrade is happening.
During the HS400 initialization, first select to HS200, and config
the related clock rate, then downgrade to HS mode. So here also need
to config the downgrade value to be true for two reasons. First,
make sure in the function mmc_set_card_speed(), after switch to HS
mode, first config the clock rate, then read the EXT_CSD, avoid
receiving data of EXT_CSD in HS mode at 200MHz. Second, after issue
the MMC_CMD_SWITCH command, it need to wait a bit then switch bus
properties.
Test on i.MX8QM MEK board, some Micron eMMC will stuck in transfer
mode in this case, and USDHC will never get data transfer complete
status, cause the uboot hang.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
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