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2017-09-18rockchip: pinctrl: rk3368: Convert to livetreePhilipp Tomsich
Update the pinctrl driver for the RK3368 to support a live device tree. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18rockchip: clk: rk3368: Convert to livetreePhilipp Tomsich
Update the clock driver for the RK3368 to support a live device tree. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Version-changes: 2 - use the dev_read_addr_ptr function in clk_rk3368.c
2017-09-18rockchip: timer: Convert to livetreePhilipp Tomsich
Update the Rockchip timer driver to support a live device tree. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18rockchip: timer: implement timer_get_boot_usPhilipp Tomsich
To make the Rockchip DM timer driver useful for the timing of bootstages, we need a few enhancements: - This implements timer_get_boot_us. - This avoids reinitialising the timer, if it has already been set up (e.g. by our TPL and SPL stages). Now, we have a single timebase ticking from TPL through the full U-Boot. - This adds support for reading the timer even before the device-model is ready: we find the timer via /chosen/tick-timer, then read its address and clock-frequency, and finally read the timeval directly). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18rockchip: mmc: convert to livetreePhilipp Tomsich
Update the Rockchip-specific wrapper for the Designware driver to support a live device tree. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Version-changes: 2 - use the dev_read_addr_ptr function in rockchip_dw_mmc.c
2017-09-18net: phy: micrel: Convert to livetreePhilipp Tomsich
Update the Micrel KSZ90x1 driver for a live tree. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-18net: designware: Convert to livetreePhilipp Tomsich
Update the Designware Ethernet MAC driver to support a live device tree. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-18dm: core: add dev_read_addr_ptr()Philipp Tomsich
The dev_read_addr_ptr() mimics the behaviour of the devfdt_get_addr_ptr(), retrieving the first address of the node's reg-property and returning it as a pointer (or NULL on failure). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-18dm: timer: handle being called before dm_root is readyPhilipp Tomsich
When used with bootstage recording, dm_timer_init may be called surprisingly early: i.e. before dm_root is ready. To deal with this case, we explicitly check for this condition and return -EAGAIN to the caller (refer to drivers/timer/rockchip_timer.c for a case where this is needed/used). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18dm: timer: Convert to livetreePhilipp Tomsich
This updates dm_timer_init to support a live tree and deals with some fallout (i.e. the need to restructure the code such, that we don't need multiple discontinuous #if CONFIG_IS_ENABLED blocks). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18bootstage: adjust Makefile to allow including bootstage in SPL, but not in TPLPhilipp Tomsich
For timing our bootstages on the RK3368, which has a minimal TPL (and where we consequently don't want to time the bootstages) and a full-featured SPL (where we can bootstage recording), we need to adjust the Makefile. Use the $(SPL_TPL_) macro in the Makefile for bootstage.o Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18rockchip: board: puma_rk3399: update README flash instructionsKlaus Goger
Puma supports other boot sources then SD-Card. Update README to include the required steps. * how to package a SPI-NOR SPL * how to flash eMMC with rkdeveloptool Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18rockchip: board: lion_rk3368: update README flash instructionsKlaus Goger
Add a section to the README on how to flash the on-board eMMC with the rkdeveloptool. Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18rockchip: rk322x: Disable integrated macphy for saving power consumingDavid Wu
Unfortunately, the integrated macphy default is enabled, which will increase power consuming, if we do not use this PHY. So let's disable it at first, which will save power consuming. If we really use it, then enable it in driver level. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18rockchip: rk322x: enable fastboot to set boot mode tagKever Yang
To support fastboot "fastboot reboot-bootloader" cmd. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18rockchip: enable rk322x sysreset driverKever Yang
The sysreset driver for rk322x is ready but not enabled, add it to Makefile to make sure it's enabled. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18ARM: dts: rockchip: add USB nodes for evb-rv1108William Wu
This patch adds USB OTG/EHCI/OHCI nodes for evb-rv1108 USB ports. Signed-off-by: William Wu <william.wu@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18configs: rockchip: add USB configs for evb-rv1108 boardWilliam Wu
This patch adds USB configs to support the USB OTG port(consist of DWC2 controller) and the USB Host port(consist of EHCI and OHCI controllers) on evb-rv1108 board, and also support fastboot over USB and USB mass storage. Signed-off-by: William Wu <william.wu@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18imx6: drop duplicated bss memset and board_init_r() callAnatolij Gustschin
bss section is cleared in crt0.S. board_init_r() is also entered from crt0 code. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Christian Gmeiner <christian.gmeiner@gmail.com> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Marek Vasut <marex@denx.de> Cc: Lukasz Majewski <lukma@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-09-18pico-imx7d: Add "how to boot with NXP 4.1 Kernel"Vanessa Maegima
The NXP 4.1 kernel needs to boot with secure boot. Add information on how to enable secure boot mode. Signed-off-by: Vanessa Maegima <vanessa.maegima@nxp.com>
2017-09-18imx: imx7d: remove CamelCase from ENET_xMHz macrosEric Nelson
Update these macros to use all upper-case to avoid checkpatch warnings: ENET_25MHz, ENET_50MHz, ENET_125MHz, Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-09-18imx_common: detect USB serial downloader reliablyStefan Agner
The current mechanism using SCR/GPR registers work well when the serial downloader boot mode has been selected explicitly (either via boot mode pins or using bmode command). However, in case the system entered boot ROM due to unbootable primary boot devices (e.g. empty eMMC), the SPL fails to detect that it has been downloaded through serial loader and tries to continue booting from eMMC: Trying to boot from MMC1 mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ### The only known way to reliably detect USB serial downloader is by checking the USB PHY receiver block power state... Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Eric Nelson <eric@nelint.com>
2017-09-18Merge git://git.denx.de/u-boot-uniphierTom Rini
2017-09-18imx: add macro to detect whether USB PHY is activeStefan Agner
This macro allows to detect whether the USB PHY is active. This is helpful to detect if the boot ROM has previously started the USB serial downloader. The idea is taken from the mfgtool support in the NXP U-Boot: http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/commit/?h=imx_v2016.03_4.1.15_2.0.0_ga&id=a352ed3c5184b95c4c9f7468f5fbb5f43de5e412 Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Eric Nelson <eric@nelint.com>
2017-09-18ARM: uniphier: add GPU(Mali) reset deassert and clk enableMasahiro Yamada
The driver for Linux is out of control of Socionext, so set up reset / clock in here. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-09-18ARM: uniphier: remove bit field macros from sc64-regs.hMasahiro Yamada
Starting from PXs3, the bit fields of RSTCTRL, CLKCTRL registers will change every SoC. There is no more point to define bitfields in the common header file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-09-18ARM: uniphier: merge two defconfig files into uniphier_v7_defconfigMasahiro Yamada
The main difference between Pro4 and PXs2/LD6b is the Denali NAND IP version. This is now distinguished by DT. Merge the two defconfig files into uniphier_v7_defconfig. Update the README.uniphier too. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-09-18mtd: nand: denali: allow to override corrupted revision registerMasahiro Yamada
The Denali IP does not update the revision register properly. Allow to override it with SoC data associated with compatible. Linux had already finished big surgery of this driver, but I need to prepare the NAND core before the full sync of the driver. For now, I am fixing the most fatal problem on UniPhier platform. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-09-17Merge git://git.denx.de/u-boot-x86Tom Rini
2017-09-16x86: ivybridge: remove unused variablesHeinrich Schuchardt
legacy_hole_base_k and legacy_hole_size_k are defined but not used. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-16x86: Enable early timer for chromebook_linkSimon Glass
Enable this option for link so that the timer is available earlier. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-16bootstage: Provide a separate record count setting for SPLSimon Glass
With SPL we often have limited memory and do not need very many bootstage records. Add a separate Kconfig option for SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-16bootstage: Drop unused optionsSimon Glass
The CONFIG_BOOTSTAGE_USER_COUNT option is no-longer needed since we can now support any number of user IDs. Also BOOTSTAGE_ID_COUNT is not needed now. Drop these unused options. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-16dm: x86: Allow TSC timer to be used before DM is readySimon Glass
With bootstage we need access to the timer before driver model is set up. To handle this, put the required state in global_data and provide a new function to set up the device, separate from the driver's probe() method. This will be used by the 'early' timer also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-16board_f: Drop the timer after relocationSimon Glass
Once U-Boot relocates itself the existing driver-model timer (if any) is no-longer valid until the device is reinitialised. Any use of the device may cause a crash. To handle this, set the timer to NULL after relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-16x86: Support Intel Cherry Hill boardBin Meng
This adds support to Intel Cherry Hill board, a board based on Intel Braswell SoC. The following devices are validated: - serial port as the serial console - on-board Realtek 8169 ethernet controller - SATA AHCI controller - EMMC/SDHC controller - USB 3.0 xHCI controller - PCIe x1 slot with a graphics card - ICH SPI controller with an 8MB Macronix SPI flash - Integrated graphics device as the video console Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16x86: braswell: Disable PUNIT power configuration for B0 steppingBin Meng
FSP's built-in UPD configuration enables PUNIT power configuration, but on B0 stepping, this causes CPU hangs in fsp_init(). Disable it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16x86: braswell: Add FSP configurationBin Meng
Add FSP related configuration for Braswell. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16x86: braswell: Add microcode for B0/C0/D0 stepping SoCBin Meng
This adds microcode device tree fragment for Braswell B0 (406C2), C0 (406C3) and D0 (406C4) stepping SoC. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16x86: Add Intel Braswell SoC supportBin Meng
This adds initial Intel Braswell SoC support. It uses Intel FSP to initialize the chipset. Similar to its predecessor BayTrail, there are some work to do to enable the legacy UART integrated in the Braswell SoC. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16x86: fsp: Update fsp command to show spec 1.1 headerBin Meng
FSP spec 1.1 adds 3 new APIs and their offsets are in the header. Update the 'fsp hdr' command to show these new entries. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16x86: dm: video: Add a framebuffer driver that utilizes VBTBin Meng
When a VBT is given to an FSP that supports graphics initialization, the FSP will produce a graphics info HOB that contains all necessary information for the linear frame buffer of the integrated graphics device. This adds a DM video driver for it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16x86: dts: Include Intel Video BIOS Table in the ROM imageBin Meng
Now that binman is able to recognize the Video BIOS Table entry, add such one in the u-boot.dtsi. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16tools: binman: Add a new entry type for Intel VBTBin Meng
This adds a new entry type for Intel Video BIOS Table. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16x86: Add Video BIOS Table (VBT) related Kconfig optionsBin Meng
This adds Kconfig options for Video BIOS Table which is normally required if you are using an Intel FSP firmware that is complaint with spec 1.1 or later to initialize the integrated graphics device. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16x86: fsp: Add FSP_GRAPHICS_INFO_HOBBin Meng
This adds a new HOB type for graphics information introduced in FSP spec 1.1. When graphics capability is included in FSP and enabled, FSP produces an FSP_GRAPHICS_INFO_HOB as described in the EFI PI specification which provides information about the graphics mode and framebuffer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16x86: fsp: Update struct common_buf for FSP spec 1.1Bin Meng
FSP spec 1.1 adds one more member to the struct common_buf to determine the memory size that can be reserved by FSP below "top of low usable memory" for bootloader usage. This new member uses the reserved space so that it is still compatible with previous FSP spec 1.0. A new HOB (FSP_HOB_RESOURCE_OWNER_BOOTLOADER_TOLUM_GUID) is also published when common_buf.tolum_size is valid and non zero. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16x86: tsc: Add Airmont reference clock valuesBin Meng
Per the Intel 64 and IA-32 Architecture Software Developer's Manual, add the reference clock for Intel Atom Processors based on the Airmont Microarchitecture (Braswell). This keeps in sync with Linux kernel commit: 6fcb41c: x86/tsc_msr: Add Airmont reference clock values Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-15Merge git://git.denx.de/u-boot-fdtTom Rini
2017-09-15test/py: gpt: make use of infra-structureStephen Warren
Make various changes to the GPT test: 1) Reference the disk image using an absolute path in all cases. This allows test/py to operate correctly if it's run from a directory other than the root of the U-Boot source tree. 2) Store the disk image in the teswt/py persistent data directory. This removes the need to re-generate it every time the tests are run. 3) Execute sgdisk using u_boot_utils.run_and_log() so that its output is captured in the test log. This allows debugging any problems running it. 4) Make the disk image a test fixture. This removes the requirement to always run all GPT tests, and run them in order. The current code doesn't create the disk image if e.g. just test_gpt_uuid() is executed via the test.py -k command-line option. 5) Use @pytest.mark.buildconfigspec for all feature dependencies, rather than manually implementing some of them. 6) Make all tests depend on sandbox, since they use the sandbox-specific host command. Fixes: a2f422555fc8 ("add pytests for 'gpt guid' command in sandbox") Fixes: c5772188ede9 ("add pytests for 'gpt rename' and 'gpt swap'") Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Tom Rini <trini@konsulko.com>
generated by cgit (git 2.34.1) at 2024-12-29 01:21:03 +0000