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2018-03-30arm64: a37xx: populate pcie memory regionWilson Ding
This patch added a new region of 32MiB AT 0xe800.0000 to Armada37x0's memory map. This region is supposed to be mapped in MMU in order to enable the access to the PCI I/O or MEM resources. Signed-off-by: Wilson Ding <dingwei@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38724 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Victor Gu <xigu@marvell.com> Signed-off-by: Ken Ma <make@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30arm64: a37xx: remove old pinctrl implementationKen Ma
Since the new pinctrl/gpio driver is used, so this patch removes the old board specific pin control settings. Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30Revert "arm64: a37xx: dts: Add pin control nodes to DT"Ken Ma
The commit "arm64: mvebu: Add pinctrl nodes for Armada 3700" has added new pinctrl nodes. This reverts commit f7cab0f95b05ec6a66fe4796b9ad44406d0cc864. Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30doc: a37xx: Introduce pinctrl device tree bindingKen Ma
Reviewed-on: http://vgitil04.il.marvell.com:8080/43289 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30arm64: a37xx: dts: Correct mpp definitionsKen Ma
This patch corrects below mpp definitions for armada 3720 DB board and ESPRESSOBin board: - "smi" pins group is added and "smi" function is set for eth0; - Now pcie pins are used as gpio to implement PCIe function in hardware, so "pcie" group function is changed to "gpio". Reviewed-on: http://vgitil04.il.marvell.com:8080/43287 Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30arm64: a37xx: pinctrl: Correct mpp definitionsKen Ma
This patch corrects below mpp definitions: - The sdio_sb group is composed of 6 pins and not 5; - The rgmii group contains pins mpp2[17:6] and not mpp2[19:6]; - Pin of group "pmic0" is mpp1[6] but not mpp1[16]; - Pin of group "pmic1" is mpp1[7] but not mpp1[17]; - A new group "smi" is added in A0 with 2 pins - mpp2[19:18], its bitmask is bit4; - Group "pcie1" has 3 pins in A0 - mpp2[5:3], its bit mask is bit5 | bit9 | bit10 but not bit4; - Group "ptp" has 3 pins in A0 as Z1, but its bitmask is changed to bit11 | bit12 | bit13. Reviewed-on: http://vgitil04.il.marvell.com:8080/43288 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30arm64: a37xx: pinctrl: Fix gpio pin offset in registerKen Ma
For armada_37xx_update_reg(), the parameter offset should be pointer so that it can be updated, otherwise offset will keep old value, and then when offset is larger than or equal to 32 the mask calculated by "BIT(offset)" will be 0 in gpio chip hook functions, it's an error, this patch set offset parameter of armada_37xx_update_reg() as pointer. Reviewed-on: http://vgitil04.il.marvell.com:8080/43287 Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30arm64: a37xx: pinctrl: Fix the pin 23 on south bridgeKen Ma
Pin 23 on South bridge does not belong to the rgmii group. It belongs to a separate group which can have 3 functions. Due to this the fix also have to update the way the functions are managed. Until now each groups used NB_FUNCS(which was 2) functions. For the mpp23, 3 functions are available but it is the only group which needs it, so on the loop involving NB_FUNCS an extra test was added to handle only the functions added. The bug was visible when the gpio regulator used the gpio 23, the whole rgmii group was setup to gpio which broke the Ethernet support on the Armada 3720 DB board. Thanks to this patch, the UHS SD cards (which need the vqmmc) _and_ the Ethernet work again. Reviewed-on: http://vgitil04.il.marvell.com:8080/43284 Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30arm64: a37xx: dts: Fix the number of GPIO on south bridgeKen Ma
The number of pins in South Bridge is 30 and not 29. There is a fix for the driver for the pinctrl, but a fix is also need at device tree level for the GPIO. Reviewed-on: http://vgitil04.il.marvell.com:8080/43286 Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30arm64: a37xx: pinctrl: Fix number of pin in south bridgeKen Ma
On the south bridge we have pin from 0 to 29, so it gives 30 pins (and not 29). Reviewed-on: http://vgitil04.il.marvell.com:8080/43285 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30arm64: a37xx: dts: Add additional pinctrl definitionKen Ma
Add mmc pins, pcie pins and sdio pins definition and do these pins' configuration for DB board and espressobin board; Add uart2 pins configuration for DB board. Reviewed-on: http://vgitil04.il.marvell.com:8080/40914 Reviewed-by: Wilson Ding <dingwei@marvell.com> Tested-by: Wilson Ding <dingwei@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30arm64: a37xx: dts: Add pinctrl configuration for ESPRESSOBin boardKen Ma
Reviewed-on: http://vgitil04.il.marvell.com:8080/40913 Reviewed-by: Wilson Ding <dingwei@marvell.com> Tested-by: Wilson Ding <dingwei@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30arm64: a37xx: defconfig: Enable PINCTRL and GPIO support for ESPRESSOBin boardKen Ma
This patch enable the PINCTRL and GPIO support, including the GPIO command on the Armada 3720 espressobin board. Reviewed-on: http://vgitil04.il.marvell.com:8080/40746 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Wilson Ding <dingwei@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30arm64: a37xx: dts: add gpio head file includingKen Ma
Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30arm64: mvebu: a8k: Add distro boot supportMark Kettenis
The various load address values are taken from the a37xx configuration and match the dowstream 'u-boot-2017.03-armada-17.10' release where appropriate. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30kwbimage: Fix out of bounds accessAlexander Graf
The kwbimage format is reading beyond its header structure if it misdetects a Xilinx Zynq image and tries to read it. Fix it by sanity checking that the header we want to read fits inside our file size. Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30configs: clearfog: enable random random MAC addressBaruch Siach
This makes the network devices usable when booting a blank board over UART, with no pre-configured MAC address stored in the environment area. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30dm: pcie: designware: add correct ATU handlingIgal Liberman
Currently, ATU (address translation unit) implementation doesn't support translate addresses > 32 bits. This patch allows to configure ATU correctly for different memory accesses (memory, configuration and IO). The same approach is used in Linux Kernel. Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-25Merge git://git.denx.de/u-boot-ubiTom Rini
2018-03-25Merge git://git.denx.de/u-boot-spiTom Rini
2018-03-25Merge git://git.denx.de/u-boot-i2cTom Rini
2018-03-25Merge tag 'xilinx-for-v2018.05' of git://git.denx.de/u-boot-microblazeTom Rini
Xilinx changes for v2018.05 - Fix mkimage recognition - Update all my fragments ZynqMP: - Use clk driver - Support loading elfs in el1 - Various DTS and defconfig changes - Enable newer pmufw versions - Support more clocks - Remove ep108 - Secure image support - Fix memtest setup Zynq: - Enabling watchdog driver - Support more clocks - defconfig changes fpga: - Simplify error path net: - GMII case update
2018-03-24Convert CONFIG_UBI_SILENCE_MSG to KconfigPetr Vorel
Signed-off-by: Petr Vorel <petr.vorel@gmail.com>
2018-03-24Convert CONFIG_UBIFS_SILENCE_MSG to KconfigPetr Vorel
Introduce another difference from upstream (kernel) source in fs/ubifs/super.c: adding preprocessor condition as y variable in mount_ubifs() depends on CONFIG_UBIFS_SILENCE_MSG: fs/ubifs/super.c:1337:15: error: variable ?y? set but not used [-Werror=unused-but-set-variable] long long x, y; Not setting CONFIG_UBIFS_SILENCE_MSG in am335x_igep003x_defconfig and igep0032_defconfig. Although it was defined in their config headers, it depends on CMD_UBIFS which is not set for them. Signed-off-by: Petr Vorel <petr.vorel@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Heiko Schocher <hs@denx.de>
2018-03-24ubifs: Reintroduce using CONFIG_UBIFS_SILENCE_MSGPetr Vorel
Use of CONFIG_UBIFS_SILENCE_MSG was added in 147162dac6 ("ubi: ubifs: Turn off verbose prints") Then it was removed in ff94bc40af ("mtd, ubi, ubifs: resync with Linux-3.14") Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Heiko Schocher <hs@denx.de> Signed-off-by: Petr Vorel <petr.vorel@gmail.com>
2018-03-23omap3: spi: Correct ti, pindir-d0-out-d1-in parsingSjoerd Simons
The ti,pindir-d0-out-d1-in property is not expected to have a value according to the device-tree binding, so treat it as a boolean not a uint property. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-03-23Merge git://git.denx.de/u-boot-arcTom Rini
Alexey: 1. Significantly rework cache-related functionality. In particular that fixes coherency problems in some corner-cases, allows us to enable and disable caches in run-time and still have properly running system, finally support execution from real flash (before we used to run from DDR from the very beginning). 2. Remove string routines implemented in assembly. That allows us to build and run U-Boot on wide range of ARC cores with different configurations. I.e. whatever tuning is used on GCC's command-line we'll get code for desired flavor of ARC. Otherwise for each and every corner-case we would need to add ifdefs in assembly code to accommodate missing instructions etc. 3. Get use of GCC's garbage collector which helps to slim-down resulting image quite a bit. 4. Also now we may disable U-Boot self-relocation for ARC if needed either by platform or for debugging purposes.
2018-03-23ARC: bootm: Refactor GO and PREP subcommands implementationEugeniy Paltsev
Refactor GO and PREP subcommands implementation for a simpler override in the boards platform code. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-03-23MAINTAINERS: Fix Zynq/ZynqMP and Microblaze fragmentsMichal Simek
Fix my fragments to list all files in the repo. Also fix path to for Xilinx Zynq SoC (mach-zynq) It should be the part of "ARM: zynq: move SoC sources to mach-zynq" (sha1: 0107f2403669f764ab726d0d404e35bb9447bbcc) And cover dts files in board MAINTAINERS files. Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23tools: xilinx: Fix zynq/zynqmp image recognitionMichal Simek
There is an issue to recognize zynq or zynqmp image because header checking is just the same. That's why zynqmp images are recognized as zynq one. Check unused fields which are initialized to zero in zynq format (__reserved1 0x38 and __reserved2 0x44) which are initialized for zynqmp. This should ensure that images are properly recognized by: ./tools/mkimage -l spl/boot.bin Also show image type as ZynqMP instead of Zynq which is confusing. Reported-by: Alexander Graf <agraf@suse.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Alexander Graf <agraf@suse.de>
2018-03-23arm64: zynqmp: Add support for verifying secure imagesSiva Durga Prasad Paladugu
This patch adds new command "zynqmp" to handle zynqmp specific commands like "zynqmp secure". This secure command is used for verifying zynqmp specific secure images. The secure image can either be authenticated or encrypted or both encrypted and authenticated. The secure image is prepared using bootgen and will be in xilinx specific BOOT.BIN format. The optional key can be used for decryption of encrypted image if user key was specified while creation BOOT.BIN. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23arm64: zynqmp: Remove ep108 boardMichal Simek
ZynqMP Emulation board is no longer tested and there is no reason to keep maintaining it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23arm64: zynqmp: Correct EG/EV part detection logicSiva Durga Prasad Paladugu
The vcu disable bit in efuse ipdisable register is valid only if PL powered up so, consider PL powerup status for determing EG/EV part. If PL is not powered up, ignore EG/EV part of string. The PL powerup status will be filled by pmufw based on PL PROGB status in the 9th bit of version field. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23arm64: zynqmp: Print the value of pl clocks and wdt clock using clk dumpVipul Kumar
This patch print pl clocks (pl0...pl3) and watchdog clock using clk dump. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23arm64: zynqmp: nand: Fixed NAND erase issue for size 1GiB or moreVipul Kumar
NAND erase was not happening for size 1GiB or more. Erase command was executing successfully but in actual, it was not erasing. This patch fixed erase issue for 1 GiB or more size nand. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23arm: zynq: Remove OF_EMBED configuration for zc770 xm011 x16Michal Simek
Use appended dtb which is default option for zynq boards. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23arm: zynq: Setup the same bootcommand as for zc770 xm011 x8Michal Simek
The same command should be used for x16 configuration. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23arm64: zynqmp: Changed scratch address used by the alternate memory testVipul Kumar
This patch changed CONFIG_SYS_MEMTEST_SCRATCH address to the accessible DDR address used by alternate memory test. Before this, 0xfffc0000 address was used, which is the OCM address and not enabled in MMU table. So, whenever trying to access 0xfffc0000 address, got Synchronous Abort exception. After changing CONFIG_SYS_MEMTEST_SCRATCH address, alternate memory test is working fine. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23arm: zynq: Enable cadence driver on zc706Michal Simek
Enable watchdog with reset-on-timeout feature. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23arm: zynq: Wire watchdog internalsMichal Simek
Watchdog is only enabled in full u-boot. Adoption for SPL should be also done because that's the right place where watchdog should be enabled. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23watchdog: Add Cadence watchdog driverShreenidhi Shedi
This IP can be found on Zynq and ZynqMP devices. The driver was tested with reset-on-timeout; feature. Also adding WATCHDOG symbol to Kconfig because it is required. Signed-off-by: Shreenidhi Shedi <imshedi@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23clk: zynq: Show watchdog clock rate properlyMichal Simek
watchdog clock is also connected to cpu 1X clocksource. Zynq> clk dump ... Before: swdt 4294967290 After: swdt 111111110 Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23arm64: zynqmp: Enable newer pmufw versionsMichal Simek
As of now newer pmufw is keeping old interfaces. That's why permit u-boot to run on newer version. Recommended version will be setup later. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23net: zynq_gem: Dont run any phy detection logic for GMII caseSiva Durga Prasad Paladugu
This patch bypasses phy detection logic for GMII interface and just depend on phy address received from DT. This patch is required as phy detection logic is different for some phys like xilinx phy which can be connected over SGMII and GMII interface. This fixes the issue of ethernet failures when xilinx phy is connected over GMII interface. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-03-23arm64: zynqmp: Add support to load an app at EL1Nitin Jain
This patch is adding support to switch to EL1 while loading an EL1 application with u-boot running at EL above EL1 in aarch64 mode. Signed-off-by: Nitin Jain <nitinj@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23arm: zynq: Enable debug uart on ZedboardSiva Durga Prasad Paladugu
It helps with debugging. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23arm64: zynqmp: Enable ethernet driver for zc1751-dc5Michal Simek
Enable missing driver on this board. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23fpga: Simplify error path in fpga_addMichal Simek
Check !desc earlier to simplify code. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Reviewed-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
2018-03-23xilinx: Sync defconfigs with latest Kconfig updatesMichal Simek
Make defconfigs up2date with current location. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23arm64: zynqmp: Convert board to use zynqmp-clk driverMichal Simek
Use zynqmp clock driver instead of fixed clocks. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
generated by cgit (git 2.34.1) at 2024-12-28 04:39:09 +0000