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2019-12-09net: mdio-uclass: rename arguments of dm_mdio_phy_connect for clarityAlex Marginean
Renamed dm_mdio_phy_connect arguments dev to mdiodev and addr to phyaddr for a bit more clarity and consistency with the following patches. Also use NULL instead of 0 on error return path. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: tftp: Fix too small block sizeAndre Przywara
Commit b618b3707633 ("net: Convert CONFIG_TFTP_BLOCKSIZE to Kconfig") accidentally set the default *option* TFTP block size to 512 bytes, even though the comment in the code says that this is a terrible choice. Most boards didn't define the symbol before, so they got the default block size of 1468 bytes before, but now use 512 bytes, which is also the fallback. This leads to both abysmal performance and a lot of hashes printed on the screen (one character for every 5K), which is both annoying and slow over serial links. Set the default block size in Kconfig back to the value it had before. This improves TFTP performance from 2.8 MB/s to 6.9 MB/s on a Pine64. Fixes: b618b3707633 ("net: Convert CONFIG_TFTP_BLOCKSIZE to Kconfig") Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09drivers: net: fsl_enetc: use XFI, USXGMII interface type macrosAlex Marginean
Apply 10G PCS init for USXGMII, XFI interface types. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09doc: bindings: Aquantia PHY node bindingAlex Marginean
A couple of optional properties have been introduced for Aquantia PHY allowing the driver to set up wiring related configuration points that are otherwise driven by firmware. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09doc: bindings: add bindings document for PHY nodesAlex Marginean
It defines that PHY nodes must be children on MDIO bus nodes and defines the only required property in U-Boot, reg. This property along with the example provided are copied over from Linux. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09drivers: net: aquantia: check system interface too when checking for link upAlex Marginean
In some cases the link on the system interface of the aquantia PHY comes up after the link on line interface. The link state loop only checks the line side, which may result in first packet sent being lost. Use aquantia_link_is_up instead, which checks both system and line side on gen 2/3 PHYs to avoid losing the 1st packet. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09drivers: net: aquantia: set SMBus addr based on DT propertyAlex Marginean
Aquantia PHYs have a SMBus interface mostly used for debug. The addresses on this interface are normally set up by PHY firmware, but depending on the board they may end up not being unique. Add an optional DT property used to change SMBus address if needed. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09drivers: net: aquantia: set MDI reversal based on DT propertyAlex Marginean
MDI pins up to the RJ45 connector may be reversed on the board and the default PHY configuration applied by firmware may or may not match that. Add an optional DT property to configure MDI reversal for this case. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09drivers: net: aquantia: set up SI protocol based on interface typeAlex Marginean
If PHY is not ready for data by the time _config is called, reconfigure the PHY system interface to use the proper protocol based on phydev->interface, just in case the defaults set by PHY firmware don't match current configuration. Signed-off-by: Florin Laurentiu Chiculita <florinlaurentiu.chiculita@nxp.com> Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09drivers: net: aquantia: add PHY generation informationAlex Marginean
Uses the data field in phy_driver structure to identify the PHY generation. This is useful for custom configuration as non-generic PHY registers are not 100% compatible between generations. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09drivers: net: aquantia: use XFI, USXGMII interface typesAlex Marginean
The PHY supports XFI and USXGMII, the notable difference being that USX AN is enabled for USXGMII. Legacy code uses XGMII for any 10G proto and detects whether USX AN should be enabled or not using a PHY status register. Keep that functionality too, so we don't break existing drivers. Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09include: phy: add data field for private driver dataAlex Marginean
This is useful to carry custom information between the driver structure associated with a specific HW and the driver code. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09include: phy: define XFI and USXGMII interface typesAlex Marginean
Drivers currently use XGMII for XFI and USXGMII and, where needed, use other information to identify the actual protocol on the board. With these two defined drivers can now rely on DT phy-mode property. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: phy: fix switch vendor nameAnatolij Gustschin
Fix vendor name in MV88E61xx option description. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: phy: mv88e61xx: register phy_driver struct for 88E6071Anatolij Gustschin
Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071Anatolij Gustschin
On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: phy: mv88e61xx: add CPU port parameter init for 88E6071Anatolij Gustschin
On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: phy: mv88e61xx: rework to enable detection of 88E6071 devicesAnatolij Gustschin
Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: phy: micrel: make sure the factory test bit is clearedNicolas Ferre
The KSZ8081 PHY has a factory test mode which is set at the de-assertion of the reset line based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a pull-down is missing, or if the pin has a pull-up, the factory test mode should be cleared by manually writing a 0 (according to the datasheet). Create another ksz8081_config function to handle this case. Suggested-by: Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: eth-uclass: ignore unavailable devicesMichael Walle
device_probe() may fail in which case the seq_id will be -1. Don't display these devices during startup. While this is only a cosmetic change, the return value of eth_initialize() will also change to the actual number of available devices. The return value is only used in spl_net to decide whether there are any devices to boot from. So returning only available devices is also more correct in that case. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: phy: aquantia: wait for phy init sequence to finishFlorin Chiculita
Aquantia quad-phys may take longer to initialize. This commit adds a polling mechanism for a global alarm bit that tells if phy init sequence is completed. Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: macb: let miiphy_read/_write pass arbitrary addressesJosef Holzmayr
This allows passing arbitrary addresses through macb_miiphy_read and macb_miiphy_write, therefore enabling the mii command to access all mdio bus devices instead of only the defined phy. Signed-off-by: Josef Holzmayr <holzmayr@rsi-elektrotechnik.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: macb: explicitly pass phy_adr to mdio read and writeJosef Holzmayr
To support accessing arbitrary addresses the mii/mdio bus it is necessary that the macb_mdio_read and macb_mdio_write functions do not implicitly use the address of the connected phy. The function signature is extended according to the Linux kernel equivalent. Signed-off-by: Josef Holzmayr <holzmayr@rsi-elektrotechnik.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: phy: Increase link up delay in genphy_update_link()Stefan Roese
I've noticed that in most cases when genphy_update_link() is called, the ethernet driver (mt7628-eth in this case) fails with the first ethernet packets. Resulting in a timeout of the first tftp command. Increasing the delay in the link check look from 1 to 50 ms and moving it below the BMSR register read fixes this issue, resulting in a stable ethernet traffic, even after initial link autonogotiation. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Weijie Gao <weijie.gao@mediatek.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09cmd: mdio/mii: add Kconfig help and allow break dependencyRamon Fried
* Add Kconfig help describing the purpose of each command. * Add CONFIG_CMD_MDIO so it could be selected individually, as it doesn't depend on the mii command. * Add Kconfig imply to mii to automatically select the mdio command. Signed-off-by: Ramon Fried <rfried.dev@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: rtl8169: Support RTL-8168c/8111cThierry Reding
This version of the RTL-8168 chip can be found on some add-in cards sold by CSL-Computer GmbH & Co. KG. The chip isn't special in any way, but it needs to have the ChipCmd register programmed after the DMA descriptors have been set up, so make sure that happens by adding an entry to the chip information table. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: mvpp2: MVPP2 now needs MVMDIONevo Hed
Changes to mvpp2.c require the MVMDIO module which in turn uses DM_MDIO. Signed-off-by: Nevo Hed <nhed+github@starry.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: mvpp2: use new MVMDIO driverNevo Hed
This commit ports mvpp2 to use the recently introduced Marvell MDIO (MVMDIO) driver. It removes direct interaction with the SMI & XSMI busses. This commit is based in part on earlier work by Ken Ma <make@marvell.com> in Marvell's own downstream repo: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c81dc39. The above refrenced work was based on an MVMDIO implementation that never made it into U-Boot. With this patch the mvpp2 driver switches to use the new MVMDIO driver that is based on a more universal mdio-uclass implementation. Signed-off-by: Nevo Hed <nhed+github@starry.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09arm: dts: armada-cp110-*dtsi: add xmdio nodesNevo Hed
Based on upstream-linux See https://github.com/torvalds/linux/commit/f66b2aff. However made the XSMI register window 0x16 (22) bytes per my reading of the functional spec. Similar commits in Marvels own repo bump it to 0x200 (512) bytes but I did not see the reasoning for that. https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/4d932b4. Also added device-name attributes to prevent ambiguity in the `mdio` command. Signed-off-by: Nevo Hed <nhed+github@starry.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: mvpp2: mark phy as invalid in case of missing appropriate driverGrzegorz Jaszczyk
If the phy doesn't match with any existing u-boot drivers, the phy framework will connect it to the generic one which uid == 0xffffffff. In this case, act as if the phy wouldn't be declared in dts. Otherwise, in case of 3310 (for which the driver doesn't exist) the link is marked as always down. Removing phy entry from dts in case of 3310 is not a good option because it is required for the phy_fw_down procedure. This patch fixes the issue with the link always down on MCBIN board. nhed: added NULL deref test. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: Igal Liberman <igall@marvell.com> Tested-by: Igal Liberman <igall@marvell.com> Signed-off-by: Nevo Hed <nhed+github@starry.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: mvpp2x: fix traffic stuck after PHY start errorStefan Chulski
Issue: - Network stuck if autonegotion fails. Issue root cause: - When autonegotiation fails during port open procedure, the packet processor configuration does not finish and open procedure exits with error. - However, this doesn't prevent u-boot network framework from calling send and receive procedures. - Using transmit and receive functions of misconfigured packet processor will cause traffic to get stuck. Fix: - Continue packet processor configuration even if autonegotiation fails. Only error message is triggered in this case. - Exit transmit and receive functions if there is no PHY link indication. - U-boot network framework now calls open procedure again during next transmit initiation. Signed-off-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Tested-by: Igal Liberman <igall@marvell.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09arm: dts: k3-am654-base-board-u-boot: change cpsw2g interface mode to rgmii-rxidGrygorii Strashko
The AM654 SoC doesn't allow to disabling RGMII TX internal delay in CPSW2G MAC. Hence, change CPSW2G interface mode to "rgmii-rxid" - RGMII with internal RX delay provided by the PHY, the MAC will add an TX delay in this case. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: phy: dp83867: refactor rgmii configurationGrygorii Strashko
Refactor SGMII configuration to group all settings together and reduce number of MDIO transactions. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: phy: dp83867: io impedance is not dependent on RGMII delayGrygorii Strashko
Based on commit 27708eb5481b ("net: phy: dp83867: IO impedance is not dependent on RGMII delay") of mainline linux kernel. The driver would only set the IO impedance value when RGMII internal delays were enabled. There is no reason for this. Move the IO impedance block out of the RGMII delay block. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: phy: dp83867: rework delay rgmii delay handlingGrygorii Strashko
Based on commit c11669a2757e ("net: phy: dp83867: Rework delay rgmii delay handling") of mainline linux kernel. The current code is assuming the reset default of the delay control register was to have delay disabled. This is what the datasheet shows as the register's initial value. However, that's not actually true: the default is controlled by the PHY's pin strapping. This patch: - insures the other direction's delay is disabled If the interface mode is selected as RX or TX delay only - validates the delay values and fail if they are not in range - checks if the board is strapped to have a delay and is configured to use "rgmii" mode and warning is generated that "rgmii-id" should have been used. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: phy: dp83867: Add ability to disable output clockGrygorii Strashko
Based on commit 13c83cf8af0d ("net: phy: dp83867: Add ability to disable output clock") of mainline linux kernel. Generally, the output clock pin is only used for testing and only serves as a source of RF noise after this. It could be used to daisy-chain PHYs, but this is uncommon. Since the PHY can disable the output, make doing so an option. I do this by adding another enumeration to the allowed values of ti,clk-output-sel. The code was not using the value DP83867_CLK_O_SEL_REF_CLK as one might expect: to select the REF_CLK as the output. Rather it meant "keep clock output setting as is", which, depending on PHY strapping, might not be outputting REF_CLK. Change this so DP83867_CLK_O_SEL_REF_CLK means enable REF_CLK output. Omitting the property will leave the setting as is (which was the previous behavior in this case). Out of range values were silently converted into DP83867_CLK_O_SEL_REF_CLK. Change this so they generate an error. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09dt-bindings: phy: dp83867: Add documentation for disabling clock outputGrygorii Strashko
Based on commit 980066e6d964 ("dt-bindings: phy: dp83867: Add documentation for disabling clock output") of mainline linux kernel. The clock output is generally only used for testing and development and not used to daisy-chain PHYs. It's just a source of RF noise afterward. Add a mux value for "off". I've added it as another enumeration to the output property. In the actual PHY, the mux and the output enable are independently controllable. However, it doesn't seem useful to be able to describe the mux setting when the output is disabled. Document that PHY's default setting will be left as is if the property is omitted. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: phy: dp83867: move static initialization to .probe()Grygorii Strashko
Move static, one-time initialization to .probe() callback. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: phy: ti: rename ti.c to dp83867.cGrygorii Strashko
The driver ti.c is actually driver for TI DP83867x PHYs, so rename it accordingly. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: tftp: Fix tftp store address check in store_block()Bin Meng
During testing of qemu-riscv32 with a 2GiB memory configuration, tftp always fails with a error message: Load address: 0x84000000 Loading: # TFTP error: trying to overwrite reserved memory... It turns out the result of 'tftp_load_addr + tftp_load_size' just overflows (0x100000000) and the test logic in store_block() fails. Fix this by adjusting the end address to ULONG_MAX when overflow is detected. Fixes: a156c47e39ad ("tftp: prevent overwriting reserved memory") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: avoid address-of-packed-member errorHeinrich Schuchardt
sandbox_defconfig does not compile using GCC 9.2.1: net/net.c: In function ‘net_process_received_packet’: net/net.c:1288:23: error: taking address of packed member of ‘struct ip_udp_hdr’ may result in an unaligned pointer value [-Werror=address-of-packed-member] 1288 | sumptr = (ushort *)&(ip->udp_src); | ^~~~~~~~~~~~~~ Avoid the error by using a u8 pointer instead of an u16 pointer and in-lining ntohs(). Simplify the checksumming of the last message byte. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net/phy: Fix phy_connect() for phy addr 0Priyanka Jain
Fix 'mask' calculation in phy_connect() for phy addr '0'. 'mask' is getting set to '0xffffffff' for phy addr '0' in phy_connect() whereas expected value is '0'. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reported-by: tetsu-aoki via github Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: nfs: Only link in NFS code outside of SPL buildsTom Rini
While we have networking use cases within SPL we do not support loading files via NFS at this point in time. Disable calling nfs_start() so that the NFS related code can be garbage collected at link time. Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09lib: Always build support for formatting MAC and IP addressJoe Hershberger
Even if not communicating over the network in U-Boot, code may be manipulating and storing IP or MAC addresses to pass to Linux, etc. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: Improve documentation for string_to_ip()Joe Hershberger
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: Always build the string_to_enetaddr() helperJoe Hershberger
Part of the env cleanup moved this out of the environment code and into the net code. However, this helper is sometimes needed even when the net stack isn't included. Move the helper to lib/net_utils.c like it's similarly-purposed string_to_ip(). Also rename the moved function to similar naming. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reported-by: Ondrej Jirman <megous@megous.com>
2019-12-08Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86Tom Rini
- 16-bit start up codes clean up
2019-12-08x86: simplify ljmp to 32-bit codeMasahiro Yamada
You can directly specify the label as the operand for ljmp. This commit saves 4-byte code. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fixed the gas warning] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-08x86: use data32 directive instead of macro for operand-size prefixMasahiro Yamada
This file defines 'a32' and 'o32' macros to avoid magic numbers of operand/address-size prefixing. GAS supports 'data32' and 'addr32' for that purpose. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-06Merge branch '2019-12-06-master-imports'Tom Rini
- Allow for the sysboot command, which is used to parse extlinux.conf files to be used without PXE support. There is no functional change here aside from fixing distro boot in a few cases where we actually lacked the ability to parse the extlinux.conf file - Add the x509/pkcs7 parsers from Linux, a pre-requisite to EFI Secure Boot support.
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