summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2011-04-04powerpc/85xx: load ucode from nand flash before qe_initHaiying Wang
In the case the QE's microcode is stored in nand flash, we need to load it from NAND flash to ddr first then the qe_init can get the ucode correctly. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04fsl_ddr: Adds 16 bit DDR Data width optionPoonam Aggrwal
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Cc: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04powerpc/85xx: Use BR_PHYS_ADDR macro to setup BRs on P1_P2_RDBPoonam Aggrwal
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04powerpc/8xxx: Display DIMM modelYork Sun
Beside displaying RDIMM or UDIMM, this patch adds display of the model numbers embedded in SPD. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04powerpc/85xx: Update fixed DDR3 timing table for P4080DSYork Sun
Most of time U-boot doesn't get an exact clock number. For example, clock 900MHz may be detected as 899.99MHz. 800MHz could be 799.99MHz. Update the table to align the desired clocks in the middle. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04powerpc/8xxx: Fix LAW init to respect pre-initialized entriesKumar Gala
If some pre-boot or earlier stage bootloader (NAND SPL) has setup LAW entries consider them good and mark them used. In the NAND SPL case we skip re-initializing based on the law_table since the SPL phase already did that. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04fsl_pci: Add support for FSL PCIe controllers v2.xPrabhakar Kushwaha
FSL PCIe controller v2.1: - New MSI inbound window - Same Inbound windows address as PCIe controller v1.x Added new pit_t member(pmit) to struct ccsr_pci for MSI inbound window FSL PCIe controller v2.2 and v2.3: - Different addresses for PCIe inbound window 3,2,1 - Exposed PCIe inbound window 0 - New PCIe interrupt status register Added new Interrupt Status register to struct ccsr_pci & updated pit_t array size to reflect the 4 inbound windows. To maintain backward compatiblilty, on V2.2 or greater controllers we start with inbound window 1 and leave inbound 0 with its default value (which maps to CCSRBAR). Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04powerpc/85xx: Refactor Qman/Portal support to be shared between SoCsHaiying Wang
There are some differences between CoreNet (P2040, P3041, P5020, P4080) and and non-CoreNet (P1017, P1023) based SoCs in what features exist and the memory maps. * Rename various immap defines to remove _CORENET_ if they are shared * Added P1023/P1017 specific memory offsets * Only setup LIODNs or LIODN related code on CORENET based SoCs (features doesn't exist on P1023/P1017) Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04powerpc/85xx: Add support for Freescale P1023/P1017 ProcessorsRoy Zang
Add P1023 (dual core) & P1017 (single core) specific information: * SERDES Table * Added P1023/P1017 to cpu_type_list and SVR list (fixed issue with P1013 not being sorted correctly). * Added P1023/P1027 to config_mpc85xx.h * Added new LAW type introduced on P1023/P1017 * Updated a few immap register/defines unique to P1023/P1017 Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04powerpc/85xx: Don't build read_tlbcam_entry for CONFIG_NAND_SPLKumar Gala
Slim down NAND SPL build a bit as we don't need read_tlbcam_entry. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04powerpc: Add cpu_secondary_init_r to allow for initialization post env setupKumar Gala
We can simplify some cpu/SoC level initialization by moving it to be after the environment and non-volatile storage is setup as there might be dependancies on such things in various boot configurations. For example for FSL SoC's with QE if we boot from NAND we need it setup to extra the ucode image to initialize the QE. If we always do this after environment & non-volatile storage is working we can have the code be the same regardless of NOR, NAND, SPI, MMC boot. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04powerpc/85xx: Cleanup some QE related definesKumar Gala
Move some processor specific QE defines into config_mpc85xx.h and use QE_MURAM_SIZE to cleanup some ifdef mess in the QE immap struct. Also fixed up some comment style issues in immap_qe.h Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04powerpc/8xxx: Refactor fsl_ddr_get_spd into common code from boardKumar Gala
Move fsl_ddr_get_spd into common mpc8xxx/ddr/main.c as most boards pretty much do the same thing. The only variations are in how many controllers or DIMMs per controller exist. To make this work we standardize on the names of the SPD_EEPROM_ADDRESS defines based on the use case of the board. We allow boards to override get_spd to either do board specific fixups to the SPD data or deal with any unique behavior of how the SPD eeproms are wired up. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04powerpc/8xxx: Replace fsl_ddr_get_mem_data_rate with get_ddr_freq()Kumar Gala
Every 85xx board implements fsl_ddr_get_mem_data_rate via get_ddr_freq() and every 86xx board uses get_bus_freq(). If implement get_ddr_freq() as a static inline to call get_bus_freq() we can remove fsl_ddr_get_mem_data_rate altogether and just call get_ddr_freq() directly. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04powerpc/85xx: Remove config.mk for nand linker scriptKumar Gala
Move the include of mpc85xx/u-boot-nand.lds to utilize CONFIG_SYS_LDSCRIPT rather than having an explicit config.mk Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04powerpc: Move cpu specific lmb reserve to arch_lmb_reserveKumar Gala
We've been utilizing board_lmb_reserve to reserve the boot page for MP systems. We can just move this into arch_lmb_reserve for 85xx & 86xx systems rather than duplicating in each board port. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04powerpc/85xx: Update P2020DS default env settingsLi Yang
Read MAC address from EEPROM. Add hwconfig settings. Modified the default othbootargs to include the cache-sram-size parameter. This parameter is needed as the L2 as SRAM is ON by default in the P2020RDB kernel and used by the Gianfar driver. Also cleanup some of the boot commands. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Zhao Chenhui <b35336@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04powerpc/85xx: Add eSDHC support on P2020DSJerry Huang
We enable SDHC_CD and SDHC_WP signals (pin muxed with GPIO8 & GPIO9 respectively). We enable EXT2, FAT, and parition support for both MMC & USB configs. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Jin Qing <b24347@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04powerpc/85xx: Add some defines for P2040, P3041, P5010, P5020Kumar Gala
Specify the number of DDR controllers, number of frame managers, number of 1g and 10g ports. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04powerpc/85xx: Extend ethernet device tree stashing parameters for "fsl,etsec2"Pankaj Chauhan
In a manner similar to passing ethernet stashing parameters into device tree for "gianfar", extend the support to the "fsl,etsec2" as well. Signed-off-by: Pankaj Chauhan <pankaj.chauhan@freescale.com> Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04powerpc/85xx: Declare fsl_ddr_set_memctl_regs in <asm/fsl_ddr_sdram.h>Kumar Gala
Remove declerations of fsl_ddr_set_memctl_regs in board files with and place it into a common header. Based on patch from Poonam Aggrwal. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04powerpc/85xx: Remove DATARATE_*_MHZ defines in static ddr initKumar Gala
Rather than having #defines DATARATE_*_MHZ, lets just match what we do on the SPD code and convert the DDR frequency into MHZ and just compare with a constant. Based on patch from Poonam Aggrwal. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04p1022ds: allow for board-specific ngPIXIS functionsTimur Tabi
The ngPIXIS is an FPGA used on the reference boards of most Freescale PowerPC SOCs. Although programming the ngPIXIS is mostly standard on all boards that have it, the P1022DS is unique in that the ngPIXIS needs to be programmed in "indirect" mode whenever the video display (DIU) is active. To support indirect mode, and to make it easier to support other quirks on future reference boards, the low-level ngPIXIS functions are all marked as weak, so that board-specific code can override any of them. We take advantage of this feature on the P1022DS, so that we can properly reset the board when the DIU is active. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04powerpc/85xx: Add support for Integrated Flash Controller (IFC)Dipen Dudhat
The Integrated Flash Controller (IFC) is used to access the external NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip selects are provided in IFC so that maximum of four Flash devices can be hooked, but only one can be accessed at a given time. Features supported by IFC are, - Functional muxing of pins between NAND, NOR and GPCM - Support memory banks of size 64KByte to 4 GBytes - Write protection capability (only for NAND and NOR) - Provision of Software Reset - Flexible Timing programmability for every chip select - NAND Machine - x8/ x16 NAND Flash Interface - SLC and MLC NAND Flash devices support with configurable page sizes of upto 4KB - Internal SRAM of 9KB which is directly mapped and availble at boot time for NAND Boot - Configurable block size - Boot chip select (CS0) available at system reset - NOR Machine - Data bus width of 8/16/32 - Compatible with asynchronous NOR Flash - Directly memory mapped - Supports address data multiplexed (ADM) NOR device - Boot chip select (CS0) available at system reset - GPCM Machine (NORMAL GPCM Mode) - Support for x8/16/32 bit device - Compatible with general purpose addressable device e.g. SRAM, ROM - External clock is supported with programmable division ratio - GPCM Machine (Generic ASIC Mode) - Support for x8/16/32 bit device - Address and Data are shared on I/O bus - Following Address and Data sequences can be supported on I/O bus - 32 bit I/O: AD - 16 bit I/O: AADD - 8 bit I/O : AAAADDDD - Configurable Even/Odd Parity on Address/Data bus supported Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04powerpc/85xx: Add SERDES support for P1010/P1014Prabhakar Kushwaha
Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Updated MPC85xx_PORDEVSR_IO_SEL & MPC85xx_PORDEVSR_IO_SEL_SHIFT Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-01atmel_nand: don't require CONFIG_SYS_NAND_ENABLE_PINmichael
If NCE is hooked up to NCS3, we don't need to (and can't) explicitly set the state of the NCE pin. Instead, the controller asserts it automatically as part of a command/data access. Only "CE don't care"-type NAND chips can be used in this manner. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Reinhard Meyer <u-boot@emk-elektronik.de>
2011-04-01NAND: add support for reading ONFI page tableFlorian Fainelli
This patch adds support for reading an ONFI page parameter from a NAND device supporting it. If this is the case, struct nand_chip onfi_version member contains the supported ONFI version, 0 otherwise. This allows NAND drivers past nand_scan_ident to set the best timings for the NAND chip. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Scott Wood <scottwood@freescale.com>
2011-04-01Fix NAND_SPL and ONENAND_IPL in MakefileHaiying Wang
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2011-04-01NAND: add more watchdog resetsScott Wood
Poke the watchdog in a variety of looping constructs, which could take a long time to complete. Signed-off-by: Scott Wood <scottwood@freescale.com>
2011-03-31Prepare v2011.03Wolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-03-31Fix build issues cause by LDFLAGS_FINAL changesWolfgang Denk
Commit 6dc1ece "Introduce a new linker flag LDFLAGS_FINAL" modified a number of Makefiles in a way that broke out-of-tree builds. The problem was that $(nandobj) was used before it got defined. Fix this. Signed-off-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
2011-03-31Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk
2011-03-31Merge branch 'master' of git://git.denx.de/u-boot-cfi-flashWolfgang Denk
2011-03-31Fix build problems caused by "_end" -> "__bss_end__" renameWolfgang Denk
Commit 44c6e65 "rename _end to __bss_end__ broke building of a large number of systems (at least all PowerPC?): libstubs.o: In function `app_startup': examples/standalone/stubs.c:197: undefined reference to `__bss_end__' The rename should not be done for the files in the examples/standalone/ directory, as these are not using the code from start.S, but do their own BSS clearing, and either use their own linker scripts or the ones provided by the compilers. Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-03-29powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCsPrabhakar Kushwaha
The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require that we initialize the SERDES registers if the lanes are configured for PCIe. Additionally these devices PCIe controller do not support ASPM and we have to explicitly disable it. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-03-28cfi_flash: fix bug with flash banks with different sector numbersMartin Krause
The function find_sector() does not take into account if the flash bank has changed since the last call. This could lead to illegal accesses inside and beyond the flash_info_t info strcture. For example if the current flash bank has less sectors than the last used flash bank. This patch adds two cheks. One that insures, that the current sector does not exceed the allowed maximum (which is always a good idea). And one that checks if the current access is to the same flash bank as the last access. If not, the search loop will start with sector 0. Signed-off-by: Martin Krause <martin.krause@tqs.de> Signed-off-by: Stefan Roese <sr@denx.de>
2011-03-28powerpc/85xx: Enable various errata on P1022/P1013 SoCsJiang Yutang
Enable workaround for errata ELBC A001, ESDHC 111 & SATA A001 on P1022/P1013 SoCs. Also updated P1022DS config to properly enable CONFIG_FSL_SATA_V2. Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-03-27Prepare vWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-03-27Coding Style cleanup: remove trailing empty linesWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-03-27Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk
2011-03-27arm: Tegra2: Change mach-type to MACH_TYPE_SEABOARD due to mach-types.h updateTom Warren
Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-03-27S5P: mmc: Resolved interrupt error during mmc_initChander Kashyap
Blocksize was hardcoded to 512 bytes. But the blocksize varies depeding on various mmc subsystem commands (between 8 and 512). This hardcoding was resulting in interrupt error during data transfer. It is now calculated based upon the request sent by mmc subsystem. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2011-03-27ARMV7: S5P: Fixed register offset in mmc.hChander Kashyap
The MMC registers are accessed through struct s5p_mmc member variables. MMC controller "control4" register offset is set to 0x8C as per data sheet. The size of struct s5p_mmc is also corrected. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2011-03-27S5P: timer: replace bss variable by gdMinkyu Kang
Use the global data instead of bss variable, replace as follow. count_value -> removed timestamp -> tbl lastdec -> lastinc Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Albert ARIBAUD <albert.aribaud@free.fr>
2011-03-27S5P: universal: Enable the pwm driverMinkyu Kang
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2011-03-27S5P: goni: Enable the pwm driverMinkyu Kang
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2011-03-27S5P: smdkc100: Enable the pwm driverMinkyu Kang
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2011-03-27S5P: timer: Use pwm functionsMinkyu Kang
Use pwm functions for timer that is PWM timer 4. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2011-03-27ARM: S5P: pwm driver supportDonghwa Lee
This is common pwm driver of S5P. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2011-03-27SMDK6400: Fixup dram_init for relocation supportseedshope
Signed-off-by: Zhong Hongbo <bocui107@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
generated by cgit (git 2.34.1) at 2024-12-29 20:07:39 +0000