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2019-11-17rockchip: rk3399: rock960: Update config for TPLPeter Robinson
Enable TPL for rock960 like other rk3399 boards. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17configs: Rename roc-rk3399-pc -> roc-pc-rk3399 defconfigJagan Teki
roc-rk3399-pc_defconfig is committed in below commit <8a681f4c5aa15db51ad0209734859c9fe7c29cfd> ("rockchip: rk3399: Add ROC-RK3399-PC support") which doesn't follow the existing defconfigs on rk3399. So, rename as followed with other rk3399 defconfigs. Cc: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17arm: dts: rk3399-roc-pc: Sync latest dts changes from LinuxJagan Teki
Few important regulator power rails fixes are available in linux-next, so sync them same. Here is the last commit details: commit <9f7f9b610e1b7d2dc86c543ab0dfcf781bd42326> ("arm64: dts: rockchip: Fix roc-rk3399-pc regulator input rails") Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: Init driver otg_data for rk3288 usb phyKever Yang
RK3288 needs to init the otg_data in board level to make the phy driver work. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: usb: Migrate to use ofnodeKever Yang
Migrate to use ofnode_* instead of fdt_* so that we may able to use live dt for usb udc driver. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: add px30-evb boardHeiko Stuebner
The px30 evb is an evaluation board for the px30 together with a dsi- connected display. This adds board and config files for it. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: add px30 architecture coreHeiko Stuebner
Add core architecture code to support the px30 soc. This includes a separate tpl board file due to very limited sram size as well as a non-dm sdram driver, as this also has to fit into the tiny sram. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: add px30 devicetreesHeiko Stuebner
Add px30 related devicetrees synced from the Linux kernel. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: misc: read cpuid either from efuse or otpHeiko Stuebner
Newer Rockchip socs use a different ip block to handle one-time- programmable memory, so depending on what got enabled get the cpuid from either source. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17misc: add driver for the Rockchip otp controllerFinley Xiao
Newer Rockchip socs like the px30 use a different ip block to handle one-time-programmable memory, so add a misc driver for it as well. Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: mkimage: add support for px30Kever Yang
Add the table entry for px30 socs. The px30 has 10K of sram available. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17net: gmac_rockchip: add support for px30Heiko Stuebner
Add the glue code to allow the px30 variant of the Rockchip gmac to provide network functionality. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: clk: add px30 clock driverKever Yang
The px30 contains 2 separate clock controllers, pmucru and cru. Add drivers for them. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17pinctrl: rockchip: add px30 pinctrl driverDavid Wu
Add the necessary glue code to allow pinctrl setting on px30 socs. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: add core px30 headersHeiko Stuebner
Add headers needed by the upcoming px30 support, including two new dt-binding headers taken from the Linux kernel. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17spl: separate SPL_FRAMEWORK config for spl and tplHeiko Stuebner
Right now enabling SPL_FRAMEWORK will also enable it for the TPL in all cases, making the TPL bigger. There may be cases where the TPL is really size constrained due to its underlying ram size. Therefore introduce a new TPL_FRAMEWORK option and make the relevant conditionals check for both. The default is set to "y if SPL_FRAMEWORK" to mimic the previous behaviour where the TPL would always get the SPL framework if it was enabled in SPL. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rk3399: Fix dram setting to make dram more stableYouMin Chen
There are some code different with rockchip vendor code which may lead to different bugs, including: 1) Fix setting error about LPDDR3 dram size ODT. 2) Set phy io speed to 0x2. 3) Fix setting error about phy_pad_fdbk_drive. 4) Fix setting error about PI_WDQLVL_VREF_EN Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rk3399: update calculate_strideKever Yang
Update the calculation of the stride to support all the DRAM case. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rk3399: Sync the io setting from Rockchip vendor codeKever Yang
The io setting are updated after some bugfix in different rk3399 boards, sync the code from vendor. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rockchip: update lpddr4 timing for rk3399Kever Yang
Update lpddr timing in lpddr4-400 and lpddr4-800 file from rockchip vendor code; Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rk3399: add support detect capacityYouMin Chen
Add capacity detect for rk3399 so that the driver able to detect the capacity automatically. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rk3399: update the function of sdram_initYouMin Chen
Clean up the sdram_init to keep sync with rockchip source code. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rk3399: fix error about get_ddrc0_con reg addrYouMin Chen
Correct the register to its correct name. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rk3399: Clean up codeYouMin Chen
Clean up rk3399 dram driver source code for more readable. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rk3399: migrate to use common codeYouMin Chen
For there are some structures and functions are common for all rockchip SoCs, migrate to use the common code so that we can clean up reduandent codes. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rk3328: use common sdram driverYouMin Chen
RK3328 has a similar controller and phy with PX30, so we can use the common driver for it and remove the duplicate codes. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: px30: add sdram driverYouMin Chen
Add the sdram driver for PX30 to support ddr3, ddr4, lpddr2 and lpddr3. For TPL_BUILD, the driver implement full dram init and without DM support due to the limit of internal SRAM size. For SPL and U-Boot proper, it's a simple driver with dm for get dram_info like other SoCs. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rockchip: add common msch reg definitionKever Yang
The noc register bit definition may be the same for different SoC while the offset of the register may be different, add the struction definition as common code. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rockchip: add phy driver code for PX30Kever Yang
This sdram_phy_px30.c is based on PX30 SoC, the functions are common for phy, other SoCs with similar hardware could re-use it. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rockchip: add controller code for PX30Kever Yang
This sdram_pctl_px30.c is based on PX30 SoC, the functions are common for controller, other SoCs with similar hardware could re-use it. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rockchip: Default enable DRAM debug infoKever Yang
The debug info for dram is main about the capacity related info which is very important the board init, so set this default enable. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rockchip: move sdram_debug function into sdram_commonKever Yang
The functions for dram info print are part of common code. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rockchip: add common code for sdram driverKever Yang
There are some function like os_reg setting, capacity detect functions, can be used as common code for different Rockchip SoCs, add a sdram_common.c for all these functions. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: sdram: update the sys_reg to sys_reg2Kever Yang
We are using sys_reg2 and sys_reg3 as ddr cap info, sync the variable name to what we real use to avoid confuse people. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: sdram: extend to use sys_reg3 for capacity infoKever Yang
Since we have new DRAM type and to support different DRAM size in different CS, we need more bits, so introduce sys_reg3 to record the info. Note that the info in sys_reg3 is extension to sys_reg2 and the info in sys_reg2 is the same as before. We define the DRAM_INFO with sys_reg3 as VERSION2. All the ENC macro are moved to sdram_common.h since the sdram.c only need to do the info decode. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: sdram: move cap structure and debug function to sdram_common.hKever Yang
The sdram.h suppose to be helper file for sdram.c which including dram size decode and some u-boot related dram init interface, and all structure and function for dram driver move to sdram_common.h Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rockchip: rename sdram_common.c/h to sdram.cKever Yang
rename sdram_common.c in arch/arm/mach-rockchip to sdram.c; so that we can use the file name sdram_common.c in dram driver for better understand the code; clean the related file who has use the header file at the same time. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rockchip: rename sdram.h to sdram_rk3288.hKever Yang
The header file sdram.h is used for rk3288 and similar SoCs, rename it to make it more understandable. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-16ARM: rmobile: Temporarily disable PCI dma-ranges updateMarek Vasut
According to discussion in the Linux PCI list [1], the dma-ranges should be continuous and describe the entire inbound window which the controller can address and not take into account the possible DRAM holes. Temporarily disable this code which updates the dma-ranges until this meaning is sorted out. [1] PCI: rcar: Do not abort on too many inbound dma-ranges Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-11-15ARM: rmobile: Enable CONFIG_ARCH_FIXUP_FDT_MEMORY on Gen3Marek Vasut
Enable CONFIG_ARCH_FIXUP_FDT_MEMORY to let U-Boot patch the Linux DT memory entries. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-11-14Merge tag 'efi-2020-01-rc3' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for UEFI sub-system for efi-2020-01-rc3 The following changes for the UEFI subsystem are provided: * allow building UEFI binaries on the sandbox * enable access to file systems without partition tables * correctly check the return value of efi_dp_from_file()
2019-11-14Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini
- Clearfog: Fix SD card booting (Baruch) - Fix potential dereference NULL pointer in dram_init() (Chris)
2019-11-14patman: fix coverletter cc list with nullsRobert Beckett
fixes: 8ab452d5877638a97e5bdd521d119403b70b45f5 When compiling list of cover letter cc addresses, using null as a separater, then encoding to utf-8 results in lots of "\x00" as separators. patman then doesnt understand that when it comes to repoting the list to send-email. Fix this by not encoding to utf-8, as done for the other patch files. Signed-off-by: Robert Beckett <bob.beckett@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-11-14patman: fix some typos in commentsAnatolij Gustschin
s/Subprocress/Subprocess/ s/easiler/easier/ s/repositiory/repository/ s/rangem/range/ s/Retruns/Returns/ Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-11-14sandbox: use correct type reading /proc/self/mapsHeinrich Schuchardt
Compiling arch/sandbox/cpu/os.c results in an error ../arch/sandbox/cpu/os.c: In function ‘os_find_text_base’: ../arch/sandbox/cpu/os.c:823:12: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast] 823 | base = (void *)addr; | ^ cc1: all warnings being treated as errors The size of void* differs from that of unsigned long long on 32bit systems. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-11-14tests: add OP-TEE test suiteHeiko Stuebner
OP-TEE can get supplied with a devicetree and will then insert its firmware node and reserved-memory sections into it. As this devicetree often is not the one supplied to a later loaded kernel, a previous commit added functionality to transfer these nodes onto that new devicetree. To make sure this functionality stays intact, also add a test for the transfer functionality. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-11-14image: fdt: copy possible optee nodes to a loaded devicetreeHeiko Stuebner
The loading convention for optee or any other tee on arm64 is as bl32 parameter to the trusted-firmware. So TF-A gets invoked with the TEE as bl32 and main u-boot as bl33. Once it has done its startup TF-A jumps into the bl32 for the TEE startup, returns to TF-A and then jumps to bl33. All of them get passed a devicetree as parameter and all components often get loaded from a FIT image. OP-TEE will create additional nodes in that devicetree namely a firmware node and possibly multiple reserved-memory nodes. While this devicetree is used in main u-boot, in most cases it won't be the one passed to the actual kernel. Instead most boot commands will load a new devicetree from somewhere like mass storage of the network, so if that happens u-boot should transfer the optee nodes to that new devicetree. To make that happen introduce optee_copy_fdt_nodes() called from the dt setup function in image-fdt which after checking for the optee presence in the u-boot dt will make sure a optee node is present in the kernel dt and transfer any reserved-memory regions it can find. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
2019-11-14fdtdec: only create phandle if caller wants it in fdtdec_add_reserved_memory()Heiko Stuebner
The phandlep pointer returning the phandle to the caller is optional and if it is not set when calling fdtdec_add_reserved_memory() it is highly likely that the caller is not interested in a phandle to the created reserved-memory area and really just wants that area added. So just don't create a phandle in that case. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-11-14fdtdec: protect against another NULL phandlep in fdtdec_add_reserved_memory()Heiko Stuebner
The change adding fdtdec_add_reserved_memory() already protected the added phandle against the phandlep being NULL - making the phandlep var optional. But in the early code checking for an already existing carveout this check was not done and thus the phandle assignment could run into trouble, so add a check there as well, which makes the function still return successfully if a matching region is found, even though no-one wants to work with the phandle. Fixes: c9222a08b3f7 ("fdtdec: Implement fdtdec_add_reserved_memory()") Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-11-14pinctrol: dm: remove the function pinctrl_decode_pin_configPatrick Delaunay
Remove the pinctrl_decode_pin_config() API, because this function is unused and not compatible with livetree (it uses fdtdec_get_bool instead of ofnode API). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
generated by cgit (git 2.34.1) at 2024-12-26 19:18:03 +0000