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2019-11-08freescale/powerpc: Rename the config CONFIG_SECURE_BOOT nameUdit Agarwal
Rename the CONFIG_SECURE_BOOT name to CONFIG_NXP_ESBC to avoid conflicts with UEFI secure boot. Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08freescale/layerscape: Rename the config CONFIG_SECURE_BOOT nameUdit Agarwal
Rename CONFIG_SECURE_BOOT to CONFIG_NXP_ESBC to avoid conflict with UEFI secure boot. Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08configs: spi: Add the SPI_FLASH_BAR for ESPIXiaowei Bao
Add the SPI_FLASH_BAR for the ESPI controller of FSL, this entry is missed by commit 6d8251783641 ("configs: Don't use SPI_FLASH_BAR as default") Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08fsl-layerscape: fix warning if no hwconfig is definedPankaj Bansal
While getting the 'subarg' of 'hwconfig' env variable in config_core_prefetch(), if no hwconfig variable is defined, below warning is received: WARNING: Calling __hwconfig without a buffer and before environment is ready Fix this by checking 'hwconfig' env variable. If not found return without further processing. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Tested-by: Michael Walle <michael@walle.cc>
2019-11-08usb: xhci: support 1.1 or later versionChunfeng Yun
The xHCI 1.1 version also need set Transfer Type field Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-11-08drivers: net: fsl_enetc: fix RGMII configurationMichael Walle
Add the missing RGMII PHY modes in which case the MAC has configure its RGMII settings. The only difference between these modes is the RX and TX delay configuration. A user might choose any RGMII mode in the device tree. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08drivers: net: fsl_enetc: set phydev->nodeMichael Walle
The saved ofnode is used by some PHY drivers to access the device tree node of the PHY. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08armv8: fsl-layerscape: introduce fsl_board_late_init()Michael Walle
The fsl-layerscape already occupies board_late_init(), therefore it is not possible for a board to have its own board_late_init(). Introduce fsl_board_late_init() which can be implemented in the board specific code. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08armv8: fsl-lsch3: convert CONFIG_TARGET_x to CONFIG_ARCH_xMichael Walle
The clocks are not dependent on the target but only on the SoC. Therefore, convert the CONFIG_TARGET_x macros to the corresponding CONFIG_ARCH_x. This will allow other targets to automatically use the common code. Otherwise every new target would have to add itself to the "#if defined(CONFIG_TARGET_x) || .." macros. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08armv8: ls1028a: add erratum A-050382 workaroundLaurentiu Tudor
Erratum A-050382 states that the eDMA ICID programmed in the eDMA_AMQR register in DCFG is not correctly forwarded to the SMMU. The workaround consists in programming the eDMA ICID in the eDMA_AMQR register in DCFG to 40. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08armv8: lx2160a: add icid setup for platform devicesLaurentiu Tudor
Add ICID setup for the platform devices contained on this chip: usb, sata, sdhc, sec. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08fsl-layerscape: add missing SATA3 and SATA4 base addressesLaurentiu Tudor
LX2160A chips have 4 sata controllers. Add missing base addresses for SATA3 and SATA4. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08armv8: ls2088a: add icid setup for platform devicesLaurentiu Tudor
Add ICID setup for the platform devices contained on this chip: usb, sata, sdhc, sec. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08fsl-layerscape: fix compile error with sec fw disabledLaurentiu Tudor
If SEC FW support is not enabled (ARMV8_SEC_FIRMWARE_SUPPORT=n), below compilation error appears arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h:169:4: error: 'CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT' undeclared here (not in a function) Fix it by wrapping with CONFIG_IS_ENABLED(). Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08armv8: fsl-layerscape: guard caam specific definesLaurentiu Tudor
These macros should only be used when CONFIG_FSL_CAAM is present. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08fsl-layerscape: do not use layerscape EFI reset if PSCI usedMathew McBride
If the secure world reset handlers are used (via CONFIG_PSCI_RESET), then do not use the layerscape-specific implementation. Signed-off-by: Mathew McBride <matt@traverse.com.au> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08armv8: dts: ls1088a: add PSCI binding for LS1088AMathew McBride
This allows the use of PSCI calls to trusted firmware to initiate reset and poweroff events with CONFIG_PSCI_RESET and CONFIG_ARM_PSCI_FW. This is desirable, for example, if the target board has implemented a custom reset or poweroff procedure in EL3. Signed-off-by: Mathew McBride <matt@traverse.com.au> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08pci: layerscape: Only set EP CFG READY bitPankaj Bansal
In ls_pcie_ep_enable_cfg(), as part of EP setup,config ready bit of pci controller is set, so that RC can read the config space of EP. While setting the config ready bit, LTSSM_EN bit in same register was also inadvertently getting cleared. This restarts the link training between RC and EP. Update code to just set the desired CFG_READY bit (bit 0), while leaving the other bits unchanged. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-07configs: j721e_evm_r5_defconfig: Remove SPL multi-DTB FIT supportAndrew F. Davis
The SPL FIT will only have one DTB, so remove support for multi-DTB. This also removes an early access to EEPROM used to select the DTB that is not valid in SPL at the point at which it is accessed, that always returns false for GP devices and causes a firewall expection on HS. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-11-07Kconfig: ti: Make board detect EEPROM addresses depend BOARD_DETECTAdam Ford
There is an option to enable the board detection for TI platforms. If this is option is not set, there is no reason to set the EEPROM bus address or chip address. This patch makes both EEPROM_BUS_ADDRESS and EEPROM_CHIP_ADDRESS depend on TI_I2C_BOARD_DETECT. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-11-07configs: omap3_logic_somlv: Remove GPIO from SPLAdam Ford
The SPL is too tight, and it cannot start any longer. To help reduce the size of SPL, we need to remove some non-critical features. This patch removes SPL_GPIO_SUPPORT to free up some operating space. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-11-07ARM: dts: logicpd-som-lv-37xx-devkit-u-boot: Remove unused GPIOAdam Ford
The only GPIO bank needed in SPL is GPIO4 and the SPL space is tight. This patch removes the all but GPIO4 from the spl device tree to reduce the SPL footprint. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-11-07Revert "ARM: omap3_logic/omap35_logic: Enable GPIO in SPL"Adam Ford
The SPL is too tight, and it cannot start any longer. To help reduce the size of SPL, we need to remove some non-critical features. This reverts commit 66063a7c1388fb724e8671b03c529fb5cda992dd. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-11-07ARM: dts: logicpd-torpedo-37xx-devkit-u-boot: Remove unused GPIOAdam Ford
The only GPIO bank needed in SPL is GPIO4 and the SPL space is tight. This patch removes the all but GPIO4 from the spl device tree to reduce the SPL footprint. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-11-07ARM: omap3_logic: Power on MMC when setting up PMICAdam Ford
The PMIC enables power to the MMC card by default, but depending on the state it was left when restarted, it's possible the MMC may be powered down. This patch patch explicitly tells the twl4030 to power the MMC. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-11-07configs: j721e_evm_r5_defconfig: Enable AVS Class 0 & dependent configsKeerthy
Enable AVS Class 0 & dependent config options. Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07configs: am65x_evm_r5_defconfig: Enable AVS class 0 supportTero Kristo
Enable AVS class 0 support for the R5 SPL bootloader. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07configs: am65x_evm_r5_defconfig: Enable TPS62363 regulator supportTero Kristo
TPS62363 is used to control the MPU_VDD voltage, so enable the driver for this. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07arm: dts: k3-j721e-r5-common-proc-board: Hook buck12_reg to vtm supplyKeerthy
Hook buck12_reg to vtm avs supply Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07arm: dts: k3-j721e-r5-common: Add tps65941 node and dependent wkup_i2c0 nodeKeerthy
Add tps65941 node and dependent wkup_i2c0 node needed for AVS class 0 support Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07arm: dts: k3-j721e-r5-common-proc-board: Add VTM nodeKeerthy
Add VTM node for voltage and thermal management. For u-boot, this is needed for supporting AVS class 0, as the efuse values for the OPPs are stored under the VTM. Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07arm: dts: k3-am654-r5-base-board: enable wkup_vtm0 node and link in suppliesTero Kristo
Link the vdd-supplies for the voltage domains under the VTM node. Also, enable the node under SPL. This will enable the AVS class 0 support on am65x-evm board. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07arm: dts: k3-am654-r5-base-board: add supply rail for MPUTero Kristo
MPU voltage on AM65x-evm is controlled via the TPS62363 chip attached to i2c0 bus. Add device node for this so that it can be controlled via a regulator driver. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07arm: dts: k3-am654-r5-base-board: enable wkup_i2c0 driver for splTero Kristo
Enable wkup_i2c0 as this is needed for voltage control. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07arm: dts: k3-am654-r5-base-board: Add VTM nodeKeerthy
Add VTM node for voltage and thermal management. For u-boot, this is needed for supporting AVS class 0, as the efuse values for the OPPs are stored under the VTM. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07arm: mach-k3: j721e_init: Initialize avs class 0Keerthy
Initialize avs class 0 Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07arm: mach-k3: am6_init: Initialize AVS class 0Keerthy
Initialize AVS class 0 so that mpu voltage rail is programmed to the AVS class 0 compensated value. Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07power: regulator: tps65941: add regulator supportKeerthy
The driver provides regulator set/get voltage enable/disable functions for tps65941 family of PMICs. Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07power: pmic: tps65941: Add support for tps65941 family of PMICsKeerthy
Add support to bind the regulators/child nodes with the pmic. Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07misc: k3_avs: Add j721e supportKeerthy
j721e SoCs have different OPP tables. Add support for the same. Note: DM Still has lot of voltages TBD hence the correct values need to be programmed once they are published. Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07power: regulator: tps6236x: add support for tps6236x regulatorsTero Kristo
TPS6236x is a family of step down DC-DC converters optimized for battery powered portable applications for a small solution size. Add a regulator driver for supporting these devices. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07clk: clk-ti-sci: Notify AVS driver upon setting clock rateKeerthy
Notify AVS driver upon setting clock rate so that voltage is changed accordingly. Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07misc: k3_avs: add driver for K3 Adaptive Voltage Scaling Class 0Tero Kristo
Adaptive Voltage Scaling is a technology used in TI SoCs to optimize the operating voltage based on characterization data written to efuse during production. Add a driver to support this feature for K3 line of SoCs, initially for AM65x. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07arm: add initial support for the Phytium Durian Boardliu hao
This adds platform code and the device tree for the Phytium Durian Board. The initial support comprises the UART and the PCIE. Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Tom Rini <trini@konsulko.com> Cc: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Steven Hao <liuhao@phytium.com.cn>
2019-11-07cmd: mtdparts: Fix build with option ..._SHOW_NET_SIZESAlexander Dahl
That option is currently not used by any defconfig and could not be set anymore since it became mandatory to used Kconfig when introducing new options with U-Boot v2016.11 or commit eed921d92348 ("Kconfig: Add a whitelist of ad-hoc CONFIG options") and commit 371244cb19f9 ("Makefile: Give a build error if ad-hoc CONFIG options are added"). It was also not considered when fixing build warnings in commit 39ac34473f3c ("cmd_mtdparts: use 64 bits for flash size, partition size & offset") and could probably not be compiled anyway after commit dfe64e2c8973 ("mtd: resync with Linux-3.7.1"), which renamed some members of struct mtd_info … so it was probably broken since then, which was U-Boot v2013.07-rc1. However it still seems to work, see example output below: U-Boot 2019.10-00035-g06a9b259ca-dirty (Oct 30 2019 - 14:03:44 +0100) CPU: SAMA5D27 1G bits DDR2 SDRAM Crystal frequency: 24 MHz CPU clock : 492 MHz Master clock : 164 MHz Model: *** DRAM: 128 MiB NAND: 256 MiB Loading Environment from NAND... OK In: serial@f8020000 Out: serial@f8020000 Err: serial@f8020000 Net: eth0: ethernet@f8008000 Hit keys 'tt' to stop autoboot (3 seconds). U-Boot> mtdparts device nand0 <atmel_nand>, # parts = 8 #: name size net size offset mask_flags 0: bootstrap 0x00040000 0x00040000 0x00000000 1 1: uboot 0x000c0000 0x000c0000 0x00040000 1 2: env1 0x00040000 0x00040000 0x00100000 0 3: env2 0x00040000 0x00040000 0x00140000 0 4: fpga_led 0x00040000 0x00040000 0x00180000 1 5: reserved 0x00040000 0x00040000 0x001c0000 1 6: rootfs_rec 0x03200000 0x03200000 0x00200000 1 7: filesystem 0x0cc00000 0x0cb80000 (!) 0x03400000 0 active partition: nand0,0 - (bootstrap) 0x00040000 @ 0x00000000 defaults: mtdids : nand0=atmel_nand mtdparts: mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env1),256k(env2),256k(fpga_led)ro,256k(reserved)ro,50M(rootfs_rec)ro,-(filesystem) Signed-off-by: Alexander Dahl <ada@thorsis.com>
2019-11-07cmd: nand: Remove not used declarationAlexander Dahl
This declaration is not used anywhere in the whole tree. There is a function 'mtd_id_parse()' which was renamed from 'id_parse()' in commit 68d7d65100e8 ("Separate mtdparts command from jffs2"), but that function is not used (anymore?) in cmd nand and build is fine without that declaration, so it's probably just safe to remove. Signed-off-by: Alexander Dahl <ada@thorsis.com>
2019-11-07arm: caches: Disable mmu only if mmu is availableLokesh Vutla
As part of disabling caches MMU as well gets disabled. But MMU is not available on all armv7 cores like R5F. So disable MMU only if it is available. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-11-07hush: re-sequence includesHeinrich Schuchardt
'make tests' on a 32bit ARM system leads to In file included from ../common/cli_hush.c:79: ../include/malloc.h:364:7: error: conflicting types for ‘memset’ void* memset(void*, int, size_t); ^~~~~~ In file included from ../include/compiler.h:126, from ../include/env.h:12, from ../common/cli_hush.c:78: ../include/linux/string.h:103:15: note: previous declaration of ‘memset’ was here extern void * memset(void *,int,__kernel_size_t); ^~~~~~ In file included from ../common/cli_hush.c:79: ../include/malloc.h:365:7: error: conflicting types for ‘memcpy’ void* memcpy(void*, const void*, size_t); ^~~~~~ In file included from ../include/compiler.h:126, from ../include/env.h:12, from ../common/cli_hush.c:78: ../include/linux/string.h:106:15: note: previous declaration of ‘memcpy’ was here extern void * memcpy(void *,const void *,__kernel_size_t); ^~~~~~ According to the U-Boot coding style guide common.h should be the first include. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-11-07dlmalloc: calloc: fix zeroing early allocationsSimon Goldschmidt
When full malloc is enabled and SYS_MALLOC_F is also enabled, the simple pre-reloc heap is used before relocation. In this case, calloc() uses the MALLOC_ZERO macro to zero out the allocated memory. However, since this macro is specially crafted for the dlmalloc implementation, it does not always work for simple malloc. For example, when allocating 16 bytes via simple malloc, only the first 12 bytes get zeroed out. The last 4 bytes will remain untouched. This is a problem for DM drivers that are allocated before relocation: memory allocated via 'platdata_auto_alloc_size' might not be set to zero, resulting in bogus behaviour. To fix this, use 'memset' instead of 'MALLOC_ZERO' to zero out memory that compes from simple malloc. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-11-07spl: fix SPI config dependenciesSimon Goldschmidt
As SPL_SPI_FLASH_SUPPORT cannot work without SPL_SPI_SUPPORT, fix dependencies to prevent enabling SPI flash support without basic SPI support. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>