summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2019-09-03riscv: dts: move out AE350 L2 node from cpus nodeRick Chen
When L2 node exists inside cpus node, uclass_get_device can not parse L2 node successfully. So move it outside from cpus node. Also add tag-ram-ctl and data-ram-ctl attributes for v5l2 cache controller driver. This can adjust timing by requirement from dtb to improve performance. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-03riscv: cache: Flush L2 cache before jump to linuxRick Chen
Flush and disable L2 cache in dcache_disable() which will be called in cleanup_before_linux() before jump to linux. The sequence will be preferred as below: L1 flush -> L1 disable -> L2 flush -> L2 disable Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-03riscv: ax25: add imply v5l2 cache controllerRick Chen
Select the v5l2 UCLASS_CACHE driver for ax25. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-03riscv: ae350: use the v5l2 driver to configure the cacheRick Chen
Find the UCLASS_CACHE driver to configure the cache controller's settings. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-03dm: cache: add v5l2 cache controller driverRick Chen
Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse the cache settings from the dtb. In this version tag and data ram control timing can be adjusted by the requirement from the dtb. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-03dm: cache: Add enable and disable ops for sandbox and testRick Chen
Add cache enable and disable ops for test coverage. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-03dm: cache: Add enable and disable ops for cache uclassRick Chen
Add cache enable/disable ops to the DM cache uclass driver Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-03riscv: andes_plic: init plic by scanning each cpu nodeRick Chen
Initialize plic driver by ofnode_for_each_subnode() instead of cpu_get_count(). This way can support to skip some harts which maybe marked as unavailable, but the cpu node exists indeed. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-03riscv: update fix_rela_dynMarcus Comstedt
The addend is now added for RELOC_TYPE relocs. Also, changed the loop structure so that all the R_RISCV_RELATIVE relocs are not required to be at the beginning of the list. Signed-off-by: Marcus Comstedt <marcus@mc.pp.se> Cc: Rick Chen <rick@andestech.com>
2019-09-03riscv: tools: Handle addend to absolute reloc in prelink-riscvMarcus Comstedt
Previously the handling of R_RISCV_32 and R_RISCV_64 would simply insert the value of the symbol and ignore any addend. However, there exist relocs where the addend is non-zero: 0000000080250900 R_RISCV_64 efi_runtime_services+0x0000000000000068 0000000080250910 R_RISCV_64 efi_runtime_services+0x0000000000000038 0000000080250920 R_RISCV_64 efi_runtime_services+0x0000000000000018 0000000080250930 R_RISCV_64 efi_runtime_services+0x0000000000000020 0000000080250980 R_RISCV_64 efi_runtime_services+0x0000000000000048 0000000080250990 R_RISCV_64 efi_runtime_services+0x0000000000000050 00000000802509a0 R_RISCV_64 efi_runtime_services+0x0000000000000058 0000000080250940 R_RISCV_64 systab+0x0000000000000030 0000000080250950 R_RISCV_64 systab+0x0000000000000040 0000000080250960 R_RISCV_64 systab+0x0000000000000050 0000000080250970 R_RISCV_64 systab+0x0000000000000060 In these cases the addend needs to be added to the symbol value to get the correct value for the reloc. Signed-off-by: Marcus Comstedt <marcus@mc.pp.se> Cc: Rick Chen <rick@andestech.com>
2019-09-03sifive-fu540: config: Add mmc0 as a boot target deviceAlistair Francis
Add the mmc0 device as a BOOT_TARGET_DEVICES. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-03riscv: sifive: fu540: set serial environment variable from otpSagar Shrikant Kadam
This patch sets the serial# environment variable by reading the board serial number from the OTP memory region. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-03riscv: cpu: Skip unavailable hart in the get_count() opBin Meng
We should not count in hart that is marked as not available in the device tree in riscv_cpu_get_count(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-09-01Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini
- r8a66597 usb changes
2019-08-31Merge branch '2019-08-30-master-imports'Tom Rini
- Assorted bug fixes
2019-08-31Makefile: fix newline escaping for CONFIG_DEFAULT_ENV_FILERasmus Villemoes
I wanted this to be compatible with mkenvimage, including the ability to embed newlines in variables by escaping them. But I failed to check that it works more than once. Fixes: f3d8f7dd73a (Allow providing default environment from file) Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2019-08-31Revert "vexpress64: fvp dram: add DRAM configuration"Ryan Harkin
This reverts commit fc04b923541d984b1544056fd3bfa8129d4e5aac where the FVP DRAM configuration was added. Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Sudeep Holla <sudeep.holla@arm.com>
2019-08-30siemens: avoid out of bound accessHeinrich Schuchardt
char num[1]; sprintf(num, "%d", i); leads to a buffer overrun. Simplify the overly complex coding. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Heiko Schocher <hs@denx.de>
2019-08-30arm: omap2: am43xx: Enable CONFIG_DM_USBSuniel Mahesh
Enable CONFIG_DM_USB to remove compile warning for am43xx based targets: ===================== WARNING ====================== This board does not use CONFIG_DM_USB. Please update the board to use CONFIG_DM_USB before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. ==================================================== Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>
2019-08-30Makefile: clean build generated SPL binary for TI AM65xSuniel Mahesh
TI AM65x platforms (evm and HS) generate an SPL image 'tispl.bin*' and there is no rule for cleanup. Added entry for cleanup in clean target. Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>
2019-08-30configs: enable CONFIG_BLOCK_CACHE for mt7623n_bpir2Weijie Gao
This patch enables CONFIG_BLOCK_CACHE for mt7623n_bpir2. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-08-30mmc: invalidate block cache after hwpart switched successfullyWeijie Gao
eMMC device has multiple hw partitions both address from zero. However the mmc driver lacks block cache invalidation for switch hwpart. This causes a problem that data of current hw partition is cached before switching to another hw partition. And the following read operation of the latter hw partition will get wrong data when reading from the addresses that have been cached previously. To solve this problem, invalidate block cache after a successful mmc_switch_part() operation. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> Tested-by: Felix Brack <fb@ltec.ch>
2019-08-30Revert "blk: Invalidate block cache when switching hwpart"Weijie Gao
This reverts commit 0ebe112d09b48230ba4be833cd3504b06997d9a4. Most block devices have only one hwpart. Multiple hwparts only found used by eMMC devices in u-boot. The mmc driver do blk_dselect_hwpart() at the beginning of mmc_bread() which causes block cache being invalidated too frequently and makes block cache useless. So it's not a good idea to put blkcache_invalidate() in the common functions. It should be called inside mmc_select_hwpart(). Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> Tested-by: Felix Brack <fb@ltec.ch>
2019-08-30board_f: fix noncached reservation calculationStephen Warren
The current code in reserve_noncached() has two issues: 1) The first update of gd->start_addr_sp always rounds down to a section start. However, the equivalent calculation in cache.c:noncached_init() always first rounds up to a section start, then subtracts a section size. These two calculations differ if the initial value is already rounded to section alignment. 2) The second update of gd->start_addr_sp subtracts exactly CONFIG_SYS_NONCACHED_MEMORY, whereas the equivalent calculation in cache.c:noncached_init() rounds the noncached size up to section alignment before subtracting it. The two calculations differ if the noncached region size is not a multiple of the MMU section size. In practice, one/both of those issues causes a practical problem on Jetson TX1; U-Boot triggers a synchronous abort during initialization, likely due to overlapping use of some memory region. This change fixes both these issues by duplicating the exact calculations from noncached_init() into reserve_noncached(). However, this fix assumes that gd->start_addr_sp on entry to reserve_noncached() exactly matches mem_malloc_start on entry to noncached_init(). I haven't traced the code to see whether it absolutely guarantees this in all (or indeed any!) cases. Consequently, I added some comments in the hope that this condition will continue to be true. Fixes: 5f7adb5b1c02 ("board_f: reserve noncached space below malloc area") Cc: Vikas Manocha <vikas.manocha@st.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2019-08-29Merge tag 'efi-2019-10-rc4' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for UEFI sub-system for v2019.10-rc4 Enable the unit test for UEFI runtime service Exit() on x86_64. Use as standalone UEFI binary for testing the handling of exceptions.
2019-08-29Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xxTom Rini
Enable DM PCI for T2080RDB, T4240RDB, T1024RDB, T1042D4RDB, P1020RDB, P2020RDB, P2041RDB, P3041DS, P4080DS, and MPC8548CDS
2019-08-29Merge tag 'u-boot-amlogic-20190828' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - add missing g12b clock driver compatible, fixing odroid-n2 usb support
2019-08-29efi_selftest: use standalone UEFI program for exceptionHeinrich Schuchardt
To fully demonstrate crash outputs for UEFI images provide a standalone UEFI application that tries to invoke an illegal opcode. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-08-29efi_selftest: enable Exit() unit test on x86_64Heinrich Schuchardt
Enable unit tests for StartImage() and Exit() unit tests on x86_64. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-08-28configs: MPC8548CDS: Enable PCIe driverHou Zhiqiang
Enable the DM PCIe driver in MPC8548CDS defconfig. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28powerpc: MPC8548CDS: Disable legacy PCIe driver when DM_PCI is enabledHou Zhiqiang
Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28MPC8548: dts: Added PCIe DT nodeHou Zhiqiang
MPC8548 integrated a PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 1.0a, and this patch is to add DT node for the PCIe controller. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Add MPC8548 PCIe supportHou Zhiqiang
Add compatible string for MPC8548 PCIe. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28powerpc: MPC85xxCDS: Disable legacy PCI fixup when DM_PCI is selectedHou Zhiqiang
Disable legacy PCI and PCIe fixup when CONFIG_DM_PCI is selected. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28powerpc: MPC8548CDS: Compile legacy PCIe routines conditionallyHou Zhiqiang
Compile the legacy PCIe initialization routines only when DM_PCI is not enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28configs: P5040DS: Enable PCIe driverHou Zhiqiang
Enable the DM PCIe driver in P5040DS defconfig. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> eviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28P5040: dts: Added PCIe DT nodesHou Zhiqiang
P5040 integrated 3 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 2.0, and this patch is to add DT node for each PCIe controller. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Add P5040 PCIe supportHou Zhiqiang
Add compatible string for P5040 PCIe. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28configs: P4080DS: Enable PCIe driverHou Zhiqiang
Enable the DM PCIe driver in P4080DS defconfig. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28P4080: dts: Added PCIe DT nodesHou Zhiqiang
P4080 integrated 3 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 2.0, and this patch is to add DT node for each PCIe controller. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Add P4080 PCIe supportHou Zhiqiang
Add compatible string for P4080 PCIe. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28configs: P3041DS: Enable PCIe driverHou Zhiqiang
Enable the DM PCIe driver in P3041DS defconfig. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28powerpc: corenet_ds: Disable legacy PCIe driver when DM_PCI is enabledHou Zhiqiang
Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28P3041: dts: Added PCIe DT nodesHou Zhiqiang
P3041 integrated 4 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 2.0, and this patch is to add DT node for each PCIe controller. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Add P3041 PCIe supportHou Zhiqiang
Add compatible string for P3041 PCIe. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28configs: P2041RDB: Enable PCIe driverHou Zhiqiang
Enable the DM PCIe driver in P2041RDB defconfig. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28powerpc: P2041RDB: Disable legacy PCIe driver when DM_PCI is enabledHou Zhiqiang
Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28P2041: dts: Added PCIe DT nodesHou Zhiqiang
P2041 integrated 3 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 2.0, and this patch is to add DT node for each PCIe controller. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Add P2041 PCIe supportHou Zhiqiang
Add compatible string for P2041 PCIe. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28powerpc: p_corenet: Compile legacy PCIe routines conditionallyHou Zhiqiang
Compile the legacy PCIe initialization routines for P2041RDB, P3041, P4080, P5020 and P5040 DS boards only when DM_PCI is not enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
generated by cgit (git 2.34.1) at 2025-01-15 17:09:09 +0000