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2020-05-01imx8qxp_mek: Remove SPL watchdog optionFabio Estevam
Currently the following watchdog error is seen in SPL: U-Boot SPL 2020.04-00407-g8d5d3bcf3c (Apr 20 2020 - 09:48:09 -0300) Normal Boot WDT: Not found! ... There is no watchdog driver for i.MX8 at the moment, nor code for configuring the watchdog in SPL, so remove the CONFIG_SPL_WATCHDOG_SUPPORT option for now. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
2020-05-01imx8: Run SPL with caches enabledFabio Estevam
It is safe to run SPL with caches enabled on i.MX8, so remove such restriction. Signed-off-by: Fabio Estevam <festevam@gmail.com> Acked-by: Peng Fan <peng.fan@nxp.com> Acked-by: Oliver Graute <oliver.graute@kococonnector.com> Acked-by: Anatolij Gustschin <agust@denx.de> Tested-by: Igor Opaniuk <igor.opaniuk@toradex.com> Acked-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2020-05-01config: apalis-imx8: Enable FEC TXC delayPhilippe Schenker
define FEC_ENET_ENABLE_TXC_DELAY to enable the delay on TXC line on the MAC. This has to be done in order to meet RGMII specs. According to RGMII specs the clock should get delayed so the edges of the clock are preferrably in the middle of the edges of data-lines so they can be sampled properly. Our PHY expects the MAC to delay TXC line, as it is also written in the spec. This patch makes sure the TXC delay on the FEC is enabled Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2020-05-01net: fec: Add possibility to enable TXC delayPhilippe Schenker
This patch enables the possibility to set FEC_ENET_ENABLE_TXC_DELAY or FEC_ENET_ENABLE_RXC_DELAY so one can via a define enable the RXC or TXC delay in the MAC. Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2020-05-01board: apalis_imx6: Add KSZ9131 phy skew settingsPhilippe Schenker
This patch adds skew register settings for KSZ9131. It checks first which phy is on the board and then applies the correct skew settings. Skew settings calculation for the KSZ9131: The i.MX6 SoC has an output skew tolerance of -100ps to 900ps. All PCB traces where routed exactly the same length so we can calculate the skew settings without taking the length into consideration. The traces are all length matched. RXC skew (PHY to MAC): - We use the 2ns DLL controlled delay on the PHY - We do not use the skew registers This results in the following values: RXC PHY fixed Delay 2000ps PHY Added Delay 0ps T_setup_R min 2.00ns T_setup_R typ 2.00ns T_setup_R max 2.00ns T_hold_R min 1.60ns T_hold_R typ 2.00ns T_hold_R max 2.40ns That means we are well within RGMII specs. TXC skew (MAC to PHY): - We use the 2ns DLL controlled delay on the PHY - We then subtract ~0.6ns with TXD[0:3] and TXC clock pad skew register in a resulting ~1.4ns delay. This results in the following values under consideration of the tolerances: TXC min TXC typ TXC max MAC min -100ps -100ps -100ps MAC max 900ps 900ps 900ps PHY fixed Delay 2000ps 2000ps 2000ps PHY added Delay -340ps -600ps -859ps T_setup_T min 1.56ns 1.30ns 1.04ns T_setup_T typ 2.06ns 1.80ns 1.54ns T_setup_T max 2.56ns 2.30ns 2.04ns T_hold_T min 1.04ns 1.30ns 1.56ns T_hold_T typ 1.94ns 2.20ns 2.46ns T_hold_T max 2.84ns 3.10ns 3.36ns This shows that T_hold_T min and T_setup_T min times are out of spec for RGMII timing. However the KSZ9131 has a minimal value for this time of 0.8ns which is met under all circumstances. Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
2020-05-01board: verdin-imx8mm: Add KSZ9131 phy skew settingsPhilippe Schenker
This patch determines which phy is placed on the board with the PHY ID then it sets the same settings for KSZ9031 as before but for KSZ9131 it enables both RXC and TXC delay lines in the PHY. This will compensate the missing delay from the MAC. Other skew settings are not needed as the traces on board are routed exactly the same length Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com> Tested-by: Igor Opaniuk <igor.opaniuk@toradex.com> Acked-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2020-05-01verdin-imx8mm: Change board phy skew values for our ksz9031Philippe Schenker
This patches uses the existing functions for interacting with the KSZ9031 and uses the values appropriate for our board. Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com> Tested-by: Igor Opaniuk <igor.opaniuk@toradex.com> Acked-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2020-05-01net: phy: micrel: Add basic support for KSZ9131Philippe Schenker
This adds basic support for the new Micrel KSZ9131 phy. Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
2020-05-01net: phy: micrel: Use defines for PHY_IDs and MASKPhilippe Schenker
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
2020-05-01mx8mq_evk: Remove unrelated commentFabio Estevam
The comment does not relate to the setup_i2c() function, so just remove it. Signed-off-by: Fabio Estevam <festevam@gmail.com>
2020-05-01imx8mp_evk: Remove unrelated commentFabio Estevam
The comment does not relate to the setup_i2c() function, so just remove it. Signed-off-by: Fabio Estevam <festevam@gmail.com>
2020-05-01imx: imx8m: Don't use the addr parameter of reset_cpuClaudius Heine
imx8m has the only implementation of `reset_cpu` which does not ignore the addr parameter and instead gives it some meaning as the base address of watchdog registers. This breaks convention with the rest of U-Boot where the parameter is ignored and callers are passing in 0. Fixes: d2041725e84b ("imx8m: restrict reset_cpu") Co-Authored-by: Harald Seiler <hws@denx.de> Signed-off-by: Claudius Heine <ch@denx.de> Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Marek Vasut <marex@denx.de>
2020-05-01imx: imx8m*: Remove do_reset from board filesClaudius Heine
Use the `do_reset` implementation of `arch/arm/lib/reset.c` in SPL instead. It is very close to what is done here, anyway, and plays more nicely with the rest of U-Boot than adding a custom `do_reset` implementation into board files. `do_reset` from `arch/arm/lib/reset.c` calls `reset_cpu` with 0 as the addr parameter while the boards are passing WDOG1_BASE_ADDR. This is ok because the `reset_cpu` implementation uses WDOG1_BASE_ADDR by default if 0 is passed in. Co-Authored-by: Harald Seiler <hws@denx.de> Signed-off-by: Claudius Heine <ch@denx.de> Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Marek Vasut <marex@denx.de>
2020-05-01ARM: reset: use do_reset in SPL/TPL if SYSRESET was not enabled for themClaudius Heine
In case CONFIG_SYSRESET is set, do_reset from reset.c will not be available anywere, even if SYSRESET is disabled for SPL/TPL. 'do_reset' is called from SPL for instance from the panic handler and PANIC_HANG is not set Signed-off-by: Claudius Heine <ch@denx.de> Reviewed-by: Marek Vasut <marex@denx.de>
2020-05-01imx8: Configure SNVSFranck LENORMAND
Add a module to configure the tamper and secure violation of the SNVS using the SCU API. The module also adds some commands: - snvs_cfg: Configure the SNVS HP and LP registers - snvs_dgo_cfg: Configure the SNVS DGO bloc if present (8QXP) - tamper_pin_cfg: Change the configuration of the tamper pins - snvs_clear_status: Allow to write to LPSR and LPTDSR to clear status bits Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01imx8: Update SCFW API to version 1.5Ye Li
Sync the latest SCFW API with below commit 6dcd0242ae7a53ac ("SCF-105: Revert accidental change") to add interfaces for PM resource reset and read/write SNVS security violation and tamper DGO registers. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01imx8: scu api: Add support for SECO manufacturing protection APIsBreno Lima
SECO provides APIs to support CAAM manufacturing protection: - sc_seco_get_mp_key() - sc_seco_get_mp_sign() - sc_seco_update_mpmr() Add SCFW APIs support. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Breno Lima <breno.lima@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01doc: ahab: Add encrypted boot documentation for i.MX8/8x devicesBreno Lima
Add AHAB encrypted boot documentation for i.MX8/8x family devices covering the following topics: - How to encrypt and sign the 2nd container in flash.bin image. - How to encrypt and sign a standalone container image. Include a CSF example to encrypt 2nd container in flash.bin image. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Catia Han <yaqian.han@nxp.com> Signed-off-by: Breno Lima <breno.lima@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01imx8m: Enable WDOG_B for timeoutYe Li
When doing reset_cpu, in normal case the WDOG_B outputs immediately after we clean WDA bit. But on mscale, the WDOG_B may be later than internal reset, and cause PMIC not reset. As we enabled the SD3.0 support, the PMIC must be reset to reset SD card. Change the reset_cpu to enable the WDOG_B for timeout as well, and set WDOG timeout to 1s. Reviewed-by: Fabio Estevam <festevam@gmail.com> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01imx8mm: clock: fix fracpll decode issueYe Li
The fracpll decoding is using the bit definitions for int pll. Most of them are same, but the CLKE bit is different. Fix the wrong CLKE_MASK for fracpll and correct all bit definitions in fracpll decoding. Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01imx8: parser: fix some bad debug message formatingPeng Fan
In SPL build, the formatting '%llx' in debug() is not supported. Also, fix some misplaced parameters in printf. Modified from Seb Fagard's downstream patch Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01imx8: ahab: fix some bad debug message formatingSeb Fagard
In SPL build, the formatting '%llx' in debug() is not supported. Also, fix some misplaced parameters in printf. Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Seb Fagard <sebastien.fagard@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01imx8: ahab: fix 'end address' parameter of rm_find_memregPeng Fan
parameter 'end address' must be inclusive of address range. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01imx8: Change to use new SECO API commandsYe Li
Latest SCFW has removed old MISC SECO commands. So update the codes to use new SECO commands. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-05-01imx8: parser: fix 'end address' parameter of rm_find_memregPeng Fan
parameter 'end address' must be inclusive of address range. Modified from Seb's downstream patch. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01imx8m: Dump DRAM PLL rate by clocks commandYe Li
Add the dump of DRAM PLL into "clocks" command Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
2020-05-01imx8mq: Set ARM core clock directly from ARM PLLPeng Fan
For ARM core clock, there are two input branches, and can select via mux: one from ARM PLL directly, second from CCM A53 clock root. Currently we are using second branch. But IC confirmed the CCM A53 root signoff timing is 1Ghz, so we should switch to input from ARM PLL directly. This patch fixes the CORE SEL slice configuration and switch ARM clock to ARM PLL. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01imx8mq: Enable eMMC HS400 and SD UHS mode on EVKYe Li
iMX8MQ EVK board has a eMMC5.0 chip and supports SD3.0, so enable the UHS and HS400 configs to enhance the eMMC/SD access. The change also needs to set usdhc clock to 400Mhz, and add the off-on-delay-us to SD reset pin, otherwise some SD cards will fail to select UHS mode in re-initialization. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01imx8m: update clock root and fix core_selPeng Fan
Update clock root table to let it be easy to configure clock at very early stage. Also the core_sel mux parent should be A53 CLK root and ARM PLL. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01imx8m: acquire ATF commit hashPeng Fan
Acquire ATF commit hash when booting U-Boot to make user easy to know the ATF version. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01imx8: move SIP macro to common headerPeng Fan
Move the SIP macro to common header and unify the name to make others could reuse them. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01imx: update is_imx6ull to include i.MX6ULZPeng Fan
Update is_imx6ull helper to include i.MX6ULZ SoC. i.MX6ULZ could share same macro, then we no need to add is_imx6ulz in various drivers. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01imx: imx8m: add i.MX8MN variants supportPeng Fan
Add i.MX8MN variants support Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01imx: imx8m: add i.MX8MQ Dual and QuadLite supportPeng Fan
Add i.MX8MQ Dual and QuadLite variants. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01imx: cpu: support speed grade for i.MX8MPPeng Fan
i.MX8MP speed grade use same layout as i.MX8MN, so reuse it for i.MX8MP Reviewed-by: Ye Li <ye.li@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01imx8mn: Update speed gradePeng Fan
imx8mn speed grade fuse uses new definitions as below. So have to update get_cpu_speed_grade_hz function to match it. SPEED_GRADE[5:4] SPEED_GRADE[3:0] MHz xx 0000 2300 xx 0001 2200 xx 0010 2100 xx 0011 2000 xx 0100 1900 xx 0101 1800 xx 0110 1700 xx 0111 1600 xx 1000 1500 xx 1001 1400 xx 1010 1300 xx 1011 1200 xx 1100 1100 xx 1101 1000 xx 1110 900 xx 1111 800 Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-05-01imx8mm: Update CPU speed gradingYe Li
According to iMX8MM datasheet (IMX8MMIEC_Rev_D and IMX8MMCEC_Rev_D), the speed grading for imx8mm is 800Mhz, 1.2Ghz, 1.6Ghz and 1.8Ghz. Update them to get_cpu_speed_grade_hz function. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-05-01imx: fix cpu_type helperPeng Fan
i.MX8MP use 0x182 as its ID, so 0xff is not valid to get the cpu type, extend it to 0x1ff. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01ARM: imx: imx8mm: Add missing clock entries for FEC clockMarek Vasut
All the FEC ethernet clock entries for iMX8MM are missing, while they are already present on iMX8MQ. Fill in the nodes on iMX8MM, as the FEC ethernet gets bogus clock information otherwise which makes ethernet inoperable. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-04-30Merge tag 'efi-2020-07-rc2' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for UEFI sub-system for efi-2020-07-rc2 This pull request contains bug fixes needed due to the merged changes for EFI secure boot. Patches are supplied to identify EFI system partitions.
2020-04-30Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86Tom Rini
- DM ACPI support (Part A) - Improve support for chain-loading x86 U-Boot
2020-04-30Merge tag 'xilinx-for-v2020.07-rc2' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2020.07-rc2 mmc: - Fix dt property handling via generic function clk: - Fix versal watchdog clock setting nand: - Fix zynq nand command comparison xilinx: - Enable ubifs - Sync board_late_init configurations with initrd_high setup - Make custom distro boot more verbose zynq: - Kconfig alignments - Fix nand cse configuration zynqmp: - Fix zcu104 low level qspi configuration - Small DT updates Signed-off-by: Tom Rini <trini@konsulko.com>
2020-04-30Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini
- Add DM_ETH support for DPAA1, DPAA2 based RDB platforms: ls1046ardb, ls1043ardb, lx2160ardb, ls2088ardb, ls1088ardb. - Add GICv3 support for ls1028a, ls2088a, ls1088a. - Add lpuart support on ls1028aqds. - Few bug fixes and updates on ls2088a, ls1012a, ls1046a, ls1021a based platforms.
2020-04-30x86: Add documentation for the chain-load featureSimon Glass
Add a few notes about this feature, which is aimed for development. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30x86: Use the existing stack when chain-loadingSimon Glass
With chromebook_coral we normally run TPL->SPL->U-Boot. This is the 'bare metal' case. When running from coreboot we put u-boot.bin in the RW_LEGACY portion of the image, e.g. with: cbfstool image-coral.serial.bin add-flat-binary -r RW_LEGACY \ -f /tmp/b/chromebook_coral/u-boot.bin -n altfw/u-boot \ -c lzma -l 0x1110000 -e 0x1110000 In this case U-Boot is run from coreboot (actually Depthcharge, its payload) so we cannot access CAR. Use the existing stack instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30x86: Add a way to detect running from corebootSimon Glass
If U-Boot is running from coreboot we need to skip low-level init. Add an way to detect this and to set the gd flag. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30x86: Move coreboot-table detection into common codeSimon Glass
To support detecting booting from coreboot, move the code which locates the coreboot tables into a common place. Adjust the algorithm slightly to use a word comparison instead of string, since it is faster. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the comments to 960KB] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30board: Add a gd flag for chain loadingSimon Glass
When U-Boot is run from another boot loader, much of the low-level init needs to be skipped. Add a flag for this and adjust ll_boot_init() to use it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30pci: Avoid auto-config when chain loadingSimon Glass
When U-Boot is not the first-stage bootloader we don't want to re-configure the PCI devices, since this has already been done. Add a check to avoid this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30x86: cpu: Skip init code when chain loadingSimon Glass
When U-Boot is not the first-stage bootloader the interrupt and cache init must be skipped, as well as init for various peripherals. Update the code to add checks for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit (git 2.34.1) at 2025-02-11 05:31:24 +0000