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2013-05-31mtd: resync with Linux-3.7.1Sergey Lapin
This patch is essentially an update of u-boot MTD subsystem to the state of Linux-3.7.1 with exclusion of some bits: - the update is concentrated on NAND, no onenand or CFI/NOR/SPI flashes interfaces are updated EXCEPT for API changes. - new large NAND chips support is there, though some updates have got in Linux-3.8.-rc1, (which will follow on top of this patch). To produce this update I used tag v3.7.1 of linux-stable repository. The update was made using application of relevant patches, with changes relevant to U-Boot-only stuff sticked together to keep bisectability. Then all changes were grouped together to this patch. Signed-off-by: Sergey Lapin <slapin@ossfans.org> [scottwood@freescale.com: some eccstrength and build fixes] Signed-off-by: Scott Wood <scottwood@freescale.com>
2013-05-22nand/fsl_ifc: Convert to self-initPrabhakar Kushwaha
Convert NAND IFC driver to support CONFIG_SYS_NAND_SELF_INIT. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2013-05-22mtd: nand: use ssize_t instead of size_t to prevent infinite loophtbegin
When a all 0xFF buffer is passed to drop_ffs, the no-0xFF check loop will loop forever. After the fix, If ssize_t i = -1 and size_t l = i + 1, the value of l will still be 0 as expected. Signed-off-by: Tao Hou <hotforest@gmail.com> Cc: Ben Gardiner <bengardiner@nanometrics.ca> Cc: Scott Wood <scottwood@freescale.com>
2013-05-22mtd: nand: fix the partial page write conditionhtbegin
When writelen is mtd->writesize - 1, it is still a partial page write Signed-off-by: Tao Hou <hotforest@gmail.com> Cc: Scott Wood <scottwood@freescale.com>
2013-05-22nand: adjust erase/read/write partition/chip size for bad blocksHarvey Chapman
Adjust the sizes calculated for whole partition/chip operations by removing the size of bad blocks so we don't try to erase/read/write past a partition/chip boundary. Signed-off-by: Harvey Chapman <hchapman@3gfp.com>
2013-05-22nand/fsl_elbc: detect page size at runtimeScott Wood
This avoids needing a separate U-Boot config when some revisions of a board have small-page NAND and other revisions have large-page NAND (except for NAND SPL targets). CONFIG_FSL_ELBC_FMR is removed -- it was never used nor documented, and it gets in the way of this change. Signed-off-by: Scott Wood <scottwood@freescale.com>
2013-05-17Update MAINTAINERS file for sandboxSimon Glass
This currently has no maintainer listed. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-05-17Update MAINTAINERS file for x86Simon Glass
This still shows the previous maintainer. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-05-17.gitignore: add GNU GLOBAL filesMasahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-05-17fdt_support: Use CONFIG_NR_DRAM_BANKS if definedDoug Anderson
It appears that there are some cases where we have more than 4 banks of memory. Use CONFIG_NR_DRAM_BANKS if it's defined to handle this. This will take up a little extra stack space (64 bytes extra if we go up to 8 banks), but that seems OK. Signed-off-by: Doug Anderson <dianders@chromium.org>
2013-05-17bootm: Avoid 256-byte overflow in fixup_silent_linux()Doug Anderson
This makes fixup_silent_linux() use malloc() to allocate its working space, meaning that our maximum kernel command line should only be limited by malloc(). Previously it was silently overflowing the stack. Note that nothing about this change increases the kernel's maximum command line length. If you have a command line that is >256 bytes it's up to you to make sure that kernel can handle it. Signed-off-by: Doug Anderson <dianders@chromium.org> Acked-by: Mike Frysinger <vapier@gentoo.org>
2013-05-16README: Correct reference for CONFIG_SUPPORT_RAW_INITRDTom Rini
Signed-off-by: Tom Rini <trini@ti.com>
2013-05-15powerpc/esdhc: Correct judgement for DATA PIO modeHaijun.Zhang
The logic for the whether to configure for polling or DMA was mistakenly reversed in this patch: Commit 7b43db92110ec2f15c5f7187a165f2928464966b drivers/mmc/fsl_esdhc.c: fix compiler warnings Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> CC: Sun Yusong-R58495 <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-15mmc: update Faraday FTSDC010 for rw performanceKuo-Jung Su
Faraday FTSDC010 is a MMC/SD host controller. Although there is already a driver in current u-boot release, which is modified from eSHDC and contributed by Andes Tech. Its performance is too terrible on Faraday A36x SoC platforms, so I turn to implement this new version of driver which is 10+ times faster than the old one. It's carefully designed to be compatible with Andes chips, so it should be safe to replace it. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> CC: Andy Fleming <afleming@gmail.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-15Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xxTom Rini
2013-05-15Power: remove support for Freescale MPC8220Wolfgang Denk
The Freescale MPC8220 Power Architecture processors have long reached EOL; Freescale does not even list these any more on their web site. Remove the code to avoid wasting maitaining efforts on dead stuff. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Andy Fleming <afleming@gmail.com>
2013-05-15doc/README.scrapyard: add missing commit IDsWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2013-05-15drivers/mmc: move spl_mmc.c to common/splYing Zhang
The mpc85xx repuires a special layout on the memory device that is connected to the eSDHC controller interface. But the file spl_mmc.c didn't handle this specfic case, there needs a special treatmen, in the powerpc drictory. So, there is no longer to keep spl_mmc.c on mpc85xx, CONFIG_SPL_FRAMEWORK is not set. When CONFIG_SPL_MMC_SUPPORT is set and CONFIG_SPL_FRAMEWORK is not set, there was an error in drivers/mmc/spl_mmc.c: drivers/mmc/libmmc.o:(.got2+0x8): undefined reference to `spl_image'. Now, the solution is to move the file "spl_mmc.c" to directory "common/spl". Signed-off-by: Ying Zhang <b40530@freescale.com>
2013-05-15smc911x: fix the timeout detectionMasahiro Yamada
If timeout is occurred at the while loop above, the value of 'timeout' is -1, not 0. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-05-15doc/README.ubi: Add description of accessing ubi filesystemsPaul B. Henson
Signed-off-by: "Paul B. Henson" <henson@acm.org>
2013-05-14T4240/eth: fix SGMII card PHY addressShaohui Xie
QSGMII card assumed to be used by default, but if SGMII card is used, it will use different PHY address, but we don't know which card is used until we access PHY on the card. So we check the card type slot by slot, if we can read a PHY ID by reading a SGMII PHY address on a slot, then the slot must have a SGMII card pluged, we mark all ports on that slot, and fix dts to use the SGMII card PHY address when doing dts fixup for the marked ports. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14powerpc/t4qds: Fix disabling remote I2C connectionEd Swarthout
Only clear IRE bit in qixis brdcfg5 register and keep other bits unchanged. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14powerpc/b4860qds: Assign DDR address in board fileYork Sun
B4860QDS requires DDRC2 has 0 as base address and DDRC1 has higher address. This is the requirement for DSP cores to run in 32-bit address space. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14powerpc/mpc8xxx: Allow board file to override DDR address assignmentYork Sun
This gives boards flexibility to assign other than default addresses to each DDR controller. For example, DDR controler 2 can have 0 as the base and DDR controller 1 has higher memory. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14powerpc/mpc85xx: Update workaround for DDR erratum A-004934York Sun
The workaround has been updated to use a slightly different magic number. Change from 0x00003000 to 0x30003000. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14T4/usb: move usb 2.0 utmi dual phy init code to cpu_init.cRoy Zang
This is what we have done for the UTMI PHY on P3041/P5020. Then the PHY initialization can be reused in kernel without “usb start” command. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14T4240/net: use QSGMII card PHY address by defaultShaohui Xie
Use QSGMII card PHY address as default SGMII card PHY address, QSGMII card PHY address is variable depends on different slot. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14net/phy: add VSC8574 supportShaohui Xie
The VSC8574 is a quad-port Gigabit Ethernet transceiver with four SerDes interfaces for quad-port dual media capability. This driver supports SGMII and QSGMII MAC mode. For now SGMII mode is tested. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14powerpc/85xx: fix build error introduced by serdes_get_prtclShengzhou Liu
Removed unused declare serdes_get_prtcl() which was no longer needed. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14net/fm: fixup ethernet for mEMACShengzhou Liu
- set proper compatible property name for mEMAC. - fixed ft_fixup_port for dual-role mEMAC, which will lead to MAC node disabled incorrectly. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14t4240qds/eth: fixup ethernet for t4240qdsShengzhou Liu
1, Implemented board_ft_fman_fixup_port() to fix port for kernel. 2, Implemented fdt_fixup_board_enet() to fix node status of different slots and interfaces. 3, Adding detection of slot present for XGMII interface. 4, There is no PHY for XFI, so removed related phy address settings. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14powerpc/85xx: add missing QMAN frequency calculationShaohui Xie
When CONFIG_SYS_FSL_QORIQ_CHASSIS2 is not defined, QMAN frequency will not be initialized, and QMAN will have a wrong frequency display. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14powerpc: Add T4160QDSYork Sun
T4160QDS shares the same platform as T4240QDS. T4160 is a low power version of T4240, with eight e6500 cores, two DDR3 controllers, and slightly different SerDes protocols. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14powerpc/t4240qds: Move SoC define into boards.cfgYork Sun
Separate CONFIG_PPC_T4240 from board config file. Prepare to add more SoC variants supported on the same board. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14powerpc/mpc85xx: Add T4160 SoCYork Sun
T4160 SoC is low power version of T4240. The T4160 combines eight dual threaded Power Architecture e6500 cores and two memory complexes (CoreNet platform cache and DDR3 memory controller) with the same high-performance datapath acceleration, networking, and peripheral bus interfaces. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14powerpc/t4240: Fix SerDes protocol arrays with const prefixYork Sun
Protocols are constants. Fix arrays with const prefix. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14powerpc/mpc85xx: Fix PIR parsing for chassis2York Sun
The PIR parsing algorithm we used is not only for E6500. It applies to all SoCs with chassis 2. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14powerpc/corenet2: Print SerDes protocol in decimalYork Sun
Use decimal and hexadecimal for protocol numbers. It helps to match with SoC user manual. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14T4/USB: Add USB 2.0 UTMI dual phy supportRoy Zang
T4240 internal UTMI phy is different comparing to previous UTMI PHY in P3041. This patch adds USB 2.0 UTMI Dual PHY new memory map and enable it for T4240. The phy timing is very sensitive and moving the phy enable code to cpu_init.c will not work. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14powerpc/t4240qds: Add voltage ID supportYork Sun
T4240 has voltage ID fuse. Read the fuse and configure the voltage correctly. Core voltage has higher tolerance on over side than below. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14powerpc/mpc85xx: Fix portal setupYork Sun
Missing nodes of crypto, pme, etc in device tree is not a fatal error. Setting up the qman portal should skip the missing node and continue to finish the rest. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14powerpc/mpc8xxx: Fix DDR 3-way interleavingYork Sun
Should check if interleaving is enabled before using interleaving mode. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14powerpc/t4240qds: Update DDR timing tableYork Sun
Update the timing table to support more rank density, based on the theory that similar density DIMMs have similar clock adjust and write level start timing. Update the timing for 1600 and 1866 MT/s. Tested with Micron MT18JSF1G72AZ-1G9E1 DIMMs, iDIMM M3CN-4GMJ3C0C-M92. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14T4/SerDes: correct the SATA indexRoy Zang
Lane H on SerDes4 should be SATA2 instead of SATA1 Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14Fman/t4240: some fix for 10G XAUIShaohui Xie
1. fix 10G mac offset by plus 8; 2. add second 10G port info for FM1 & FM2 when init ethernet info; 3. fix 10G lanes name to match lane protocol table; Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14powerpc/t4240qds: fix XAUI card PHY addressShaohui Xie
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14T4/serdes: fix the serdes clock frequencyRoy Zang
Reverse the bit sequence to set and display serdes clock frequency correctly. The correct bit maps in BRDCFG2 are 0 1 2 3 4 5 6 7 S1RATE[1:0] S2RATE[1:0] S3RATE[1:0] S4RATE[1:0] Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14e6500: Move L1 enablement after L2 enablementAndy Fleming
The L1 D-cache on e6500 is write-through. This means that it's not considered a good idea to have the L1 up and running if the L2 is disabled. We don't actually *use* the L1 until after the L2 is brought up on e6500, so go ahead and move the L1 enablement after that code is done. Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14powerpc/t4240qds: Fix SPI flash typeShaohui Xie
T4240QDS uses a SST instead of SPANSION SPI flash. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14powerpc/mpc85xx: Update corenet global utility block registersYork Sun
Fix ccsr_gur for corenet platform. Remove non-exist registers. Add fuse status register. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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